IEC 60424-5:2009

Ferrite cores - Guide on the limits of surface irregularities - Part 5: Planar-cores

IEC 60424-5:2009 gives guidance on allowable limits of surface irregularities applicable to planar-cores in accordance with the relevant generic specification. This standard is considered as a sectional specification useful in the negotiation between ferrite core manufacturers and users about surface irregularities.

Noyaux de ferrite - Guide relatif aux limites des irrégularités de surface - Partie 5: Noyaux planaires

La CEI 60424-5:2009 donne des lignes directrices relatives aux limites admissibles pour les irrégularités de surface applicables aux noyaux planaires conformément à la spécification générique applicable. La présente norme est considérée comme une spécification intermédiaire utile dans les négociations entre fabricants et utilisateurs de noyaux de ferrite concernant les irrégularités de surface.

General Information

• Status: Replaced
• Publication Date: 25-Feb-2009
• ICS: 29.100.10 - Magnetic components
• Technical Committee: TC 51 - Magnetic components, ferrite and magnetic powder materials
• Drafting Committee: WG 1 - TC 51/WG 1
• Current Stage: DELPUB - Deleted Publication
• Start Date: 28-Jun-2019
• Completion Date: 16-Apr-2020

Relations

• Replaced By: IEC 63093-9:2020 - Ferrite cores - Guidelines on dimensions and the limits of surface irregularities - Part 9: Planar cores
• Effective Date: 05-Sep-2023

Standards Content (Sample)

IEC 60424-5


®

Edition 1.0 2009-02



INTERNATIONAL



STANDARD





Ferrite cores – Guide on the limits of surface irregularities –
Part 5: Planar-cores



IEC 60424-5:2009(E)

---------------------- Page: 1 ----------------------
THIS PUBLICATION IS COPYRIGHT PROTECTED

Copyright © 2009 IEC, Geneva, Switzerland



All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form

or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from
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If you have any questions about IEC copyright or have an enquiry about obtaining additional rights to this publication,

please contact the address below or your local IEC member National Committee for further information.



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Switzerland
Email: [e-mail]
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About the IEC
The International Electrotechnical Commission (IEC) is the leading global organization that prepares and publishes
International Standards for all electrical, electronic and related technologies.

About IEC publications
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latest edition, a corrigenda or an amendment might have been published.
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---------------------- Page: 2 ----------------------
IEC 60424-5


®

Edition 1.0 2009-02



INTERNATIONAL



STANDARD





Ferrite cores – Guide on the limits of surface irregularities –
Part 5: Planar-cores

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
PRICE CODE
N
ICS 29.100.10 ISBN 978-2-88910-190-0
® Registered trademark of the International Electrotechnical Commission

---------------------- Page: 3 ----------------------
– 2 – 60424-5 © IEC:2009(E)



CONTENTS

FOREWORD.3


1 Scope.5

2 Normative references .5

3 Limits of surface irregularities.6


3.1 Chips and ragged edges.6

3.1.1 Chips and ragged edges on the mating surfaces (see Figures 1, 2

and 3).6

3.1.2 Chips and ragged edges on other surfaces.7
3.2 Cracks.10
3.3 Flash.10
3.4 Pull-out .10

Figure 1 – Chip location for planar EL-core.6
Figure 2 – Chip location for low profile E-core.6
Figure 3 – Chip location for low profile ER-core .6
Figure 4 – Cracks and pull-out location for planar EL-core .10
Figure 5 – Cracks and pull-out location for low profile E-core.11
Figure 6 – Cracks and pull-out location for low profile ER-core .11
Figure 7 – Reference dimensions for EL-core .11
Figure 8 – Reference dimensions for E-core .12
Figure 9 – Reference dimensions for ER-core.13

2
Table 1 – Allowable areas of chips in mm for planar EL-core.7
2
Table 2 – Allowable areas of chips in mm for low profile E-core .8
2
Table 3 – Allowable areas of chips in mm for low profile ER-core .8
Table 4 – Area and length reference for visual inspection .9
Table 5 – Limits of cracks for planar EL-core .12
Table 6 – Limits of cracks for low profile E-core.13
Table 7 – Limits of cracks for low profile ER-core .14

---------------------- Page: 4 ----------------------
60424-5 © IEC:2009(E) – 3 –


INTERNATIONAL ELECTROTECHNICAL COMMISSION

____________



FERRITE CORES –

GUIDE ON THE LIMITS OF SURFACE IRREGULARITIES –



Part 5: Planar-cores





FOREWORD

1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of the IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC
Publication(s)“). Their preparation is entrusted to technical committees; any IEC National Committee interested
in the subject dealt with may participate in this preparatory work. International, governmental and non-
governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely
with the International Organization for Standardization (ISO) in accordance with conditions determined by
agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence
between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
the latter.
5) IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with an IEC Publication.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60424-5 has been prepared by IEC technical committee 51:
Magnetic components and ferrite materials.
The text of this standard is based on the following documents:
FDIS Report on voting
51/947/FDIS 51/950/RVD

Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all parts of the IEC 60424 series, under the general title Ferrite cores – Guide on the
limits of surface irregularities, can be found on the IEC website.

---------------------- Page: 5 ----------------------
– 4 – 60424-5 © IEC:2009(E)


The committee has decided that the contents of this publication will remain unchanged until

the maintenance result date indicated on the IEC web site under "http://webstore.iec.ch" in

the data related to the specific publication. At this date, the publication will be


• reconfirmed,

• withdrawn,

• replaced by a revised edition, or

• amended.


A bilingual version of this publication may be issued at a later date.

---------------------- Page: 6 ----------------------
60424-5 © IEC:2009(E) – 5 –


FERRITE CORES –

GUIDE ON THE LIMITS OF SURFACE IRREGULARITIES –



Part 5: Planar-cores








1 Scope


This part of IEC 60424 gives guidance on allowable limits of surface irregularities applicable
to planar-cores in accordance with the relevant generic specification defined in IEC 60424-1.
The relations between the main dimensions of planar E-, ER- and EL-cores differ from those
of standard cores. For example, the width of planar cores is larger while the total height is
much smaller. Also the thickness of the legs is in most cases smaller than compared to
standard cores. Therefore the concept of fixed reference dimensions to determine the length
of crack limits yield crack lengths which are not acceptable for this type of core. This part of
IEC 60424 follows another concept which relates the crack length to dimensions of the
surface on which the crack occurs.
Al
...

IEC 60424-5


®

Edition 1.0 2009-02



INTERNATIONAL



STANDARD



NORME
INTERNATIONALE


Ferrite cores – Guide on the limits of surface irregularities –
Part 5: Planar-cores

Noyaux de ferrite – Guide relatif aux limites des irrégularités de surface –
Partie 5: Noyaux planaires


IEC 60424-5:2009

---------------------- Page: 1 ----------------------
THIS PUBLICATION IS COPYRIGHT PROTECTED


Copyright © 2009 IEC, Geneva, Switzerland

All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form or by

any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from either IEC or

IEC's member National Committee in the country of the requester.
If you have any questions about IEC copyright or have an enquiry about obtaining additional rights to this publication,
please contact the address below or your local IEC member National Committee for further information.



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publication, utilisez les coordonnées ci-après ou contactez le Comité national de la CEI de votre pays de résidence.

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International Standards for all electrical, electronic and related technologies.

About IEC publications
The technical content of IEC publications is kept under constant review by the IEC. Please make sure that you have the
latest edition, a corrigenda or an amendment might have been published.
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---------------------- Page: 2 ----------------------
IEC 60424-5


®

Edition 1.0 2009-02



INTERNATIONAL



STANDARD



NORME
INTERNATIONALE


Ferrite cores – Guide on the limits of surface irregularities –
Part 5: Planar-cores

Noyaux de ferrite – Guide relatif aux limites des irrégularités de surface –
Partie 5: Noyaux planaires


INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
N
CODE PRIX
ICS 29.100.10 ISBN 978-2-88910-190-0
® Registered trademark of the International Electrotechnical Commission
Marque déposée de la Commission Electrotechnique Internationale

---------------------- Page: 3 ----------------------
– 2 – 60424-5 © IEC:2009



CONTENTS

FOREWORD.3


1 Scope.5

2 Normative references .5

3 Limits of surface irregularities.6


3.1 Chips and ragged edges.6

3.1.1 Chips and ragged edges on the mating surfaces (see Figures 1, 2

and 3).6

3.1.2 Chips and ragged edges on other surfaces.7
3.2 Cracks.10
3.3 Flash.10
3.4 Pull-out .10

Figure 1 – Chip location for planar EL-core.6
Figure 2 – Chip location for low profile E-core.6
Figure 3 – Chip location for low profile ER-core .6
Figure 4 – Cracks and pull-out location for planar EL-core .10
Figure 5 – Cracks and pull-out location for low profile E-core.11
Figure 6 – Cracks and pull-out location for low profile ER-core .11
Figure 7 – Reference dimensions for EL-core .11
Figure 8 – Reference dimensions for E-core .12
Figure 9 – Reference dimensions for ER-core.13

2
Table 1 – Allowable areas of chips in mm for planar EL-core.7
2
Table 2 – Allowable areas of chips in mm for low profile E-core .8
2
Table 3 – Allowable areas of chips in mm for low profile ER-core .8
Table 4 – Area and length reference for visual inspection .9
Table 5 – Limits of cracks for planar EL-core .12
Table 6 – Limits of cracks for low profile E-core.13
Table 7 – Limits of cracks for low profile ER-core .14

---------------------- Page: 4 ----------------------
60424-5 © IEC:2009 – 3 –


INTERNATIONAL ELECTROTECHNICAL COMMISSION

____________



FERRITE CORES –

GUIDE ON THE LIMITS OF SURFACE IRREGULARITIES –



Part 5: Planar-cores





FOREWORD

1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of the IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,
Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC
Publication(s)“). Their preparation is entrusted to technical committees; any IEC National Committee interested
in the subject dealt with may participate in this preparatory work. International, governmental and non-
governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely
with the International Organization for Standardization (ISO) in accordance with conditions determined by
agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence
between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in
the latter.
5) IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with an IEC Publication.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60424-5 has been prepared by IEC technical committee 51:
Magnetic components and ferrite materials.
This bilingual version, published in 2009-07, corresponds to the English version.
The text of this standard is based on the following documents:
FDIS Report on voting
51/947/FDIS 51/950/RVD

Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
The French version of this standard has not been voted upon.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.

---------------------- Page: 5 ----------------------
– 4 – 60424-5 © IEC:2009


A list of all parts of the IEC 60424 series, under the general title Ferrite cores – Guide on the

limits of surface irregularities, can be found on the IEC website.


The committee has decided that the contents of this publication will remain unchanged until

the maintenance result date indicated on the IEC web site under "http://webstore.iec.ch" in

the data related to the specific publication. At this date, the publication will be


• reconfirmed,

• withdrawn,

• replaced by a revised edition, or

• amended.

---------------------- Page: 6 ----------------------
60424-5 © IEC:2009 – 5 –


FERRITE CORES –

GUIDE ON THE LIMITS OF SURFACE IRREGULARITIES –



Part 5: Planar-cores








1 Scope


This part of IEC 60424 gives guidance on allowable limits of surface irregularities applicable
to planar-cores in accordance with the relevant generic specification defined in IEC 60424-1.
The relations between the main dimensions of planar E-, ER- and EL-cores differ from those
of standard cores. For example, the width of planar cores is larger while the total height is
much smaller. Also the thickness of the legs is in most cases smaller than compared to
standard cores. Therefore the concept of fixed reference dimensions to determine the length
of crack limits yield crack lengths which are not acceptable for this type of core. This part of
IEC 60424 follows another concept which relates the crack length to dimensions of the
surface on which the crack occurs.
Also the concept to determine the maximum area of chips based on the total mating surface
fails in the case of planar cores. The outer legs of planar cores are much thinner than those of
standard cores which makes overlapping and gluing much more difficult. A single chip of
maximum size on the outer leg may risk the functionality of the core set. Therefore this
standard uses as a reference the mating surface on which the chip occurs.
Windings of planar cores are often PCBs which are glued to the inner surfaces of the planar
core. For this reason the inner surfaces of the planar cores need to have a better quality than
the inner surfaces of standard cores. This was taken into account by reducing the maximum
allowable area of pull outs in the inner surfaces.
This standard is considered as a sectional specification useful in the negotiation between
ferrite core manufacturers and users about surface irregularities.
2 Normative references
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document (including any amendments) applies.

IEC 60424-1, Ferrite cores – Guide on the limits of surface irregularities – Part 1: General
specification
IEC 62317-9, Ferrite cores – Dimensions – Part 9: Planar cores

---------------------- Page: 7 ----------------------
– 6 – 60424-5 © IEC:2009



3 Limits of surface irregularities


3.1 Chips and ragged edges


3.1.1 Chips and ragged edges on the mating surfaces (see Figures 1, 2 and 3)


Mating surfaces

C1′



C1
Ragged edges
IEC  360/09

Figure 1 – Chip location for planar EL-core

Mating surfaces
C1′
C2
C1
Ragged edges
IEC  361/09

Figure 2 – Chip location for low profile E-core

Mating surfaces
C1′
C2

Wire slot area
C1
Ragged edges
IEC  362/09

Figure 3 – Chip location for low profile ER-core
Areas of the chips located on the mating surfaces (C1 and C1’ irregularities in Figures 1, 2
and 3) shall not exceed the following limits:
– the cumulative area of the chips shall be less than 4 % of the relevant mating surface. The
mating surface of each outer leg and centre post is considered separately; the allowable
areas are rounded to the figures in Table 4 (Area and length reference for visual
2
inspection) and the minimum allowable area is taken as 0,5 mm to be distinguishable to
the naked eye;

---------------------- Page: 8 ----------------------
60424-5 © IEC:2009 – 7 –


– the total area of all chips on all mating surfaces shall not exceed the value given for

“overall chipping on the mating surface” in Tables 1, 2 or 3;


– the total length of the ragged edges shall be less than 25 % of the perimeter of the

relevant mating surface.


3.1.2 Chips and ragged edges on other surfaces


– the allowable chipping areas are doubled as compared to the limits for the whole mating

surfaces (see Table 1 for planar EL-cores, Table 2 for low profile E-cores, Table 3 for low

profile ER-cores);

– the total length of the ragged edges shall be less than 25 % of the perimeter of the smaller
adjoining surface;
– chips and ragged edges are not acceptable on the ridge of the clamping recess area;
– chips and ragged edges are not acceptable on the inner edges of wire slot area
(C2 irregularity in Figures 2 and 3).
The core sizes given in Tables 1, 2 and 3 correspond to the cores defined in IEC 62317-9,
and area and length reference for visual inspection are given in Table 4.
2
Table 1 – Allowable areas of chips in mm for planar EL-core
Chipping on mating Chipping on mating
Overall chipping on
Core size surface of one outer surface of centre Other surfaces
mating surface
leg post
EL 11 × 2,0 0,5 0,5 1,5 3,0
EL 11 × 3,0 0,5 0,5 1,5 3,0
EL 13 × 2,2 0,5 1,0 2,0 4,0
EL 13 × 3,2 0,5 1,0 2,0 4,0
EL 15,5 × 2,9 0,5 1,0 2,0 4,0
EL 15,5 × 4,4 0,5 1,0 2,0 4,0
EL 18 × 3,7 1,0 2,0 4,0 8,0
EL 18 × 5,7 1,0 2,0 4,0 8,0
EL 20 × 3,8 1,0 2,0 4,0 8,0

EL 20 × 5,8 1,0 2,0 4,0 8,0
EL 22 × 4,0 1,5 2,5 5,5 11,0
EL 22 × 6,0 1,5 2,5 5,5 11,0
EL 25 × 4,3 1,5 3,5 6,5 13,0
EL 25 × 6,3 1,5 3,5 6,5 13,0

---------------------- Page: 9 ----------------------
– 8 – 60424-5 © IEC:2009


2
Table 2 – Allowable areas of chips in mm for low profile E-core



Chipping on mating Chipping on mating
Overall chipping on
Core size surface of one outer surface of centre Other surfaces

mating surface
leg post


E 14 × 3,5 × 5 0,5 0,5 1,5 3,0

E 18 × 4 × 10 1,0 1,5 3,5 7,0

E 22 × 6 × 16 1,5 3,0 6,0 12,0

E 32 × 6 × 20 2,5 5,0 10,0 20,0

E 38 × 8 × 25 3,5 8,0 15,0 30,0
E 43 × 10 × 28 4,5 9,0 18,0 36,0
E 58 × 11 × 38 6,0 12,5 24,5 49,0
E 64 × 10 × 50 10,0 20,0 40,0 80,0
E 102 × 20 × 38 12,5 20,0 45,0 90,0

2
Table 3 – Allowable areas of chips in mm for low profile ER-core
Chipping on mating Chipping on mating
Overall chipping on
Core size surface of one outer surface of centre Other surfaces
mating surface
leg post
ER 9,5 × 2,5 × 5 0,5 0,5 1,5 3,0
ER 11 × 2,5 × 6 0,5 0,5 1,5 3,0
ER 13 × 3 × 9 0,5 1,0 2,0 4,0
ER 14,5 × 3 × 7 0,5 1,0 2,0 4,0
ER 18 × 3 × 10 0,5 1,0 2,0 4,0
ER 20 × 6 × 14 1,5 2,0 5,0 10,0
ER 23 × 3,6 × 13 1,0 2,0 4,0 8,0
ER 23 × 5 × 13 1,0 2,0 4,0 8,0
ER 25 × 6 × 15 1,5 3,0 6,0 12,0
ER 30 × 8 × 20 2,5 4,0 9,0 18,0
ER 32 × 5 × 21 2,0 4,0 8,0 16,0

ER 32 × 6 × 25 2,5 5,0 10,0 20,0
ER 35 × 10 × 26 3,5 7,0 14,0 28,0
ER 40 × 10 × 28 4,0 7,0 15,0 30,0

---------------------- Page: 10 ----------------------
60424-5 © IEC:2009 – 9 –


Table 4 – Area and length reference for visual inspection


Area
AB C D E Area AB C
DE


2 2
0,5 mm 12,5 mm


2

1,0 mm

2
15,0 mm

2
1,5 mm
2
2,0 mm
2
17,5 mm
2
2,5 mm
2
20,0 mm
2
3,0 mm
2
2
3,5 mm
25,0 mm
2
4,0 mm
2
30,0 mm
2
4,5 mm
2
2
5,0 mm
35,0 mm
2
6,0 mm
2
40,0 mm
2
7,0 mm
2
2
8,0 mm

45,0 mm
2
9,0 mm
2
50,0 mm
2
10,0 mm
Scale 1:1
1 mm 2 mm 3 mm 4 mm
5 mm 7,5 mm 10 mm
IEC  674/99

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3.2 Cracks


Different cracks are shown in Figures 4, 5 and 6. In principle three different types of cracks

can be distinguished.


a) Cracks which are parallel to the magnetic flux path (S1, S2, S5, S5’, S5’’). These

cracks are magnetically not critical. The maximum length of a single crack is 33 % (1/3)

of the dimension of the relevant surface which is parallel to the crack. In the case of

multiple cracks the maximum cumulative length doubles.


b) Cracks which are perpendicular to the magnetic flux path (S3, S3’, S3’’, S4, S4’).

These cracks are magnetically critical. They may reduce the relative cross-section of
the magnetic flux or add an additional air gap into the magnetic circuit. The maximum
total length of cracks is 20 % (1/5) of the dimension of the relevant surface which is
parallel to the crack.
c) Cracks which go from one edge to another edge (S6). These cracks may cause
chipping during the operation in the circuit. The loose particles may cause
malfunctions in the circuit. Therefore this type of crack is not acceptable in any case.
The limits for cracks are given in Tables 5, 6 and 7.
3.3 Flash
There shall be no flash extending from the core into the wire slot.
3.4 Pull-out
The pull-outs are applicable only for the inner surface where the PCB is seated (as shown in
Figures 4, 5 and 6).
For planar EL-cores, low profile E-cores and low profile ER-cores, the cumulative area of pull-
outs of the core shall be less than 20 % of the total respective surface area.

S1 S5″
S3
S3″
S2
S5
Pull-out

S4′
S5′
S4
S6
IEC  363/09

Figure 4 – Cracks and pull-out location for planar EL-core

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60424-5 © IEC:2009 – 11 –



S1

S3
S5″

S2
S3″

S5


S3′
Pull-out


S5′
S6

S4′
S4
IEC  364/09




Figure 5 – Cracks and pull-out location for low profile E-core


S5″

S1
S3″
S3
S2

S5
Pull-out
S4′
S5′
S6
S4
IEC  365/09

Figure 6 – Cracks and pull-out location for low profile ER-core


D
F
2
R  8 places
2
R R
1 1

F
2
R =
1
B C
1
2
IEC  366/09

Figure 7 – Reference dimensions for EL-core
F
1
E
A

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Table 5 – Limits of cracks for planar EL-core

1 2
Limits for single crack Limits for multiple cracks
Type Reference dimension

S1 F 33 % (1/3) of reference dim. 66 % (2/3) of reference dim.
1

S2 (A-E)/2 33 % (1/3) of reference dim. 66 % (2/3) of reference dim.

S3 F 20 % (1/5) of reference dim. 20 % (1/5) of reference dim.

2

S3’ F 20 % (1/5) of reference dim. 20 % (1/5) of reference dim.
1

S3’’ C 20 % (1/5) of reference dim. 20 % (1/5) of reference dim.


S4 B – D 20 % (1/5) of reference dim. 20 % (1/5) of reference dim.
1
S4’ B – D 20 % (1/5) of reference dim. 20 % (1/5) of reference dim.
1
S5 B 33 % (1/3) of reference dim. 66 % (2/3) of reference dim.
1
A
S5’ 33 % (1/3) of reference dim. 66 % (2/3) of reference dim.
S5” A 33 % (1/3) of reference dim. 66 % (2/3) of reference dim.
S6 Multiple edges No cracks allowed
1
See Figure 4.
2
See Figure 7.


B
1
C
D
IEC  367/09

Figure 8 – Reference dimensions for E-core

A
F
E

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Table 6 – Limits of cracks for low profile E-core

1 2
Limits for single crack Limits for multiple cracks
Type Reference dimension


S1 F 33 % (1/3) of reference dim. 66 % (2/3) of reference dim.

S2 (A-E)/2 33 % (1/3) of reference dim. 66 % (2/3) of reference dim.

S3 C 20 % (1/5) of reference dim. 20 % (1/5) of reference dim.

S3’ F 20 % (1/5) of reference dim. 20 % (1/5) of reference dim.


S3’’ C 20 % (1/5) of reference dim. 20 % (1/5) of reference dim.

S4 B – D 20 % (1/5) of reference dim. 20 % (1/5) of reference dim.
1

S4’ 20 % (1/5) of reference dim. 20 % (1/5) of reference dim.
B – D
1
S5 B 33 % (1/3) of reference dim. 66 % (2/3) of reference dim.
1
S5’ A 33 % (1/3) of reference dim. 66 % (2/3) of reference dim.
S5” A 33 % (1/3) of reference dim. 66 % (2/3) of reference dim.
S6 Multiple edges No cracks allowed
1
See Figure 5.
2
See Figure 8.


B
1
C
D
IEC  368/09

Figure 9 – Reference dimensions for ER-core

A
F
G
E

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Table 7 – Limits of cracks for low profile ER-core

1 2
Limits for single crack Limits for multiple cracks
Type Reference dimension

S1 F 33 % (1/3) of reference dim. 66 % (2/3) of reference dim.

S2 (A-G)/2 33 % (1/3) of reference dim. 66 % (2/3) of reference dim.

S3 F 20 % (1/5) of reference dim. 20 % (1/5) of reference dim.

 S3’’ C 20 % (1/5) of reference dim. 20 % (1/5) of reference dim.

S4 B – D 20 % (1/5) of reference dim. 20 % (1/5) of reference dim.
1

S4’ B – D 20 % (1/5) of reference dim. 20 % (1/5) of reference dim.
1

S5 B 33 % (1/3) of reference dim. 66 % (2/3) of reference dim.
1
S5’ A 33 % (1/3) of reference dim. 66 % (2/3) of reference dim.
S5” A 33 % (1/3) of reference dim. 66 % (2/3) of reference dim.
S6 Multiple edges No cracks allowed
1
See Figure 6.
2
See Figure 9.

_____________

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SOMMAIRE

AVANT PROPOS .17


1 Domaine d’application .19

2 Références normatives.19

3 Limites des irrégularités de surface .20


3.1 Eclats et angles ébréchés .20

3.1.1 Eclats et angles ébréchés sur les surfaces de contact (voir les

Figures 1, 2 et 3) .20

3.1.2 Eclats et angles ébréchés sur d’autres surfaces .21
3.2 Fissures .24
3.3 Bavure .24
3.4 Arrachement.24

Figure 1 – Emplacement des éclats pour les noyaux planaires EL .20
Figure 2 – Emplacement des éclats pour les noyaux E extra-plats .20
Figure 3 – Emplacement des éclats pour les noyaux ER extra-plats.20
Figure 4 – Emplacement des fissures et des arrachements pour le noyau planaire EL .24
Figure 5 – Emplacement des fissures et des arrachements pour le noyau E extra-plat.25
Figure 6 – Emplacement des fissures et des arrachements pour le noyau ER extra-plat .25
Figure 7 – Dimensions de référence pour le noyau EL .25
Figure 8 – Dimensions de référence pour le noyau E .26
Figure 9 – Dimensions de référence pour le noyau ER.27

2
Tableau 1 – Surfaces admissibles des éclats en mm pour le noyau planaire EL .21
2
Tableau 2 – Surfaces admissibles des éclats en mm pour le noyau E extra-plat.22
2
Tableau 3 – Surfaces admissibles des éclats en mm pour le noyau ER extra-plat .22
Tableau 4 – Référence de longueur et de surface pour l’examen visuel .23
Tableau 5 – Limites des fissures pour le noyau planaire EL .25
Tableau 6 – Limites des fissures pour le noyau E extra-plat.26
Tableau 7 – Limites des fissures pour le noyau ER extra-plat .27

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COMMISSION ÉLECTROTECHNIQUE INTERNATIONALE

____________



NOYAUX DE FERRITE –

GUIDE RELATIF AUX LIMITES

DES IRRÉGULARITÉS DE SURFACE –



Partie 5: Noyaux planaires





AVANT PROPOS
1) La CEI (Commission Électrotechnique Internationale) est une organisation mondiale de normalisation
composée de l'ensemble des comités électrotechniques nationaux (Comités nationaux de la CEI). La CEI a
pour objet de favoriser la coopération internationale pour toutes les questions de normalisation dans les
domaines de l'électricité et de l'électronique. A cet effet, la CEI, entre autres activités, publie des Normes
Internationales, des Spécifications Techniques, des Rapports Techniques, des Spécifications accessibles au
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comités d'études, aux travaux desquels tout Comité national intéressé par l
...