Information technology — Telecommunications and information exchange between systems — High-level data link control (HDLC) procedures — Frame structure

Technologies de l'information — Télécommunications et échange d'information entre systèmes — Procédure de commande de liaison de données à haut niveau (HDLC) — Structure de trame

General Information

Status
Withdrawn
Publication Date
12-Jun-1991
Withdrawal Date
12-Jun-1991
Current Stage
9599 - Withdrawal of International Standard
Start Date
23-Dec-1993
Completion Date
23-Dec-1993
Ref Project

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ISO 3309:1991 - Information technology -- Telecommunications and information exchange between systems -- High-level data link control (HDLC) procedures -- Frame structure
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ISO/IEC
I NTER NATIONAL
STANDARD
Fourth edition
1991 46-01
Information technology - Telecommunications
and information exchange between systems -
High-level data link control (HDLC)
procedures - Frame structure
Technologies de l'information - Télécommunications et échange
d'informafion entre systèmes - Procédure de commande de liaison de
données à haut niveau (HDLC) - Structure de frame
Reference number
ISOAEC 3309:1991(E)
---------------------- Page: 1 ----------------------
ISODEC 3309 : 1991 (E)
Contents Page

Introduction ................................................................................................................ .iv

1 scope ....................................................................................................................... 1

2 Normative reference ................................................................................................ 1

3 Basic frame sîructure ............................................................................................... 1

4 Elements of the frame .............................................................................................. 1

5 Extensions ............................................................................................................... 4

6 Addressing conventions ........................................................................................... 4

Annexes

A Explanatory notes on the implementation of the frame checking sequence ............ 6

0 iSO/IEC 1991

All riahts reserved. No Dart of this publication may be reproduced or utilized In any form

or byany means, electr'onlc or rnechanlcal, Including photocopying and microfilm, without

permission In writlng from the publisher.
ISOliEC Copyrlght Office Case Postale 56 CH-I211 Genève 20 Switzerland
Prlnted In Switzerland
---------------------- Page: 2 ----------------------
ISO/IEC 3309 : 1991 (E)
Foreword

IS0 (the International Organization for Standardization) and IEC (the international

Electrotechnical Commission) form the specialized system for worldwide standardiz-

ation. National bodies that are members of IS0 or IEC participate in the development

of International Standards through technical committees established by the respective

organization to deal with particular fields of technical activity. IS0 and IEC technical

committees collaborate in fields of mutual interest. Other international organizations,

governmental and non-governmental, in liaison with IS0 and IEC, also take part in the

work.

In the field of information technology, IS0 and IEC have established a joint technical

ISO/IEC JTC 1. Draft International Standards adopted by the joint
committee,

technical committee are circulated to national bodies for voting. Publication as an

International Standard requires approval by at least 75 Yo of the national bodies

casting a vote.
International Standard ISO/IEC 3309 was prepared by Joint Technical Committee
ISOAEC JTC 1, Information technology.

This fourth edition cancels and replaces the third edition (IS0 3309 : 1984), which has

been technically revised.
Annex A is for information only.
---------------------- Page: 3 ----------------------
ISO/IEC 3309 : 1991 (E)
Introduction

This Internationai Standard is one of a series to be used in the implementation of

various applications which utilize synchronous or start/stop transmission facilities.

---------------------- Page: 4 ----------------------
~~ ~
ISOAEC 3309 : 1991 (E)
INTERNATIONAL STANDARD
Information technology - Telecommunications and
information exchange between systems - High-level data
data link control (HDLC) procedures - Frame structure
Each frame consists of the following fields (transmission
1 Scope
sequence left to right):
This International Standard specifies the frame structure for
data communication systems using bit-oriented high-level
Fiag IAddresslControl~nformatio~ FCS I Flag
data link control (HDLC) procedures. It defines the relative

positions of the various components of the basic frame and 011111101 Sbits I8bits I * I16or32 bits 101 111 110

the bit combination for the frame delimiting sequence (flag).
* An unspecified number of bits which in some cases may be
The mechanisms used to achieve bit pattern independence
a multiple of a particular character size; for example, an octet.
(transparency) within the frame are also defined. In addition,
two frame checking sequences (FCS) are specified; the rules
where
for address field extension are defined; and the addressing
conventions available are described.
Flag = flag sequence
Control field encodmgs and formats are defined in other
Address = data station address field
Intemational Standards.
Control = control field
2 Normative reference
Information = information field
The following standard contains provisions which, through
reference in this text, constitute provision of this Intemational
FCS = frame checking sequence field
Standard. At the time of publication, the edition indicated
Frames containing only control sequences form a special case
was valid. All standards are subject to revision, and parties to
where there is no information field. The format for these
agreements based on this International Standard are
frames shall be
encouraged to investigate the possibility of applying the most
recent edition of the standard indicated below. Members of
Flag IAddresslControl] FCS I Flag
IEC and IS0 maintain registers of currently valid
01111110~ Sbits I Sbits ~16or32bits~01111110
I I I I I I
Intemational Standards.
IS0 2382/9 : 1984, Data processing - Vocabulary - Part
09: Da%a communication.
4 Elements of the frame
4.1 Flag sequence
3 Basic frame structure
All frames shall start and end with the flag sequence. All data
In HDLC, all transmissions are in frames. The basic frame
stations which are attached to the data link shall continuously
structure does not include bits inserted for bit-synchronization
hunt for this sequence. Thus, the flag is used for frame
(i.e., start or stop elements, see 4.7.2) or bits or octets inserted
synchronization. A single flag may be used as both the
for transparency (see 4.5).
closing flag for one frame and the opening flag for the next
frame.
---------------------- Page: 5 ----------------------
ISO/IEC 3309 : 1991 (E)
calculation, shall:
4.2 Address field
In command frames. the address shall identify the data
a) Upon the occurrence of the flag or a control escape
station(s) for which the command is intended. In response
octet, complement the 6th bit of the octet, and
frames. the address shall identify the data station from which
b) insert a control escape octet immediately preceding
the response originated.
the octet resulting Erom the above prior to transmission.
The receiver shall examine the frame content between the two
4.3 Control field
flag octets and shall, upon receipt of a control escape octet
The control field indicates the type of commands or
and prior to FCS calculation:
responses, and contains sequence numbers, where
a) Discard the control escape octet, and
appropriate. The control field shaii be used
b) Restore the immediately following octet by
a) to convey a command to the addressed data station(s)
complementing its 6th bit.
to perform a particular operation, or
b) to convey a response to such a command from the
NOTE - other octet values may optionaiiy be included in the
addressed data station.
transparency procedure by the transmitter. Such inclusion shall
be subject to prior system/application agreement.
4.4 Information field e
4.6 Frame checking sequencing (FCS) fiekl
Information may be any sequence of bits. In most cases it
will be Wed to a convenient character structure, for example
4.6.1 General
octets, but, if required, it may be an unspecified number of
Two frame checking sequences are specified, a 16-bit frame
bits and unrelated to a character structure.
checking sequence and a 32-bit frame checking sequence.
For start/stop transmission there shall be eight (8) information
The 16-bit frame checking sequence is normally used. The

bits between the start element and the stop element. If the 32-bit frame checking sequence is for use by prior agreement

information field is other than a multiple of 8 bits, the final in those cases that need a higher degree of protection than can

remainder less than an octet will require pad bits to complete
be provided by the 16-bit frame checking sequence.
the octet. The method of providing and unambiguously
NOTES
identifying the pad bits is not a subject of this International
Standard.
1. If future applications show that other degrees of protection
are needed, different numbers of bits in the FCS will be
specified. but they wiii be an integral number of octets.
4.5 Transparency
45.1 Synchronous transmission
2. Explanatory notes on the implementation of the frame
checking sequence are given in Annex A.
The transmitter shall examine the frame content between the
two flag sequences including the address. control and FCS
4.6.2 16-bit frame checking sequence
fields and shall insert a "O" bit after all sequences of 5
contiguous "1" bits (including the last 5 bits of the FCS) to
The 16-bit FCS shaii be the ones complement of the sum
ensure that a flag sequence is not simulated. The receiver
(modulo 2) of
shall examine the frame content and shall discard any "O" bit
a) the remainder of
which directly follows 5 contiguous "1" bits.
Xt(X15 +XI4 +XI3 +XI2 +XI1 +XI0 +x9 +
4.53 Stadstop transmission
x* +x7 +x6 +x5 +x4 +x3 +x2 +x + 1)
The control escape octet is a transparency identifier that
divided (modulo 2) by the generator polynomial
identifies an octet occurring within a frame to which the
following transparency procedure is applied. The encoding
XI6 +XI2 +xJ + 1,
of the control escap octet is:
where k is the number of bits in the frame existing
between, but not including, the 6nai bit of the
1 2 3 4 5 6 7 8 Bitpositioninoctet
opening flag and the first bit of the FCS, excluding
10111110
start and stop elements (start/stop transmission), and
bits (synchronous transmission) and octets (stari/stop
t ri^^ bit
transmission) inserted for transparency and
b) the remainder of the division (modulo 2) by the
The transmitter shall examine the frame content between the
generator polynomial
opening and closing flag sequences including the address,
control, and FCS fields and, following completion of the FCS
---------------------- Page: 6 ----------------------
ISO/IEC 3309 : 1991 (E)
x16 +XI2 +x5 + 1 existing between, but not including. the final bit of
the opening flag and the first bit of the FCS,
of the product of x16 by the content of the frame
excluding start and stop elements (start/stop
existing between, but not including, the final bit of
transmission), and bits (synchronous transmission)
the opening flag and the first bit of the FCS,
and octets (start/stop transmission) inserteù for
excluding start and stop elements (starthtop
transparency.
transmission), and bits (synchronous transmission)
As a typical implementation, at the transmitter, the initial
and octets (start/stop transmission) inserted for
content of the register of the device computing the remainder
transparency.
of the division is preset to aii ones and is then modified by
As a typical implementation, at the transmitter, the initial
division by the generator polynomial (as described above) of
content of the register of the device computing the remainder
the address. control and information fields, the ones
of the division is preset to all ones and is then modified by
complement of the resulting remainder is transmitted as the
division by the generator polynomial (as described above) of
32-bit FCS.
the address, control and information fields; the ones
At the receiver. the initial content of the register of the device
complement of the resulting remainder is transmitted as the
computing the remahder is preset to all ones. The final
16-bit FCS.
remainder after multiplication by x3' and then division
As the receiver, the initial content of the register of the device
(modulo 2) by the generator polynomial
computing the remainder is preset to all ones. The final
io x32 +xx +xm +x= +XI6 +XI2 +XI1 +XI0 +
remainder after multiplication by x16 and then division
(modulo 2) by the generator polynomial
x8 +x7 +x5 +x4 +x2 +x + 1
XI6 +XI2 +x5 + 1
of the serial incoming protected bits and the FCS will be
of the serial incoming protected bits and the FCS will be
1100 O111 m 0100 1101 1101 O111 1011
O001 1101 oo00 11 11 (x15 through x', respectively)
(x31 through xo, respectively)
in the absence of transmission errors.
...

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