ISO/IEC 14776-115:2004
(Main)Information technology - Small Computer System Interface (SCSI) - Part 115: Parallel Interface-5 (SPI-5)
Information technology - Small Computer System Interface (SCSI) - Part 115: Parallel Interface-5 (SPI-5)
The SCSI parallel interface (SPI) is designed to provide an efficient peer-to-peer I/O bus with the maximum number of hosts and peripherals determined by the bus width (i.e., 8 or 16). Data may be transferred asynchronously or synchronously at rates that depend on implementation. The objectives of the SCSI parallel interface are: a) To provide host computers with device independence within a class of devices. Thus, different disk drives, tape drives, printers, optical media drives, and other SCSI devices may be added to the host computers without requiring modifications to generic system hardware. b) To provide compatibility such that conforming SPI-2, SPI-3 devices may interoperate with SPI-5 devices given that the systems engineering is correctly done. The interface protocol includes provision for the connection of multiple SCSI initiator ports (i.e., SCSI devices capable of initiating an I/O process) and multiple SCSI target ports (i.e., SCSI devices capable of responding to a request to perform an I/O process). This international standard defines mechanical, electrical, timing requirements, command, and the task management delivery protocol requirements to transfer commands and data between SCSI devices attached to an SCSI parallel interface, i.e. to allow conforming SCSI devices to interoperate. It is intended to be used in conjunction with the SCSI command sets. The resulting interface facilitates the interconnection of computers and intelligent peripherals and thus provides a common interface standard for both system integrators and suppliers of intelligent peripherals. This standard is a functional description. Conforming implementations may employ any design technique that does not violate interoperability. This standard has made obsolete single-ended and multimode signalling alternatives. Implementations that use single-ended or multimode signalling alternatives should reference the SCSI Parallel Interface-2 standard (ISO/IEC 14776-112).
Technologies de l'information — Interface de petit système d'ordinateur (SCSI) — Partie 115: Interface parallèle 5 (SPI-5)
General Information
- Status
- Published
- Publication Date
- 28-Nov-2004
- Technical Committee
- ISO/IEC JTC 1/SC 25 - Interconnection of information technology equipment
- Current Stage
- 9093 - International Standard confirmed
- Start Date
- 13-Jul-2018
- Completion Date
- 30-Oct-2025
Relations
- Consolidated By
ISO 4210-8:2014 - Cycles - Safety requirements for bicycles - Part 8: Pedal and drive system test methods - Effective Date
- 06-Jun-2022
Overview
ISO/IEC 14776-115:2004 - Information technology - Small Computer System Interface (SCSI) - Part 115: Parallel Interface-5 (SPI-5) - defines the functional, mechanical and electrical specifications for the SCSI parallel interface (SPI-5). The standard describes how SCSI initiator and target ports exchange commands and data over an LVD-based parallel bus, specifies connector and cable requirements, and provides timing, negotiation and protocol rules to ensure interoperability among conforming devices. SPI-5 is intended to be used with SCSI command sets and supersedes single-ended/multimode signalling options (those remain in SPI-2).
Keywords: ISO/IEC 14776-115:2004, SCSI, SPI-5, Parallel Interface-5, LVD, SCSI initiator, SCSI target
Key topics and technical requirements
The standard covers these principal areas and requirements:
- Scope and model: SCSI parallel interface architecture, device roles (initiator/target), bus topology and addressing.
- Mechanical & connector specs: approved connector types (shielded/non‑shielded alternatives), contact assignments and cable interconnect guidelines.
- Electrical characteristics: Low Voltage Differential (LVD) driver/receiver behavior, termination and TERMPWR handling, decoupling and capacitive load limits.
- Signalling and transmission: LVD signal states, OR‑tied signals, SE/HVD detection (backward compatibility considerations).
- Timing & protocol: Detailed bus timing values, arbitration, bus set/clear/settle delays, flow control and skew limits.
- Data transfer modes: Asynchronous, synchronous and paced transfers; ST/DT DATA phases and information unit transfers.
- Negotiation and message sequences: SDTR/WDTR/PPR negotiation algorithms, negotiable fields (transfer period, REQ/ACK offset, width exponent, protocol options).
- Command & task management delivery: Requirements for transferring SCSI commands, status and task management across the parallel interface.
- Interoperability focus: Functional descriptions allowing varied implementations provided they do not break interoperability.
Applications and who uses it
ISO/IEC 14776-115:2004 is relevant to:
- Storage device manufacturers designing SCSI disk drives, tape drives and optical devices compliant with SPI-5.
- Host adapter and controller vendors implementing SCSI initiator ports and bus interconnect hardware.
- System integrators and OEMs integrating multiple SCSI peripherals into servers, SAN gateways, and embedded systems.
- Firmware and driver developers implementing negotiation, timing and task management across a parallel SCSI bus.
- Cable and connector suppliers producing compliant LVD cables and terminated assemblies.
Related standards
- ISO/IEC 14776-112 (SCSI Parallel Interface‑2) - references single‑ended and multimode signalling alternatives.
- SCSI command set standards - to be used in conjunction with SPI‑5 for command semantics and task management.
This standard is a functional interoperability reference for professionals implementing or integrating parallel SCSI (SPI‑5) interfaces in storage and peripheral systems.
Frequently Asked Questions
ISO/IEC 14776-115:2004 is a standard published by the International Organization for Standardization (ISO). Its full title is "Information technology - Small Computer System Interface (SCSI) - Part 115: Parallel Interface-5 (SPI-5)". This standard covers: The SCSI parallel interface (SPI) is designed to provide an efficient peer-to-peer I/O bus with the maximum number of hosts and peripherals determined by the bus width (i.e., 8 or 16). Data may be transferred asynchronously or synchronously at rates that depend on implementation. The objectives of the SCSI parallel interface are: a) To provide host computers with device independence within a class of devices. Thus, different disk drives, tape drives, printers, optical media drives, and other SCSI devices may be added to the host computers without requiring modifications to generic system hardware. b) To provide compatibility such that conforming SPI-2, SPI-3 devices may interoperate with SPI-5 devices given that the systems engineering is correctly done. The interface protocol includes provision for the connection of multiple SCSI initiator ports (i.e., SCSI devices capable of initiating an I/O process) and multiple SCSI target ports (i.e., SCSI devices capable of responding to a request to perform an I/O process). This international standard defines mechanical, electrical, timing requirements, command, and the task management delivery protocol requirements to transfer commands and data between SCSI devices attached to an SCSI parallel interface, i.e. to allow conforming SCSI devices to interoperate. It is intended to be used in conjunction with the SCSI command sets. The resulting interface facilitates the interconnection of computers and intelligent peripherals and thus provides a common interface standard for both system integrators and suppliers of intelligent peripherals. This standard is a functional description. Conforming implementations may employ any design technique that does not violate interoperability. This standard has made obsolete single-ended and multimode signalling alternatives. Implementations that use single-ended or multimode signalling alternatives should reference the SCSI Parallel Interface-2 standard (ISO/IEC 14776-112).
The SCSI parallel interface (SPI) is designed to provide an efficient peer-to-peer I/O bus with the maximum number of hosts and peripherals determined by the bus width (i.e., 8 or 16). Data may be transferred asynchronously or synchronously at rates that depend on implementation. The objectives of the SCSI parallel interface are: a) To provide host computers with device independence within a class of devices. Thus, different disk drives, tape drives, printers, optical media drives, and other SCSI devices may be added to the host computers without requiring modifications to generic system hardware. b) To provide compatibility such that conforming SPI-2, SPI-3 devices may interoperate with SPI-5 devices given that the systems engineering is correctly done. The interface protocol includes provision for the connection of multiple SCSI initiator ports (i.e., SCSI devices capable of initiating an I/O process) and multiple SCSI target ports (i.e., SCSI devices capable of responding to a request to perform an I/O process). This international standard defines mechanical, electrical, timing requirements, command, and the task management delivery protocol requirements to transfer commands and data between SCSI devices attached to an SCSI parallel interface, i.e. to allow conforming SCSI devices to interoperate. It is intended to be used in conjunction with the SCSI command sets. The resulting interface facilitates the interconnection of computers and intelligent peripherals and thus provides a common interface standard for both system integrators and suppliers of intelligent peripherals. This standard is a functional description. Conforming implementations may employ any design technique that does not violate interoperability. This standard has made obsolete single-ended and multimode signalling alternatives. Implementations that use single-ended or multimode signalling alternatives should reference the SCSI Parallel Interface-2 standard (ISO/IEC 14776-112).
ISO/IEC 14776-115:2004 is classified under the following ICS (International Classification for Standards) categories: 35.200 - Interface and interconnection equipment. The ICS classification helps identify the subject area and facilitates finding related standards.
ISO/IEC 14776-115:2004 has the following relationships with other standards: It is inter standard links to ISO 4210-8:2014. Understanding these relationships helps ensure you are using the most current and applicable version of the standard.
You can purchase ISO/IEC 14776-115:2004 directly from iTeh Standards. The document is available in PDF format and is delivered instantly after payment. Add the standard to your cart and complete the secure checkout process. iTeh Standards is an authorized distributor of ISO standards.
Standards Content (Sample)
INTERNATIONAL ISO/IEC
STANDARD 14776-115
First edition
2004-11
Information technology –
Small computer system interface (SCSI) –
Part 115:
Parallel Interface-5 (SPI-5)
Reference number
INTERNATIONAL ISO/IEC
STANDARD 14776-115
First edition
2004-11
Information technology –
Small computer system interface (SCSI) –
Part 115:
Parallel Interface-5 (SPI-5)
© ISO/IEC 2004
All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form or by any
means, electronic or mechanical, including photocopying and microfilm, without permission in writing from the publisher.
ISO/IEC Copyright Office Case postale 56 CH-1211 Genève 20 Switzerland
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PRICE CODE
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Contents
Page
Foreword .19
Introduction.20
1 Scope .21
2 Normative references .22
2.1 Normative references .22
2.2 Approved references .22
2.3 References under development .23
2.4 Other references .23
3 Definitions, symbols, abbreviations, and conventions .23
3.1 Definitions .23
3.2 Symbols and abbreviations .32
3.3 Keywords .33
3.4 Conventions .34
3.5 Notation for Procedures and Functions .35
4 SCSI parallel interface model .36
4.1 SCSI parallel interface model overview .36
4.2 Cables, connectors, signals, transceivers .36
4.3 Physical architecture of bus segment .36
4.4 Driver-receiver connections .37
4.5 Physical topology details and definitions .37
4.6 Bus segment loading .39
4.7 Termination requirements .39
4.8 SCSI device Addressing .39
4.9 Clocking methods for data transfers .40
4.10 Paced transfer on a SCSI bus .42
4.11 Data transfers .44
4.11.1 Data transfer modes .44
4.11.1.1 Asynchronous transfers .44
4.11.1.2 Synchronous transfers .44
4.11.1.3 Paced transfers .44
4.11.2 ST DATA phase parallel transfers .44
4.11.3 DT DATA phase parallel transfers .45
4.11.3.1 DT DATA phase parallel transfers format .45
4.11.3.2 Data group transfers .45
4.11.3.3 Information unit transfers .45
4.12 Negotiation .46
4.12.1 Negotiation introduction .46
4.12.2 Negotiation algorithm .46
4.12.3 When to negotiate .47
4.12.4 Negotiable fields .48
4.12.4.1 Negotiable fields introduction .48
4.12.4.2 Transfer agreements .49
4.12.4.3 Transfer period factor .49
4.12.4.4 REQ/ACK offset .51
4.12.4.5 Transfer width exponent .52
4.12.4.6 Protocol options .52
4.12.4.6.1 Protocol options introduction .52
4.12.4.6.2 IU_REQ .53
4.12.4.6.3 DT_REQ .54
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4.12.4.6.4 QAS_REQ .54
4.12.4.6.5 HOLD_MCS .54
4.12.4.6.6 WR_FLOW .55
4.12.4.6.7 RD_STRM .55
4.12.4.6.8 RTI .55
4.12.4.6.9 PCOMP_EN .55
4.12.5 Negotiable field combinations .56
4.12.6 Message restrictions .57
4.12.7 Negotiation message sequences .58
4.12.7.1 Negotiation message sequences overview .58
4.12.7.2 SCSI initiator port originated PPR negotiation .59
4.12.7.3 SCSI initiator port originated WDTR negotiation .60
4.12.7.4 SCSI initiator port originated SDTR negotiation .62
4.12.7.5 SCSI target port originated WDTR negotiation .64
4.12.7.6 SCSI target port originated SDTR negotiation .67
4.13 Protocol .68
5 SCSI parallel interface connectors .71
5.1 SCSI parallel interface connectors overview .71
5.2 Non-shielded connector .71
5.2.1 Non-shielded connector alternative 1 - A cable .71
5.2.2 Non-shielded connector alternative 2 - A cable .71
5.2.3 Non-shielded connector alternative 3 - P cable .72
5.2.4 Non-shielded connector alternative 4 .72
5.3 Shielded connector .78
5.3.1 Shielded connector overview .78
5.3.2 Shielded connector alternative 1 - A cable .78
5.3.3 Shielded connector alternative 2 - A cable .78
5.3.4 Shielded connector alternative 3 - P cable .78
5.3.5 Shielded connector alternative 4 - P cable .78
5.4 Connector contact assignments .86
5.4.1 Connector contact assignments overview .86
5.4.2 Differential connector contact assignments .87
6 SCSI bus segment interconnect .90
6.1 SCSI bus segment interconnect overview .90
6.2 SCSI bus segment cables .90
6.3 Interconnect characteristics for signals .91
6.3.1 SCSI bulk cable .91
6.3.2 Minimum conductor size for signals .92
6.3.3 Local transmission line impedance .92
6.3.4 Extended distance transmission line impedance .92
6.3.5 Capacitance .92
6.3.6 Differential propagation time and propagation time skew .92
6.3.7 Differential attenuation .92
6.3.8 Crosstalk .93
6.4 Decoupling characteristics for TERMPWR lines .93
6.5 Connection requirements for RESERVED lines .94
6.6 Cables used with LVD transceivers .94
6.7 LVD stub length and spacing .95
7 SCSI parallel interface electrical characteristics .96
7.1 SCSI parallel interface electrical characteristics overview .96
7.2 LVD termination .96
7.2.1 LVD termination overview .96
7.2.2 LVD driver characteristics .101
7.2.3 LVD receiver characteristics .104
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7.2.4 LVD capacitive loads .105
7.2.4.1 Management of LVD release glitches .107
7.2.5 SE/HVD transmission mode detection .109
7.2.5.1 SE/HVD transmission mode detection overview .109
7.2.5.2 LVD DIFFSENS driver .109
7.2.5.3 LVD DIFFSENS receiver .110
7.3 Terminator power .112
8 SCSI bus signals .114
8.1 SCSI bus signals overview .114
8.2 Signal descriptions .114
8.3 LVD Signal states .117
8.4 OR-tied signals .118
8.5 Signal sources .118
9 SCSI parallel bus timing .120
9.1 SCSI parallel bus timing values .120
9.2 Timing description .126
9.2.1 Arbitration delay .126
9.2.2 ATN transmit setup time .127
9.2.3 ATN receive setup time .127
9.2.4 Bus clear delay .127
9.2.5 Bus free delay .127
9.2.6 Bus set delay .127
9.2.7 Bus settle delay .128
9.2.8 Cable skew .128
9.2.9 Chip noise in receiver .128
9.2.10 Clock jitter .128
9.2.11 Crosstalk time shift .128
9.2.12 Flow control receive hold time .128
9.2.13 Flow control receive setup time .128
9.2.14 Flow control transmit hold time .128
9.2.15 Flow control transmit setup time .128
9.2.16 Offset induced time asymmetry .129
9.2.17 pCRC receive hold time .129
9.2.18 pCRC receive setup time .129
9.2.19 pCRC transmit hold time .129
9.2.20 pCRC transmit setup time .129
9.2.21 Data release delay .129
9.2.22 DIFFSENS voltage filter time .129
9.2.23 Physical disconnection delay .129
9.2.24 Power on to selection .129
9.2.25 QAS arbitration delay .130
9.2.26 QAS assertion delay .130
9.2.27 QAS release delay .130
9.2.28 QAS non-DATA phase REQ(ACK) period .130
9.2.29 Receive assertion period .130
9.2.30 Receive hold time .130
9.2.31 Receive internal hold time .130
9.2.32 Receive internal setup time .130
9.2.33 Receive negation period .131
9.2.34 Receive setup time .131
9.2.35 Receive REQ(ACK) period tolerance .131
9.2.36 Receive REQ assertion period with P_CRCA transitioning .131
9.2.37 Receive REQ negation period with P_CRCA transitioning .131
9.2.38 Receive Skew Compensation .131
9.2.39 Receiver amplitude time skew .131
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9.2.40 Receiver de-skewed data valid window .131
9.2.41 REQ(ACK) period .132
9.2.42 Reset delay .132
9.2.43 Reset hold time .132
9.2.44 Reset to selection .132
9.2.45 Residual skew error .133
9.2.46 Selection abort time .133
9.2.47 Selection time-out delay .133
9.2.48 Signal timing skew .133
9.2.49 Skew correction range .133
9.2.50 Strobe offset tolerance .134
9.2.51 System deskew delay .134
9.2.52 System noise at launch .134
9.2.53 System noise at receiver .134
9.2.54 Time asymmetry .134
9.2.55 Transmit assertion period .134
9.2.56 Transmit hold time .135
9.2.57 Transmit ISI Compensation .135
9.2.58 Transmit negation period .135
9.2.59 Transmit setup time .135
9.2.60 Transmit REQ(ACK) period tolerance .135
9.2.61 Transmit REQ assertion period with P_CRCA transitioning .135
9.2.62 Transmit REQ negation period with P_CRCA transitioning .135
9.2.63 Transmitter skew .135
9.2.64 Transmitter time asymmetry .136
9.3 Measurement points .136
9.3.1 Measurement points overview .136
9.3.2 LVD measurement points .137
9.4 Receiver Masks .139
9.4.1 Synchronous transfers and for fast-160 paced transfer clocking signals .139
9.4.2 Paced transfers with precompensation enabled on fast-160 .140
9.4.3 Paced transfers with precompensation disabled on fast-160 and fast-320 .142
9.5 Timing parameters .148
9.6 Setup and hold timings .148
9.6.1 ST data transfer calculations .148
9.6.2 DT data transfer calculations .149
10 SCSI bus phases .151
10.1 SCSI bus phases overview .151
10.2 BUS FREE phase .151
10.3 Expected and unexpected bus free phases .151
10.4 Arbitration .152
10.4.1 Arbitration and QAS overview .152
10.4.2 NORMAL ARBITRATION phase .152
10.4.3 QAS protocol .153
10.4.4 QAS phase .154
10.5 SELECTION phase .155
10.5.1 Selection Overview .155
10.5.2 Selection using attention condition .156
10.5.2.1 Starting the SELECTION phase when using attention condition .156
10.5.2.2 Information unit transfers disabled .156
10.5.2.3 Information unit transfers enabled .156
10.5.2.4 Selection using attention condition time-out procedure .156
10.5.3 Selection without using attention condition .157
10.5.3.1 Information unit transfers disabled or enabled .157
10.5.3.2 Selection without using attention condition time-out procedure .157
10.6 RESELECTION phase .158
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10.6.1 RESELECTION phase overview .158
10.6.2 Physical reconnection .158
10.6.3 Physical reconnection time-out procedure .159
10.7 Information transfer phases .159
10.7.1 Information transfer phases overview .159
10.7.2 Asynchronous transfer .160
10.7.3 Synchronous transfer .161
10.7.3.1 Synchronous transfer overview .161
10.7.3.2 ST synchronous transfer .161
10.7.3.3 DT synchronous transfer .162
10.7.3.3.1 DT synchronous transfer overview .162
10.7.3.3.2 Information unit transfer .162
10.7.3.3.3 DT DATA IN phase information unit transfer exception condition handling .163
10.7.3.3.4 DT DATA OUT phase information unit transfer exception condition handling .164
10.7.3.3.5 Data group data field transfer .165
10.7.3.3.6 Data Group Pad field and pCRC field transfer to SCSI initiator port .165
10.7.3.3.7 Data Group Pad field and pCRC field transfer to SCSI target port .167
10.7.4 Paced transfer .168
10.7.4.1 Paced transfer overview .168
10.7.4.2 Paced transfer training pattern .169
10.7.4.2.1 Training pattern overview .169
10.7.4.2.2 DT DATA IN phase training pattern .170
10.7.4.2.3 DT DATA OUT phase training pattern .171
10.7.4.3 P1 data valid/invalid state transitions .172
10.7.4.3.1 P1 data valid/invalid state transitions overview .172
10.7.4.3.2 Starting pacing transfers at end of training pattern .173
10.7.4.3.3 Starting pacing transfers with no training pattern .173
10.7.4.3.4 Ending pacing transfers .174
10.7.4.4 Paced information unit transfer .174
10.7.4.5 Deskewing .175
10.7.5 Wide transfer .175
10.8 COMMAND phase .176
10.8.1 COMMAND phase description .176
10.8.2 COMMAND phase exception condition handling .176
10.9 DATA phase .177
10.9.1 DATA phase overview .177
10.9.2 DT DATA IN phase .177
10.9.3 DT DATA OUT phase .177
10.9.4 ST DATA IN phase .177
10.9.5 ST DATA OUT phase .177
10.10 STATUS phase .177
10.10.1 STATUS phase description .177
10.10.2 STATUS phase exception condition handling .178
10.11 MESSAGE phase .178
10.11.1 MESSAGE phase overview .178
10.11.2 MESSAGE IN phase .178
10.11.3 MESSAGE IN phase exception condition handling .178
10.11.4 MESSAGE OUT phase .178
10.11.5 MESSAGE OUT phase exception condition handling .179
10.12 Signal restrictions between phases .179
11 DATA BUS protection .181
11.1 DATA BUS protection overview .181
11.2 ST DATA BUS protection using parity .181
11.3 DT DATA BUS protection using CRC .181
11.3.1 DT DATA BUS protection using CRC overview .181
11.3.2 Error detection capabilities .181
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11.3.3 Order of bytes in the CRC field .182
11.3.4 CRC generation and checking .184
11.3.5 Test cases .184
12 SCSI bus conditions .185
12.1 SCSI bus conditions overview .185
12.2 Attention condition .185
12.3 Bus reset condition .186
12.4 Hard reset .186
12.5 Reset events .187
12.5.1 Reset events overview .187
12.5.2 Bus reset event .187
12.5.3 Power on reset event .187
12.5.4 Target reset event .187
13 SCSI bus phase sequences .188
13.1 SCSI bus phase sequences overview .188
13.2 Phase sequences with information units disabled .189
13.2.1 Phase sequences for physical reconnection or selection using attention condition .189
13.2.2 Phase sequences for selection without using attention condition .190
13.3 Phase sequences with information unit enabled .191
13.3.1 Phase sequences for physical reconnection or selection without using attention condition .191
13.3.2 Phase sequences for selection using attention condition .192
14 SPI information units .193
14.1 SPI information unit overview .193
14.2 Information unit transfer logical operations .193
14.3 SPI information units .199
14.3.1 SPI command information unit .199
14.3.2 SPI L_Q information unit .203
14.3.3 SPI data information unit .206
14.3.4 SPI data stream information unit .207
14.3.5 SPI status information unit .208
15 SCSI pointers .212
16 SCSI messages .213
16.1 SCSI messages overview .213
16.2 Message protocols and formats .213
16.2.1 Message protocol rules .213
16.2.2 Message formats .213
16.2.3 One-byte messages .214
16.2.4 Two-byte messages .214
16.2.5 Extended messages .214
16.3 Link control messages .216
16.3.1 Link control message codes .216
16.3.2 DISCONNECT .217
16.3.3 IDENTIFY .217
16.3.4 IGNORE WIDE RESIDUE .218
16.3.5 INITIATOR DETECTED ERROR .219
16.3.6 LINKED COMMAND COMPLETE .
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