Semiconductor devices - Hot carrier test on MOS transistors

IEC 62416:2010 describes the wafer level hot carrier test on NMOS and PMOS transistors. The test is intended to determine whether the single transistors in a certain (C)MOS process meet the required hot carrier lifetime.

Dispositifs à semiconducteurs - Essai de porteur chaud sur les transistors MOS

La CEI 62416:2010 décrit l'essai de porteur chaud au niveau de la plaquette sur les transistors NMOS et PMOS. Cet essai est destiné à déterminer si les transistors individuels sont conformes à la durée de vie exigée du porteur chaud dans un processus (C)MOS donné.

General Information

Status
Published
Publication Date
25-Apr-2010
Technical Committee
Current Stage
PPUB - Publication issued
Start Date
26-Apr-2010
Completion Date
26-Apr-2010
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IEC 62416
Edition 1.0 2010-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor devices – Hot carrier test on MOS transistors
Dispositifs à semiconducteurs – Essai de porteur chaud sur les transistors MOS
IEC 62416:2010
---------------------- Page: 1 ----------------------
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---------------------- Page: 2 ----------------------
IEC 62416
Edition 1.0 2010-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor devices – Hot carrier test on MOS transistors
Dispositifs à semiconducteurs – Essai de porteur chaud sur les transistors MOS
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
CODE PRIX
ICS 31.080 ISBN 978-2-88910-695-0
® Registered trademark of the International Electrotechnical Commission
Marque déposée de la Commission Electrotechnique Internationale
---------------------- Page: 3 ----------------------
– 2 – 62416 © IEC:2010
CONTENTS

FOREWORD...........................................................................................................................3

1 Scope...............................................................................................................................5

2 Abbreviations and letter symbols ......................................................................................5

3 Test structures .................................................................................................................6

4 Stress time .......................................................................................................................6

5 Stress conditions ..............................................................................................................6

6 Sample size......................................................................................................................7

7 Temperature.....................................................................................................................7

8 Failure criteria ..................................................................................................................7

9 Lifetime estimation method...............................................................................................7

9.1 DC acceleration models ..........................................................................................7

9.1.1 General .......................................................................................................7

9.1.2 Method 1: extrapolation vs. drain currrent....................................................8

9.1.3 Method 2: extrapolation vs. drain bias and channel length ...........................8

9.2 AC estimation model ...............................................................................................9

10 Lifetime requirements .......................................................................................................9

11 Reporting .........................................................................................................................9

Bibliography..........................................................................................................................10

---------------------- Page: 4 ----------------------
62416 © IEC:2010 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES –
HOT CARRIER TEST ON MOS TRANSISTORS
FOREWORD

1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising

all national electrotechnical committees (IEC National Committees). The object of IEC is to promote

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patent rights. IEC shall not be held responsible for identifying any or all such patent rights.

International Standard IEC 62416 has been prepared by IEC technical committee 47:

Semiconductor devices.
The text of this standard is based on the following documents:
FDIS Report on voting
47/2041/FDIS 47/2048/RVD

Full information on the voting for the approval of this standard can be found in the report on

voting indicated in the above table.

This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.

---------------------- Page: 5 ----------------------
– 4 – 62416 © IEC:2010

The committee has decided that the contents of this publication will remain unchanged until

the stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data

related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
---------------------- Page: 6 ----------------------
62416 © IEC:2010 – 5 –
SEMICONDUCTOR DEVICES –
HOT CARRIER TEST ON MOS TRANSISTORS
1 Scope

This standard describes the wafer level hot carrier test on NMOS and PMOS transistors. The

test is intended to determine whether the single transistors in a certain (C)MOS process meet

the required hot carrier lifetime.
2 Abbreviations and letter symbols
In this document the following abbreviations and letter symbols apply:
MOS Metal Oxide Semiconductor
NMOS n-channel MOS transistor
PMOS p-channel MOS transistor
(C)MOS Complementary MOS
L [μm] length of polysilicon gate of MOS transistor
W [μm] width of polysilicon gate of MOS transistor
L [μm] minimum L allowed by the design rules of the process
nominal
W [μm] minimum W allowed by the design rules of the process
nominal
V [V] gate-source voltage of MOS transistor
V [V] drain-source voltage of MOS transistor
V [V] backgate-source voltage of MOS transistor
I [μA]: drain-source current of MOS transistor
I [μA] substrate current of MOS transistor
I [nA] gate current of MOS transistor
V [V] V biasing condition during hot carrier stress
gs,stress gs
V [V] V biasing condition during hot carrier stress
ds,stress ds
V [V] maximum V allowed by the design rules of the process as stated in the
ds,use_max ds
design manual
V [V] V at which avalanche or punch-through currents become dominant;
ds,breakdown ds
defined as V at which I = 1,5 × (I at V ) while V = V
ds ds ds ds,use_max gs ds,use_max
V [V] threshold voltage of MOS transistor defined as V voltage at which I =
t gs ds
0,01 × W / L [μA]. Other (commonly agreed) definitions of V are also
allowed as long as this is clearly reported.
g [μA/V] transconductance of MOS transistor
g [μA/V] maximum transconductance of MOS transistor
m,max
I [μA] saturated drain-source current at V = V = V ; I
ds,sat gs ds ds,use_,max ds,sat_forward
measured with source and drain having same polarity as during stress,
I measured with source and drain polarity interchanged with
ds,sat_reverse
respect to stress.
L( MOST) length of the square MOS transistor (L = W)
g ( MOST) g of the square MOS transistor (L = W)
m,max m,max
---------------------- Page: 7 ----------------------
– 6 – 62416 © IEC:2010
τ[s] lifetime of the MOS transistor

L [μm] effective electrical channel length of MOS transistor; the L for a given L is

eff eff
determined using the g of a large ‘square ( )‘ MOS transistor with W =
m,max
L >> L .
nominal
3 Test structures

For the evaluation of the hot carrier degradation vulnerability of a technology, nominal

transistors (L = L ) are recommended. The following gate lengths are recommended
nominal

when lifetime extrapolation versus L is needed (see 9.1): L = 1,0 × L , L = 1,5 × L ,

nominal nominal
L = 2,0 × L , L = 5,0 × L , L = W.
nominal nominal

Gates and sources of the transistors may be combined to reduce the number of bond pads

required for these test structures.
Typical values for W are 10 μm for L < 1 μm, and 20 μm for L 1μm. A
nominal nominal

transistor with small W (e.g. W = L ) can be used to evaluate the occurrence of potential

nominal
‘narrow width’ effects.

The nominal transistor shall be placed with various orientations on the wafer (e.g. one with

the orientation of its gate parallel to the flat of the wafer and one with its gate orientation

perpendicular to the flat) whenever asymmetry effects due to ion implantation are expected.

4 Stress time

Typically 40 000 s (one night), in some ‘low voltage’ cases 200 000 s (1 weekend); readpoints

logarithmically spaced (at least 3 per decade). Stress times shall be chosen such that the

degradation exceeds at least 20 % of the maximum value for the selected failure criterion (see

Clause 8).
5 Stress conditions
At least 3 different V conditions where V < V , V = 0 V.
ds,stress ds,stress_max ds,breakdown bs

NMOS transistors are stressed at maximum substrate current conditions. Usually, the

maximum substrate current occurs at approximately
V = V / 2 V – 0,5 V (1)
gs,stress ds,stress

If this is not the case for a certain technology, one shall determine the appropriate V

gs,stress
by substrate current measurements.

For deep-submicron transistors worst-case degradation may not occur at maximum substrate

current, and it is therefore recommended that the worst-case stress conditions are checked.

PMOS transistors are stressed at maximum gate current conditions. Usually, maximum gate

current occurs at approximately
V = V – 1,0 V (2)
gs,stress t
(e.g. V = –0,8 V then V = –1,8 V)
t gs

If this is not the case for a certain technology, one shall determine the appropriate V

gs,stress
by gate current measurements.
---------------------- Page: 8 ----------------------
62416 © IEC:2010 – 7 –

For accurate determination of the life time it is recommended to reach the failure criterion

during the stress. This can be achieved by choosing a high V value. A reasonable starting

value is V = 0,9 × V . If this is not feasible it is recommended to take at least two

ds ds,breakdown
time decades of valid data and extrapolate to the failure criterion.
6 Sample size

The sample size is not prescribed. Too low sample sizes will result in short life times due to

the 60 % confidence requirement for extrapolation.

It is recommended to use at least 3 V bias conditions and 4 different W/L ratios.

The resulting number of datapoints is for example 3 (V ) × 4 (transistors) × 2 batches = 24

datapoints.
7 Temperature
Room temperature, kept constant within ±3 °C.
8 Failure criteria

Failure criteria have to be selected for one or more of the following parameters:

Δg , ΔV , ΔI , ΔI , ΔI . Recommended criteria are given below:
m,max t ds,sat_ forward ds,sat_reverse ds,lin
|Δg /g | = 10% at V = 0,1 V or
m,max m,max ds
|ΔV | = 0,02xV with a minimum value of 100 mV at V = 0,1 V or
t dd,max ds
|ΔI /I |forward = 10 % or
ds,sat ds,sat
|ΔI /I |reverse = 10 % or
ds,sat ds,sat
|ΔI /I |forward = 10 %
ds,lin ds,lin
NMOS transistors typically show a decrease in g and I and an increase in |V |.
m ds,sat t
PMOS transistors typically show an increase in g and I and a decrease in |V |.
m ds,sat t

Lifetimes can be determined by interpolation and extrapolation of data. However it is

recommended to disregard data where the shift in g , I or V did not exceed 20 % of the

m ds,sat t

failure criteria or when the data must be extrapolated by more than one decade in time in

order to reach the failure criteria.
9 Lifetime estimation method
9.1 DC acceleration models
9.1.1 General

Two different methods for lifetime estimation are given. Method 1 uses the dependence of

lifetime on the drain current, and requires only the nominal transistor. Method 2 uses the

dependency of lifetime on gate length, and requires test structures with different L. Method 2

is used when the dependency of lifetime on channel length is needed.
---------------------- Page: 9 ----------------------
– 8 – 62416 © IEC:2010
9.1.2 Method 1: extrapolation vs. drain current
For NMOS transistors, extrapolation is done according to
τ = A × (I ) (3)
where
A is a process-dependent constant, and
m is the substrate current acceleration exponent.
For L < 0,5 μm, a better fit may be obtained with [1] :
τ*I = A × (I /I ) (4)
ds b ds
For PMOS transistors, extrapolation is done according to [2]:
τ = A × (I ) (5)

The parameters A and m are found by plotting log(τ) versus log(I ) or log(I ) (see equation 4

b g

and equation 6 respectively), or by plotting log(τ*I ) versus log(I /I ) (see equation 5). A

d b d
straight line is found with slope m and intercept log(A).
9.1.3 Method 2: extrapolation versus drain bias and channel length

For NMOS transistors, the Takeda model [3] can be used for the channel length dependence.

τ = A × exp(B / V ) × (L ) (6)
ds,stress eff
where
A is a process-dependent constant;
B is the process-dependent voltage acceleration constant;
C is the process-dependent channel length acceleration constant.
L is given by
eff
L = L( MOST) × g ( MOST) / g (L) (7)
eff m,max m,max

For PMOS transistors, the Woltjer model [4] can be used for the channel length dependence.

τ = A × exp(B / V ) × exp(C × √(L)) (8)
ds,stress eff

The parameters A, B and C are found from a simultaneous fit of the lifetime τ as a function of

V and L .
ds,stress eff

For deep submicron CMOS technologies other extrapolation models are also used for the

channel length dependence of lifetime for both NMOS en PMOS transistors, e.g. τ = A ×

exp(CxL ) or τ = A × exp(C/L )
eff eff

NOTE In these models, only lifetime data based on one failure criterion should be used at a time.

___________
The figures in square brackets refer to the Bibliography.
---------------------- Page: 10 ----------------------
62416 © IEC:2010 – 9 –
9.2 AC estimation model
For AC applications, lifetime is calculated according to
τ = τ × t /(t +t ) (9)
AC DC cycle rise fall
where
τ is the lifetime of the AC bias condition,
τ the lifetime of the DC bias condition,
t is the cycle time of the AC stress,
cycle
t is the rise time of the AC stress, and
rise
t is the fall time of the AC stress.
fall
AC tests are recommended.
10 Lifetime requirements

In analog circuits, the required lifetime may be achieved by increasing the minimum L

eff
allowed in analog designs.

Hot carrier lifetime of digital circuitry exceeds the static transistor lifetime by far due to duty

cycle effects and limited sensitivity of digital circuitry to transistor degradation [5].

11 Reporting

The following items shall be reported as a minimum, when presenting hot carrier data:

– number of transistors used as well as their dimensions;
– stress voltages used;
– failu
...

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