IEC 62416:2010

Semiconductor devices - Hot carrier test on MOS transistors

IEC 62416:2010 describes the wafer level hot carrier test on NMOS and PMOS transistors. The test is intended to determine whether the single transistors in a certain (C)MOS process meet the required hot carrier lifetime.

Dispositifs à semiconducteurs - Essai de porteur chaud sur les transistors MOS

La CEI 62416:2010 décrit l'essai de porteur chaud au niveau de la plaquette sur les transistors NMOS et PMOS. Cet essai est destiné à déterminer si les transistors individuels sont conformes à la durée de vie exigée du porteur chaud dans un processus (C)MOS donné.

General Information

• Status: Published
• Publication Date: 25-Apr-2010
• ICS: 01 - GENERALITIES. TERMINOLOGY. STANDARDIZATION. DOCUMENTATION
• ICS: 31.080.30 - Transistors
• Technical Committee: TC 47 - Semiconductor devices
• Drafting Committee: WG 5 - TC 47/WG 5
• Current Stage: PPUB - Publication issued
• Start Date: 15-May-2010
• Completion Date: 26-Apr-2010

Standards Content (Sample)

IEC 62416 ®
Edition 1.0 2010-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor devices – Hot carrier test on MOS transistors

Dispositifs à semiconducteurs – Essai de porteur chaud sur les transistors MOS

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IEC 62416 ®
Edition 1.0 2010-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor devices – Hot carrier test on MOS transistors

Dispositifs à semiconducteurs – Essai de porteur chaud sur les transistors MOS

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
K
CODE PRIX
ICS 31.080 ISBN 978-2-88910-695-0
– 2 – 62416 © IEC:2010
CONTENTS
FOREWORD.3
1 Scope.5
2 Abbreviations and letter symbols .5
3 Test structures .6
4 Stress time .6
5 Stress conditions .6
6 Sample size.7
7 Temperature.7
8 Failure criteria .7
9 Lifetime estimation method.7
9.1 DC acceleration models .7
9.1.1 General .7
9.1.2 Method 1: extrapolation vs. drain currrent.8
9.1.3 Method 2: extrapolation vs. drain bias and channel length .8
9.2 AC estimation model .9
10 Lifetime requirements .9
11 Reporting .9
Bibliography.10

62416 © IEC:2010 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES –
HOT CARRIER TEST ON MOS TRANSISTORS

FOREWORD
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International Standard IEC 62416 has been prepared by IEC technical committee 47:
Semiconductor devices.
The text of this standard is based on the following documents:
FDIS Report on voting
47/2041/FDIS 47/2048/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.

– 4 – 62416 © IEC:2010
The committee has decided that the contents of this publication will remain unchanged until
the stability date indicated on the IEC web site under "http://webstore.iec.ch" in the data
related to the specific publication. At this date, the publication will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
62416 © IEC:2010 – 5 –
SEMICONDUCTOR DEVICES –
HOT CARRIER TEST ON MOS TRANSISTORS

1 Scope
This standard describes the wafer level hot carrier test on NMOS and PMOS transistors. The
test is intended to determine whether the single transistors in a certain (C)MOS process meet
the required hot carrier lifetime.
2 Abbreviations and letter symbols
In this document the following abbreviations and letter symbols apply:
MOS Metal Oxide Semiconductor
NMOS n-channel MOS transistor
PMOS p-channel MOS transistor
(C)MOS Complementary MOS
L [μm] length of polysilicon gate of MOS transistor
W [μm] width of polysilicon gate of MOS transistor
L [μm] minimum L allowed by the design rules of the process
nominal
W [μm] minimum W allowed by the design rules of the process
nominal
V [V] gate-source voltage of MOS transistor
gs
V [V] drain-source voltage of MOS transistor
ds
V [V] backgate-source voltage of MOS transistor
bs
I [μA]: drain-source current of MOS transistor
ds
I [μA] substrate current of MOS transistor
b
I [nA] gate current of MOS transistor
g
V [V] V biasing condition during hot carrier stress
gs,stress gs
V [V] V biasing condition during hot carrier stress
ds,stress ds
V [V] maximum V allowed by the design rules of the process as stated in the
ds,use_max ds
design manual
V [V] V at which avalanche or punch-through currents become dominant;
ds,breakdown ds
defined as V at which I = 1,5 × (I at V ) while V = V
ds ds ds ds,use_max gs ds,use_max
V [V] threshold voltage of MOS transistor defined as V voltage at which I =
t gs ds
0,01 × W / L [μA]. Other (commonly agreed) definitions of V are also
t
allowed as long as this is clearly reported.
g [μA/V] transconductance of MOS transistor
m
g [μA/V] maximum transconductance of MOS transistor
m,max
I [μA] saturated drain-source current at V = V = V ; I
ds,sat gs ds ds,use_,max ds,sat_forward
measured with source and drain having same polarity as during stress,
I measured with source and drain polarity interchanged with
ds,sat_reverse
respect to stress.
L( MOST) length of the square MOS transistor (L = W)
g ( MOST) g of the square MOS transistor (L = W)
m,max m,max
– 6 – 62416 © IEC:2010
τ[s] lifetime of the MOS transistor
L [μm] effective electrical channel length of MOS transistor; the L for a given L is
eff eff
determined using the g of a large ‘square ( )‘ MOS transistor with W =
m,max
L >> L .
nominal
3 Test structures
For the evaluation of the hot carrier degradation vulnerability of a technology, nominal
transistors (L = L ) are recommended. The following gate lengths are recommended
nominal
when lifetime extrapolation versus L is needed (see 9.1): L = 1,0 × L , L = 1,5 × L ,
nominal nominal
L = 2,0 × L , L = 5,0 × L , L = W.
nominal nominal
Gates and sources of the transistors may be combined to redu
...