Ferrite cores - Guidelines on dimensions and the limits of surface irregularities - Part 9: Planar cores

IEC 63093-9:2020 specifies the shapes and dimensions of ferrite cores for inductive components (transformers and chokes), whose the coil is typically made of multi-layer boards (or the coil is part of the motherboard), and the effective parameter values used in calculations. This document gives guidelines on allowable limits of surface irregularities applicable to planar-cores as well.
This document is considered as a sectional specification useful in the negotiation between ferrite core suppliers and users about surface irregularities.
This first edition cancels and replaces the first edition of IEC 60424-5 published in 2009 and first edition of IEC 62317-9 published in 2006 and its Amendment 1:2007. This edition constitutes a technical revision.
This edition includes the following significant technical changes with respect to the previous editions of IEC 60424-5 and IEC 62317-9:
a) IEC 63093-9 integrates IEC 60424-5 and IEC 62317-9;
b) Table 1, Table 2 and Table 3 in IEC 60424-5:2009 have been moved to Annex B;
c) some numbers are corrected in Table 4;
d) Table 6 is amended following IEC 60205.

Noyaux ferrites - Lignes directrices relatives aux dimensions et aux limites des irrégularités de surface - Partie 9: Noyaux planaires

L’IEC 63093-9:2020 spécifie les formes et dimensions des noyaux ferrites pour les composants inductifs (transformateurs et inductances) dont la bobine est généralement composée de la carte multicouche (ou la bobine fait partie de la carte mère) et des valeurs de paramètres effectifs utilisés dans les calculs. Le présent document donne des lignes directrices relatives aux limites admissibles des irrégularités de surface applicables également aux noyaux planaires.
Le présent document est considéré comme une spécification intermédiaire utile dans les négociations entre les fournisseurs de noyaux ferrites et leurs utilisateurs portant sur les irrégularités de surface.
Cette première édition annule et remplace la première édition de l’IEC 60424-5 parue en 2009 et la première édition de l’IEC 62317-9 parue en 2006 et son Amendement 1:2007. Cette édition constitue une révision technique.
Cette édition inclut les modifications techniques majeures suivantes par rapport aux éditions précédentes de l’IEC 60424-5 et l’IEC 62317-9:
a) l’IEC 63093-9 réunit l’IEC 60424-5 et l’IEC 62317-9;
b) le Tableau 1, le Tableau 2 et le Tableau 3 contenus dans l’IEC 60424-5:2009 ont été déplacés vers l’Annexe B;
c) certains chiffres du Tableau 4 sont corrigés;
d) le Tableau 6 est modifié sur la base de l’IEC 60205.

General Information

Status
Published
Publication Date
15-Apr-2020
Current Stage
PPUB - Publication issued
Completion Date
16-Apr-2020
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IEC 63093-9
Edition 1.0 2020-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Ferrite cores – Guidelines on dimensions and the limits of
surface irregularities –
Part 9: Planar-cores
Noyaux ferrites – Lignes directrices relatives aux dimensions
et aux limites des irrégularités de surface –
Partie 9: Noyaux planaires
IEC 63093-9:2020-04(en-fr)
---------------------- Page: 1 ----------------------
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---------------------- Page: 2 ----------------------
IEC 63093-9
Edition 1.0 2020-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Ferrite cores – Guidelines on dimensions and the limits of
surface irregularities –
Part 9: Planar-cores
Noyaux ferrites – Lignes directrices relatives aux dimensions
et aux limites des irrégularités de surface –
Partie 9: Noyaux planaires
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 29.100.10 ISBN 978-2-8322-8080-5

Warning! Make sure that you obtained this publication from an authorized distributor.

Attention! Veuillez vous assurer que vous avez obtenu cette publication via un distributeur agréé.

® Registered trademark of the International Electrotechnical Commission
Marque déposée de la Commission Electrotechnique Internationale
---------------------- Page: 3 ----------------------
– 2 – IEC 63093-9:2020 © IEC 2020
CONTENTS

FOREWORD ........................................................................................................................... 4

INTRODUCTION ..................................................................................................................... 6

1 Scope .............................................................................................................................. 7

2 Normative references ...................................................................................................... 7

3 Terms and definitions ...................................................................................................... 7

4 Primary dimensions ......................................................................................................... 7

4.1 Planar shapes and dimensions ............................................................................... 7

4.2 Dimensions and effective parameters of planar EL-core and mating PLT-core ........ 8

4.3 Dimensions and effective parameters of low-profile E-core and mating PLT-

core ...................................................................................................................... 10

4.4 Dimensions and effective parameters of low-profile ER-core and mating

PLT-core ............................................................................................................... 12

5 Limits of surface irregularities ........................................................................................ 15

5.1 General ................................................................................................................. 15

5.2 Examples of surface irregularities ......................................................................... 16

5.3 Chips and ragged edges ....................................................................................... 17

5.3.1 General ......................................................................................................... 17

5.3.2 Chips and ragged edges on the mating surfaces ............................................ 17

5.3.3 Chips and ragged edges on other surfaces .................................................... 18

5.4 Cracks .................................................................................................................. 20

5.5 Flash .................................................................................................................... 20

5.6 Pull-outs ............................................................................................................... 20

5.7 Crystallites ............................................................................................................ 24

5.8 Pores .................................................................................................................... 24

Annex A (normative) Low-profile core design ....................................................................... 26

A.1 General design ..................................................................................................... 26

A.2 EL-core design ...................................................................................................... 26

A.3 ER-core design ..................................................................................................... 27

Annex B (informative) Reference values of allowable areas of chips .................................... 29

Bibliography .......................................................................................................................... 31

Figure 1 – Planar EL-core and mating PLT-core...................................................................... 8

Figure 2 – Low-profile E-core and mating PLT-core .............................................................. 10

Figure 3 – Low-profile ER-core and mating PLT-core ............................................................ 12

Figure 4 – Examples of surface irregularities for planar EL-core ........................................... 16

Figure 5 – Examples of surface irregularities for low-profile E-core ....................................... 16

Figure 6 – Examples of surface irregularities for low-profile ER-core..................................... 16

Figure 7 – Chip location for planar EL-core ........................................................................... 17

Figure 8 – Chip location for low-profile E-core ...................................................................... 17

Figure 9 – Chip location for low-profile ER-core .................................................................... 17

Figure 10 – Cracks and pull-out location for planar EL-core .................................................. 20

Figure 11 – Cracks and pull-out location for low-profile E-core .............................................. 21

Figure 12 – Cracks and pull-out location for low-profile ER-core ........................................... 21

Figure 13 – Reference dimensions for EL-core ..................................................................... 21

---------------------- Page: 4 ----------------------
IEC 63093-9:2020 © IEC 2020 – 3 –

Figure 14 – Reference dimensions for E-core ....................................................................... 22

Figure 15 – Reference dimensions for ER-core ..................................................................... 23

Figure 16 – Example of the location of a crystallite on planar EL-core ................................... 24

Figure 17 – Example of the location of a crystallite on low-profile E-core .............................. 24

Figure 18 – Example of the location of a crystallite on low-profile ER-core ............................ 24

Figure 19 – Example of the location of a pore on planar EL-core .......................................... 25

Figure 20 – Example of the location of a pore on low-profile E-core ...................................... 25

Figure 21 – Example of the location of a pore on low-profile ER-core .................................... 25

Table 1 – Dimensions of planar EL-core EL and mating PLT-core ........................................... 9

Table 2 – Effective parameter values and A values .......................................................... 10

min

Table 3 – Dimensions of low-profile E-core and mating PLT-core .......................................... 11

Table 4 – Effective parameter values and A values .......................................................... 12

min

Table 5 – Dimensions of low-profile ER-core and mating PLT-core ....................................... 13

Table 6 – Effective parameter values and A values .......................................................... 14

min

Table 7 – Area and length reference for visual inspection ..................................................... 19

Table 8 – Limits of cracks for planar EL-core ........................................................................ 22

Table 9 – Limits of cracks for low-profile E-core .................................................................... 23

Table 10 – Limits of cracks for low-profile ER-core ............................................................... 23

Table A.1 – Sizes and design ratios for ER-core ................................................................... 28

Table B.1 – Allowable areas of chips for planar EL-core ....................................................... 29

Table B.2 – Allowable areas of chips for low-profile E-core ................................................... 29

Table B.3 – Allowable areas of chips for low-profile ER-core................................................. 30

---------------------- Page: 5 ----------------------
– 4 – IEC 63093-9:2020 © IEC 2020
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
FERRITE CORES – GUIDELINES ON DIMENSIONS AND
THE LIMITS OF SURFACE IRREGULARITIES –
Part 9: Planar-cores
FOREWORD

1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising

all national electrotechnical committees (IEC National Committees). The object of IEC is to promote

international co-operation on all questions concerning standardization in the electrical and electronic fields. To

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2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international

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8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is

indispensable for the correct application of this publication.

9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of

patent rights. IEC shall not be held responsible for identifying any or all such patent rights.

International Standard IEC 63093-9 has been prepared by IEC technical committee 51:

Magnetic components, ferrite and magnetic powder materials.

This first edition cancels and replaces the first edition of IEC 60424-5 published in 2009 and

first edition of IEC 62317-9 published in 2006 and its Amendment 1:2007. This edition

constitutes a technical revision.

This edition includes the following significant technical changes with respect to the previous

editions of IEC 60424-5 and IEC 62317-9:
a) IEC 63093-9 integrates IEC 60424-5 and IEC 62317-9;
b) Table 1, Table 2 and Table 3 in IEC 60424-5:2009 have been moved to Annex B;
c) some numbers are corrected in Table 4;
d) Table 6 is amended following IEC 60205.
---------------------- Page: 6 ----------------------
IEC 63093-9:2020 © IEC 2020 – 5 –
The text of this International Standard is based on the following documents:
CDV Report on voting
51/1308/CDV 51/1326/RVC

Full information on the voting for the approval of this International Standard can be found in

the report on voting indicated in the above table.

This document has been drafted in accordance with the ISO/IEC Directives, Part 2.

A list of all parts in the IEC 63093 series, published under the general title Ferrite cores –

Guidelines on dimensions and the limits of surface irregularities, can be found on the IEC

website.

The committee has decided that the contents of this document will remain unchanged until the

stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to

the specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
---------------------- Page: 7 ----------------------
– 6 – IEC 63093-9:2020 © IEC 2020
INTRODUCTION

Today, DC-to-DC converter power supplies increasingly employ transformers and chokes, the

windings of which are made of multi-layer printed circuit boards or are constructed in the

motherboard, rather than the transformers wound by conventional copper wires. This

document specifies the optimum shapes and dimensions of cores for surface mounted devices

(SMDs) and of cores for which the windings are constructed in the motherboard. The

motherboard has slots cut out to accept the ferrite cores. This is called the total integration in

a multi-layer motherboard. The core shape specified in this document satisfies the demand for

lower profile as well as for smaller floor space.

The relations between the main dimensions of planar E-, ER- and EL-cores differ from those

of standard cores. For example, the width of planar-cores is larger while the total height is

much smaller. Also the thickness of the legs is in most cases smaller than compared to

standard cores. Therefore the concept of fixed reference dimensions to determine the length

of crack limits yields crack lengths which are not acceptable for this type of core. This

document follows another concept which relates the crack length to dimensions of the surface

on which the crack occurs.

Also the concept to determine the maximum area of chips based on the total mating surface

fails in the case of planar-cores. The outer legs of planar-cores are much thinner than those

of standard cores which makes overlapping and gluing much more difficult. A single chip of

maximum size on the outer leg can affect the functionality of the core set. Therefore this

document uses as a reference the mating surface on which the chip occurs.

Windings of planar-cores are often PCBs which are glued to the inner surfaces of the planar-

core. For this reason the inner surfaces of the planar-cores should have a better quality than

the inner surfaces of standard cores. This was taken into account by reducing the maximum

allowable area of pull-outs in the inner surfaces.
---------------------- Page: 8 ----------------------
IEC 63093-9:2020 © IEC 2020 – 7 –
FERRITE CORES – GUIDELINES ON DIMENSIONS AND
THE LIMITS OF SURFACE IRREGULARITIES –
Part 9: Planar-cores
1 Scope

This part of IEC 63093 specifies the shapes and dimensions of ferrite cores for inductive

components (transformers and chokes), whose the coil is typically made of multi-layer boards

(or the coil is part of the motherboard), and the effective parameter values used in

calculations. This document gives guidelines on allowable limits of surface irregularities

applicable to planar-cores as well.

This document is considered as a sectional specification useful in the negotiation between

ferrite core suppliers and users about surface irregularities.

The general consideration upon which the design of this range of cores is based is given in

Annex A.
2 Normative references

The following documents are referred to in the text in such a way that some or all of their

content constitutes requirements of this document. For dated references, only the edition

cited applies. For undated references, the latest edition of the referenced document (including

any amendments) applies.
IEC 60205:2016, Calculation of the effective parameters of magnetic piece parts

IEC 60401-1, Terms and nomenclature for cores made of magnetically soft ferrites – Part 1:

Terms used for physical irregularities

IEC 60424-1, Ferrite cores – Guidelines on the limits of surface irregularities – Part 1:

General specification
3 Terms and definitions

For the purpose of this document, the terms and definitions given in IEC 60401-1 and

IEC 60424-1 apply.

ISO and IEC maintain terminological databases for use in standardization at the following

addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
4 Primary dimensions
4.1 Planar shapes and dimensions

The main shapes and dimensions shall be as given in the following figures and tables.

The main shapes, dimensions, and parameters for EL-cores are given in:
---------------------- Page: 9 ----------------------
– 8 – IEC 63093-9:2020 © IEC 2020
• Figure 1 – Planar EL-core- and mating PLT-core;
• Table 1 – Dimensions of planar EL-core and mating PLT-core;
• Table 2 – Effective parameter values and A values.
min
The main shape, dimensions, and parameters for low-profile E-cores are given in:
• Figure 2 – Low-profile E-core and mating PLT-core;
• Table 3 – Dimensions of low-profile E-core and mating PLT-core;
• Table 4 – Effective parameter values and A values.
min
The main shape, dimensions, and parameters for ER-cores are given in:
• Figure 3 – Low-profile ER-core and mating PLT-core;
• Table 5 – Dimensions of low-profile ER-core and mating PLT-core;
• Table 6 – Effective parameter values and A values.
min

A uniform dimensional nomenclature has been chosen in order to facilitate a comparison of

major physical attributes among the different core shapes.
4.2 Dimensions and effective parameters of planar EL-core and mating PLT-core

For the definitions of effective parameters and their calculations, reference shall be made to

IEC 60205.
Figure 1 – Planar EL-core and mating PLT-core
---------------------- Page: 10 ----------------------
IEC 63093-9:2020 © IEC 2020 – 9 –
Table 1 – Dimensions of planar EL-core EL and mating PLT-core
Dimensions in millimetres
Size A B B C D E F F R
1 2 1 2 2
10,80 1,91 8,60 0,90 8,97 2,68 6,25
0,3
EL11 × 2,0 min.
11,20 2,11 9,00 1,10 9,37 2,88 6,55
max.
EL11 × 3,0 min. 10,80 2,91 8,60 1,90 8,97 2,68 6,25
0,3
max. 11,20 3,11 9,00 2,10 9,37 2,88 6,55
PLT11 × 1,0 min. 10,80 0,96 8,60
max. 11,20 1,06 9,00
EL13 × 2,2 min. 12,75 2,09 10,20 0,90 10,63 3,19 7,41
0,3
max. 13,25 2,29 10,60 1,10 11,03 3,39 7,71
EL13 × 3,2 min. 12,75 3,09 10,20 1,90 10,63 3,19 7,41
0,3
max. 13,25 3,29 10,60 2,10 11,03 3,39 7,71
PLT13 × 1,2 min. 12,75 1,14 10,20
max. 13,25 1,24 10,60
EL15,5 × 2,9 min. 15,20 2,82 12,15 1,40 12,67 3,82 8,81
0,3
max. 15,80 3,02 12,65 1,60 13,17 4,02 9,21
EL15,5 × 4,4 min. 15,20 4,32 12,15 2,90 12,67 3,82 8,81
0,3
max. 15,80 4,52 12,65 3,10 13,17 4,02 9,21
PLT15,5 × 1,4 min. 15,20 1,32 12,15
max. 15,80 1,52 12,65
EL18 × 3,7 min. 17,70 3,55 14,15 1,90 14,70 4,45 10,27
0,3
max. 18,30 3,75 14,65 2,10 15,30 4,65 10,67
EL18 × 5,7 min. 17,70 5,55 14,15 3,85 14,70 4,45 10,27
0,3
max. 18,30 5,75 14,65 4,15 15,30 4,65 10,67
PLT18 × 1,7 min. 17,70 1,55 14,15
max. 18,30 1,75 14,65
EL20 × 3,8 min. 19,65 3,73 15,70 1,90 16,37 4,91 11,43
0,5
max. 20,35 3,93 16,30 2,10 16,97 5,21 11,83
EL20 × 5,8 min. 19,65 5,68 15,70 3,85 16,37 4,91 11,43
0,5
max. 20,35 5,98 16,30 4,15 16,97 5,21 11,83
PLT20 × 1,8 min. 19,65 1,73 15,70
max. 20,35 1,93 16,30
EL22 × 4,0 min. 21,60 3,92 17,30 1,90 17,98 5,41 12,54
0,5
max. 22,40 4,12 17,90 2,10 18,68 5,71 13,04
EL22 × 6,0 min. 21,60 5,87 17,30 3,85 17,98 5,41 12,54
0,5
max. 22,40 6,17 17,90 4,15 18,68 5,71 13,04
PLT22 × 2,0 min. 21,60 1,92 17,30
max. 22,40 2,12 17,90
EL25 × 4,3 min. 24,55 4,19 19,65 1,90 20,48 6,17 14,29
0,5
max. 25,45 4,39 20,35 2,10 21,18 6,47 14,79
EL25 × 6,3 min. 24,55 6,14 19,65 3,85 20,48 6,17 14,29
0,5
max 25,45 6,44 20,35 4,15 21,18 6,47 14,79
PLT25 × 2,3 min. 24,55 2,19 19,65
max. 25,45 2,39 20,35
---------------------- Page: 11 ----------------------
– 10 – IEC 63093-9:2020 © IEC 2020
Table 2 – Effective parameter values and A values
min
C C l A V A
min
1 2 e e e
Size Remarks
–1 –3 2 3 2
mm mm mm mm mm mm
EL-EL11 × 4,0 0,826 45 49,923 × 10 13,7 16,5 226 15,9 The
combination
EL-EL13 × 4,4 0,666 66 28,815 × 10 15,4 23,1 357 22,4
EL-EL refers
EL-EL15,5 × 5,8 0,596 74 18,143 × 10 19,6 32,9 646 31,9
to two shorter
height EL-
EL-EL18 × 7,3 0,538 30 12,162 × 10 23,8 44,3 1 050 43,0
cores for
size-
EL-EL20 × 7,7 0,468 64 8,586 6 × 10 25,6 54,6 1 400 52,9
designation.
EL-EL22 × 8,0 0,412 80 6,231 4 × 10 27,3 66,2 1 810 64,2 The
combination
EL-EL25 × 8,6 0,350 34 4,094 2 × 10 30,0 85,6 2 570 83,0
EL-PLT refers
EL-PLT11 × 4,0 0,826 45 49,943 × 10 13,7 16,5 226 15,9
to one taller
height EL
EL-PLT13 × 4,4 0,666 66 28,815 × 10 15,4 23,1 357 22,4
core paired
with one PLT-
EL-PLT15,5 × 5,8 0,569 74 18,143 × 10 19,6 32,9 646 31,9
core for each
EL-PLT18 × 7,3 0,538 30 12,162 × 10 23,8 44,3 1 050 43,0
size-
designation.
EL-PLT20 × 7,7 0,468 64 8,586 6 × 10 25,6 54,6 1 400 52,9
EL-PLT22 × 8,0 0,412 80 6,231 4 × 10 27,3 66,2 1 810 64,2
EL-PLT25 × 8,6 0,350 34 4,094 2 × 10 30,0 85,6 2 570 83,0
EL-PLT11 × 3,0 0,701 76 42,170 × 10 11,7 16,6 194 15,9
EL-PLT13 × 3,4 0,577 71 24,857 × 10 13,4 23,2 312 22,4
EL-PLT15,5 × 4,3 0,502 96 15,212 × 10 16,6 33,1 550 31,9
EL-PLT18 × 5,3 0,445 54 10,011 × 10 19,8 44,5 882 43,0
EL-PLT20 × 5,7 0,392 32 7,167 9 × 10 21,6 54,9 1 180 52,9
EL-PLT22 × 6,0 0,350 61 5,264 5 × 10 23,4 66,6 1 560 64,2
EL-PLT25 × 6,6 0,302 22 3,515 6 × 10 26,0 86,0 2 230 83,0
See 4.2 of IEC 60205:2016 for the definition of A .
min

4.3 Dimensions and effective parameters of low-profile E-core and mating PLT-core

For the definitions of effective parameters and their calculations, reference shall be made to

IEC 60205.
Figure 2 – Low-profile E-core and mating PLT-core
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IEC 63093-9:2020 © IEC 2020 – 11 –
Table 3 – Dimensions of low-profile E-core and mating PLT-core
Dimensions in millimetres
Size A B B C D E F
1 2
E14 × 3,5 × 5 min. 13,70 3,40 4,90 1,90 10,75 2,95
max. 14,30 3,60 5,10 2,10 11,25 3,05
PLT14 × 1,5 × 5 min. 13,70 1,40 4,90
max. 14,30 1,60 5,10
E18
...

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