ISO/IEC TR 14496-9:2008
(Main)Information technology — Coding of audio-visual objects — Part 9: Reference hardware description
Information technology — Coding of audio-visual objects — Part 9: Reference hardware description
The main goal of ISO/IEC TR 14496-9:2008 is to facilitate a more widespread use of the MPEG-4 standard. Design methodologies of the EDA industry have evolved from schematics to Hardware Description Languages (HDLs) to address the needs of the vast number of gates available on a single device. The increased number of gates allowed more elaborate algorithms to be deployed but also required a shift in design paradigm to handle the complexity created. Through HDLs, more complicated systems could be designed faster through the enabling technology of synthesis of the HDL code towards different silicon technologies where trade offs could be explored. Now the EDA industry again faces challenges where HDLs may not provide the level of abstraction needed for system designers to evaluate system level parameters and complexity issues. There have been a number of tool investigations under way to address this problem. Profiling tools aid in exposing bottlenecks in an abstract way so that early design decisions can be made. C to gates tools allow a C based simulation environment while also enabling direct synthesis to gates for hardware acceleration. In conclusion, it is the aim of this ISO/IEC TR 14496-9:2008 to enable more widespread use of the MPEG-4 standard through reference hardware descriptions and close integration with ISO/IEC TR 14496-7 (MPEG-4 Part 7 Optimized Reference Software). Additionally, it is aimed that exposure to such a platform will enable a more systematic way to investigate the complexity of new codecs and open up the algorithm search space with an order of magnitude more compute cycles.
Technologies de l'information — Codage des objets audiovisuels — Partie 9: Description de matériel de référence
General Information
Relations
Buy Standard
Standards Content (Sample)
TECHNICAL ISO/IEC
REPORT TR
14496-9
Second edition
2008-08-15
Information technology — Coding of
audio-visual objects —
Part 9:
Reference hardware description
Technologies de l'information — Codage des objets audiovisuels —
Partie 9: Description de matérial de référence
Reference number
ISO/IEC TR 14496-9:2008(E)
©
ISO/IEC 2008
---------------------- Page: 1 ----------------------
ISO/IEC TR 14496-9:2008(E)
PDF disclaimer
PDF files may contain embedded typefaces. In accordance with Adobe's licensing policy, such files may be printed or viewed but shall
not be edited unless the typefaces which are embedded are licensed to and installed on the computer performing the editing. In
downloading a PDF file, parties accept therein the responsibility of not infringing Adobe's licensing policy. The ISO Central Secretariat
accepts no liability in this area.
Adobe is a trademark of Adobe Systems Incorporated.
Details of the software products used to create the PDF file(s) constituting this document can be found in the General Info relative to
the file(s); the PDF-creation parameters were optimized for printing. Every care has been taken to ensure that the files are suitable for
use by ISO member bodies. In the unlikely event that a problem relating to them is found, please inform the Central Secretariat at the
address given below.
This CD-ROM contains:
1) the publication ISO/IEC TR 14496-9:2008 in portable document format (PDF), which can be viewed
using Adobe® Acrobat® Reader;
2) "Alveiro University" Software Package
3) "Calgary Platform" Software package
4) "Dublin University HDL modules" Software Package
5) "University of Calgary HDL modules" Software Package
6) "Xilinx Platform" Software package.
Adobe and Acrobat are trademarks of Adobe Systems Incorporated.
.
This second edition cancels and replaces the first edition (ISO/IEC TR 14496-9:2004) which has been
technically revised.
COPYRIGHT PROTECTED DOCUMENT
© ISO/IEC 2008
All rights reserved. Unless required for installation or otherwise specified, no part of this CD-ROM may be reproduced, stored in a retrieval
system or transmitted in any form or by any means without
...
TECHNICAL ISO/IEC
REPORT TR
14496-9
Second edition
2008-08-15
Information technology — Coding of
audio-visual objects —
Part 9:
Reference hardware description
Technologies de l'information — Codage des objets audiovisuels —
Partie 9: Description de matériel de référence
Reference number
ISO/IEC TR 14496-9:2008(E)
©
ISO/IEC 2008
---------------------- Page: 1 ----------------------
ISO/IEC TR 14496-9:2008(E)
PDF disclaimer
This PDF file may contain embedded typefaces. In accordance with Adobe's licensing policy, this file may be printed or viewed but
shall not be edited unless the typefaces which are embedded are licensed to and installed on the computer performing the editing. In
downloading this file, parties accept therein the responsibility of not infringing Adobe's licensing policy. The ISO Central Secretariat
accepts no liability in this area.
Adobe is a trademark of Adobe Systems Incorporated.
Details of the software products used to create this PDF file can be found in the General Info relative to the file; the PDF-creation
parameters were optimized for printing. Every care has been taken to ensure that the file is suitable for use by ISO member bodies. In
the unlikely event that a problem relating to it is found, please inform the Central Secretariat at the address given below.
COPYRIGHT PROTECTED DOCUMENT
© ISO/IEC 2008
All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form or by any means,
electronic or mechanical, including photocopying and microfilm, without permission in writing from either ISO at the address below or
ISO's member body in the country of the requester.
ISO copyright office
Case postale 56 • CH-1211 Geneva 20
Tel. + 41 22 749 01 11
Fax + 41 22 749 09 47
E-mail copyright@iso.org
Web www.iso.org
Published in Switzerland
ii © ISO/IEC 2008 – All rights reserved
---------------------- Page: 2 ----------------------
ISO/IEC TR 14496-9:2008(E)
Contents Page
Foreword .v
Introduction.vii
1 Scope.1
2 Copyright disclaimer for HDL software modules.1
3 Abbreviated terms.2
4 HDL software availability.2
5 HDL coding format and standards .2
5.1 HDL standards and libraries .2
5.2 Conditions and tools for the synthesis of HDL modules.3
5.3 Conformance with the reference software .3
6 Integrated Framework supporting the “Virtual Socket” between HDL modules described
in Part 9 and the MPEG Reference Software (Implementation 1).3
6.1 Introduction.3
6.2 Addressing.4
6.3 Memory Map.4
6.4 Hardware Accelerator Interface.6
6.5 User Hardware Accelerator Sockets.12
7 Integrated Framework supporting the “Virtual Socket” between HDL modules described
in Part 9 and the MPEG Reference Software (Implementation 2).14
7.1 Introduction.14
7.2 Development Example of a Typical Module : Calc_Sum_Product Module .14
7.3 Second Example of a Typical Module : fifo_transfer module.19
7.4 Integrating the Multi-Modules within the Framework .23
7.5 Calc_Sum_Product Module Controller (memory data transfer) .29
7.6 Simulation of the whole system.44
7.7 Debug Menu.45
8 Integrated Framework supporting the “Virtual Socket” between HDL modules described
in Part 9 and the MPEG Reference Software (Implementation 3).47
8.1 An Integrated Virtual Socket Hardware-Accelerated Co-design Platform for MPEG-4.47
8.2 Reference for Virtual Socket API Function Calls .73
8.3 Tutorial on the Integrated Virtual Socket Hardware-Accelerated Co-design Platform for
MPEG-4 Part 9 Implementation 3 .98
8.4 An Integration of the MPEG-4 Part 10/AVC DCT/Q Hardware Module into the Virtual
Socket Co-design Platform .142
8.5 Migrating Virtual Socket Hardware-Accelerated Co-design Platform From WildCard-II to
WildCard-4.155
9 Integrated Framework supporting the “Virtual Socket” between HDL modules described
in Part 9 and the MPEG Reference Software: Implementation 4 - Virtual Memory
Extension .168
9.1 Introduction.168
9.2 Overview of the “Virtual Socket Platform” implementation 4 .168
9.3 Development information .172
9.4 Technical details.173
9.5 How to build the platform .196
9.6 Simulation of the platform.203
9.7 Synthesis of the platform .209
9.8 Building the platform system software.213
9.9 How to use the platform.214
© ISO/IEC 2008 – All rights reserved iii
---------------------- Page: 3 ----------------------
ISO/IEC TR 14496-9:2008(E)
9.10 Understanding VHDL code .216
9.11 Appendix.221
9.12 Glossary.223
10 HDL MODULES.226
10.1 INVERSE QUANTIZER HARDWARE IP BLOCK FOR MPEG-4 PART 2.226
10.2 2-D IDCT HARDWARE IP BLOCK FOR MPEG-4 PART 2.232
10.3 VLD+IQ+IDCT for MPEG-4.242
10.4 A SYSTEM C MODEL FOR 2X2 HADAMARD TRANSFORM AND QUANTIZATION FOR
MPEG–4 PART 10.247
10.5 A VHDL HARDWARE BLOCK FOR 2X2 HADAMARD TRANSFORM AND QUANTIZATION
WITH APPLICATION TO MPEG–4 PART 10 AVC .255
10.6 A SYSTEMC MODEL FOR 4X4 HADAMARD TRANSFORM AND QUANTIZATION FOR
MPEG-4 PART 10 .261
10.7 A VHDL HARDWARE IP BLOCK FOR 4X4 HADAMARD TRANSFORM AND QUANTIZATION
FOR MPEG-4 PART 10 AVC .269
10.8 A HARDWARE BLOCK FOR THE MPEG-4 PART 10 4X4 DCT-LIKE TRANSFORMATION
AND QUANTIZATION.275
10.9 A SYSTEMC MODEL FOR THE MPEG-4 PART 10 4X4 DCT-LIKE TRANSFORMATION AND
QUANTIZATION.281
10.10 A 8X8 INTEGER APPROXIMATION DCT TRANSFORMATION AND QUANTIZATION
SYSTEMC IP BLOCK FOR MPEG-4 PART 10 AVC .289
10.11 INTEGER APPROXIMATION OF 8X8 DCT TRANSFORMATION AND QUANTIZATION, A
HARDWARE IP BLOCK FOR MPEG-4 PART 10 AVC .299
10.12 A VHDL CONTEXT-BASED ADAPTIVE VARIABLE LENGTH CODING (CAVLC) IP BLOCK
FOR MPEG-4 PART 10 AVC .306
10.13 A VERILOG HARDWARE IP BLOCK FOR SA-DCT FOR MPEG-4 .311
10.14 A VERILOG HARDWARE IP BLOCK FOR SA-IDCT FOR MPEG-4 .322
10.15 A VERILOG HARDWARE IP BLOCK FOR 2D-DCT (8X8).335
10.16 SHAPE CODING BINARY MOTION ESTIMATION HARDWARE ACCELERATION MODULE .344
10.17 A SIMD ARCHITECTURE FOR FULL SEARCH BLOCK MATCHING ALGORITHM .358
10.18 HARDWARE MODULE FOR MOTION ESTIMATION (4xPE) .367
10.19 A IP BLOCK FOR H.264/AVC QUARTER PEL FULL SEARCH VARIABLE BLOCK MOTION
ESTIMATION.381
10.20 AN IP BLOCK FOR VARIABLE BLOCK SIZE MOTION ESTIMATION IN H.264/MPEG-4 AVC.390
10.21 An IP Block for AVC Deblocking Filter .400
Annex A (Informative) Specification of directory structure for reference SW, HDL and
documentation files of MPEG-4 Part 9 Reference HW Description.409
A.1 Introduction.409
A.2 Directory Structure of TR SW Modules .409
A.3 Additional Section in Contribution Document (e.g. SA-DCT) .410
CVS Module Name .410
Integration Framework Version.411
Reference Software Version and Modifications .411
Annex B (Informative) Tutorial on Part 9 CVS Client Installation & Operation.412
B.1 Introduction.412
B.2 Tools for accessing the EPFL CVS repository .412
B.3 Basic CVS commands.420
Annex C (Informative) Additional utility software.422
Annex D (Informative) Providers of reference hardware code .423
Bibliography .424
iv © ISO/IEC 2008 – All rights reserved
---------------------- Page: 4 ----------------------
ISO/IEC TR 14496-9:2008(E)
Foreword
ISO (the International Organization for Standardization) and IEC (the International Electrotechnical
Commission) form the specialized system for worldwide standardization. National bodies that are members of
ISO or IEC participate in the development of International Standards through technical committees
established by the respective organization to deal with particular fields of technical activity. ISO and IEC
technical committees collaborate in fields of mutual interest. Other international organizations, governmental
and non-governmental, in liaison with ISO and IEC, also take part in the work. In the field of information
technology, ISO and IEC have established a joint technical committee, ISO/IEC JTC 1.
International Standards are drafted in accordance with the rules given in the ISO/IEC Directives, Part 2.
The main task of the joint technical committee is to prepare International Standards. Draft International
Standards adopted by the joint technical committee are circulated to national bodies for voting. Publication as
an International Standard requires approval by at least 75 % of the national bodies casting a vote.
In exceptional circumstances, the joint technical committee may propose the publication of a Technical Report
of one of the following types:
⎯ type 1, when the required support cannot be obtained for the publication of an International Standard,
despite repeated efforts;
⎯ type 2, when the subject is still under technical development or where for any other reason there is the
future but not immediate possibility of an agreement on an International Standard;
⎯ type 3, when the joint technical committee has collected data of a different kind from that which is
normally published as an International Standard (“state of the art”, for example).
Technical Reports of types 1 and 2 are subject to review within three years of publication, to decide whether
they can be transformed into International Standards. Technical Reports of type 3 do not necessarily have to
be reviewed until the data they provide are considered to be no longer valid or useful.
Attention is drawn to the possibility that some of the elements of this document may be the subject of patent
rights. ISO and IEC shall not be held responsible for identifying any or all such patent rights.
ISO/IEC TR 14496-9, which is a Technical Report of type [3], was prepared by Joint Technical Committee
ISO/IEC JTC 1, Information technology, Subcommittee SC 29, Coding of audio, picture, multimedia and
hypermedia information.
This second edition cancels and replaces the first edition (ISO/IEC TR 14496-9:2004) which has been
technically revised.
ISO/IEC TR 14496 consists of the following parts, under the general title Information technology — Coding of
audio-visual objects:
⎯ Part 1: Systems
⎯ Part 2: Visual
⎯ Part 3: Audio
⎯ Part 4: Conformance testing
⎯ Part 5: Reference software
© ISO/IEC 2008 – All rights reserved v
---------------------- Page: 5 ----------------------
ISO/IEC TR 14496-9:2008(E)
⎯ Part 6: Delivery Multimedia Integration Framework (DMIF)
⎯ Part 7: Optimized reference software for coding of audio-visual objects [Technical Report]
⎯ Part 8: Carriage of ISO/IEC 14496 contents over IP networks
⎯ Part 9: Reference hardware description [Technical Report]
⎯ Part 10: Advanced Video Coding
⎯ Part 11: Scene description and application engine
⎯ Part 12: ISO base media file format
⎯ Part 13: Intellectual Property Management and Protection (IPMP) extensions
⎯ Part 14: MP4 file format
⎯ Part 15: Advanced Video Coding (AVC) file format
⎯ Part 16: Animation Framework eXtension (AFX)
⎯ Part 17: Streaming text format
⎯ Part 18: Font compression and streaming
⎯ Part 19: Synthesized texture stream
⎯ Part 20: Lightweight Application Scene Representation (LASeR) and Simple Aggregation Format (SAF)
⎯ Part 21: MPEG-J Graphics Framework eXtensions (GFX)
⎯ Part 22: Open font format
⎯ Part 23: Symbolic Music Representation
⎯ Part 24: Audio and systems interaction [Technical Report]
⎯ Part 25: 3D Graphics Compression Model
vi © ISO/IEC 2008 – All rights reserved
---------------------- Page: 6 ----------------------
ISO/IEC TR 14496-9:2008(E)
Introduction
The main goal of this Technical Report is to facilitate a more widespread use of the MPEG-4 standard.
Design methodologies of the EDA industry have evolved from schematics to Hardware Description Languages
(HDLs) to address the needs of the vast number of gates available on a single device. The increased number
of gates allowed more elaborate algorithms to be deployed but also required a shift in design paradigm to
handle the complexity created. Through HDLs, more complicated systems could be designed faster through
the enabling technology of synthesis of the HDL code towards different silicon technologies where trade offs
could be explored. Now the EDA industry again faces challenges where HDLs may not provide the level of
abstraction needed for system designers to evaluate system level parameters and complexity issues. There
have been a number of tool investigations under way to address this problem. Profiling tools aid in exposing
bottlenecks in an abstract way so that early design decisions can be made. C to gates tools allow a C based
simulation environment while also enabling direct synthesis to gates for hardware acceleration.
In conclusion, it is the aim of this Technical Report to enable more widespread use of the MPEG-4 standard
through reference hardware descriptions and close integration with ISO/IEC TR 14496-7 (MPEG-4 Part 7
Optimized Reference Software). Additionally, it is aimed that exposure to such a platform will enable a more
systematic way to investigate the complexity of new codecs and open up the algorithm search space with an
order of magnitude more compute cycles.
© ISO/IEC 2008 – All rights reserved vii
---------------------- Page: 7 ----------------------
TECHNICAL REPORT ISO/IEC TR 14496-9:2008(E)
Information technology — Coding of audio-visual objects —
Part 9:
Reference hardware description
1 Scope
This Technical Report specifies descriptions of the main video coding tools in hardware description language
(HDL) form. Such alternative descriptions to the ones that are reported in ISO/IEC 14496-2, ISO/IEC 14496-5
and ISO/IEC TR 14496-7 correspond to the need of providing the public with conformant standard
descriptions that are closer to the starting point of the development of codec implementations than textual
descriptions or pure software descriptions. This part of ISO/IEC 14496 contains conformant descriptions of
video tools that have been validated within the recommendation ISO/IEC TR 14496-7.
2 Copyright disclaimer for HDL software modules
Each HDL module, and all derivative modules, shall be accompanied by the following copyright disclaimer:
/*********************************************************************
This software module was originally developed by
, , ,
(date: ,)
and edited by: , ,
This HDL module is an implementation of a part of one or more MPEG-4
tools(ISO/IEC 14496).
ISO/IEC gives users of the MPEG-4 free license to this HDL module or
modifications thereof for use in hardware or software products claiming
conformance to the MPEG-4 Standard.
Those intending to use this HDL module in hardware or software products are
advised that its use may infringe existing patents.
The original developer of this HDL module and his/her company, the subsequent
editors and their companies, and ISO/IEC have no liability for use of this HDL
module or modifications thereof in an implementation.
Copyright is not released for non MPEG-4 Video conforming products.
retains full right to use the code for his/her own purpose, assign
or donate the code to a third party and to inhibit third parties from using the
code for non MPEG standard conforming products.
This copyright notice must be included in all copies or derivative works.
Copyright (c) .
Module Name: .vhd
Abstract:
Revision History:
**********************************************************************/
© ISO/IEC 2008 – All rights reserved 1
---------------------- Page: 8 ----------------------
ISO/IEC TR 14496-9:2008(E)
3 Abbreviated terms
For the purposes of this document, the following abbreviated terms apply.
AV Audio-Visual
DCT Discrete Cosine Transform
IDCT Inverse Discrete Cosine Transform
HDL Hardware Description language
ISO International Organization for Standardization
MPEG Moving Picture Experts Group
Verilog A Hardware Description Language
VHDL VHSIC high speed Hardware Description Language
SAD Sum of Absolute Differences
MAC Multiply ACcumulate
MAD Minimum Absolute Difference
SIMD Single Instruction Multiple Data
DA Distributive Arithmetic
EDA Electronic Design and Automation
IEEE Institute of Electrical and Electronic Engineers
IMEC Interuniversity Micro Electronic Center
EPFL École Polytechnique Fédérale de Lausanne
4 HDL software availability
The HDL and System C software modules described in this part of ISO/IEC 14496 are available within the zip
file containing this Technical Report. Each module contains a separate directory structure for the source code
with a readme.txt file explaining the top level and all files to be included for simulation and synthesis.
5 HDL coding format and standards
5.1 HDL standards and libraries
As the IEEE has several HDL coding standards that are commonly used in hardware reference code (i.e.
VHDL1076-1987, VHDL 1164-1993, Verilog 1364-2000, Verilog 1364-1995), the modules constituting this part
of ISO/IEC 14496 are made of the latest IEEE standard possible at the time of coding for all reference HDL
code. As the IEEE has provided libraries to assist in the use of HDL, only IEEE standard libraries are needed
to use the HDL code.
Custom libraries which are specific to the vendor's (Silicon) base library elements are used only if they are
freely available for synthesis and simulation and are provided in an accompanying module version of the
submitted HDL code using the standard libraries mentioned above.
2 © ISO/IEC 2008 – All rights reserved
---------------------- Page: 9 ----------------------
ISO/IEC TR 14496-9:2008(E)
5.2 Conditions and tools for the synthesis of HDL modules
As there are many choices commercially for HDL synthesis and HDL simulation software tools, specific
synthesis or simulation libraries that are used for reference HDL code are properly documented. The same
code that is used to synthesize towards an implementation is also used to perform HDL behavioral simulation
of the MPEG-4 tool. The code is properly documented with respect to the synthesis and simulation tool (and
version) that has been used to perform the work. HDL module codes with multiple synthesis and simulation
tools are also possible. In the event a source code modification must be made to support an additional
synthesis or simulation tool, an additional source code is provided with proper documentation.
5.3 Conformance with the reference software
HDL reference code provides sufficient test bench code and documentation on how it is conformant with
respect to the reference software. To the extent possible, bit and cycle true models are provided which can be
used directly in the reference software code for verification. In the case that the reference HDL code is derived
from other languages such as: C, C++, System C, Java, it is recommended that that this code and information
on the methodology used to generate HDL should be provided to improve verification of conformance of the
HDL code.
6 Integrated Framework supporting the “Virtual Socket” between HDL modules
described in Part 9 and the MPEG Reference Software (Implementation 1).
6.1 Introduction
The aim of this clause is to document the framework developed by Xilinx Research Labs for the integration of
HW modules with the MPEG-4 reference software. The purpose of this virtual socket framework is to create
an abstraction between the specific physical layer and specific software driver library to facilitate a reusable
hardware/software co-design environment. By acting as an intermediary between specific physical layer bus
protocols, the hardware accelerator designer can focus on the acceleration algorithm rather than lower level
interface protocols.
The framework of the Virtual Socket allows for 31 addressable hardware accelerators to be present in a single
device (see Figure 1). Each specific hardware accelerator will be assigned a bit of the 32-bit hardware
identification register and these bit locations shall be assigned to particular MPEG development teams (see
Figure 2 for an example containing two accelerators at slots 1 and 6). If an accelerator socket is not present
then its bit in the identification register will be de-asserted. Unassigned sockets will also be de-asserted
indicating no accelerator is present. In the event that hardware accelerator designers wish to put further
identification of their socket they may do so by allocating further identification registers within their socket’s
assigned register space.
© ISO/IEC 2008 – All rights reserved 3
---------------------- Page: 10 ----------------------
ISO/IEC TR 14496-9:2008(E)
Figure 1 — Block Diagram of Virtual Socket Platform.
Figure 2 — Example 32-Bit Hardware Identification Register.
6.2 Addressing
The virtual socket provides four strobes that indicate what region of the memory space, register or memory,
has been accessed as well as the type of operation, write or read. Although a 16-bit is provided to each
socket, the least significant nine bits are only necessary to address within the 512 word assigned memory
region.The Virtual Socket API uses macros that assist the software designer in transferring data to and from
memory locations.
6.3 Memory Map
Table 1 — Memory Mapping for Register File Allocation
Register Read-Only Register Write-Only
Socket
# Begin End Begin End
Master 0000 01FF 4000 41FF
1 0200 03FF 4200 43FF
2 0400 05FF 4400 45FF
3 0600 07FF 4600 47FF
4 0800 09FF 4800 49FF
5 0A00 0BFF 4A00 4BFF
6 0C00 0DFF 4C00 4DFF
7 0E00 0FFF 4E00 4FFF
4 © ISO/IEC 2008 – All rights reserved
---------------------- Page: 11 ----------------------
ISO/IEC TR 14496-9:2008(E)
8 1000 11FF 5000 51FF
9 1200 13FF 5200 53FF
10 1400 15FF 5400 55FF
11 1600 17FF 5600 57FF
12 1800 19FF 5800 59FF
13 1A00 1BFF 5A00 5BFF
14 1C00 1DFF 5C00 5DFF
15 1E00 1FFF 5E00 5FFF
16 2000 21FF 6000 61FF
17 2200 23FF 6200 63FF
18 2400 25FF 6400 65FF
19 2600 27FF 6600 67FF
20 2800 29FF 6800 69FF
21 2A00 2BFF 6A00 6BFF
22 2C00 2DFF 6C00 6DFF
23 2E00 2FFF 6E00 6FFF
24 3000 31FF 7000 71FF
25 3200 33FF 7200 73FF
26 3400 35FF 7400 75FF
27 3600 37FF 7600 77FF
28 3800 39FF 7800 79FF
29 3A00 3BFF 7A00 7BFF
30 3C00 3DFF 7C00 7DFF
31 3E00 3FFF 7E00 7FFF
Table 2 — Memory Mapping for the Block RAM Allocation
Memory Read-Only Memory Write-Only
Socket
# Begin End Begin End
Master 8000 81FF C000 C1F
...
Questions, Comments and Discussion
Ask us and Technical Secretary will try to provide an answer. You can facilitate discussion about the standard in here.