IEC 60191-6:2009

Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages

IEC 60191-6:2009 gives general rules for the preparation of outline drawings of surface-mounted semiconductor devices. It supplements IEC 60191-1 and IEC 60191-3. It covers all surface-mounted devices discrete semiconductors with lead count of greater or equal to 8, as well as integrated circuits classified as form E in Clause 3 of IEC 60191-4. This third edition of IEC 60191-6 cancels and replaces the second edition, published in 2004 and constitutes a technical revision. This edition includes the following significant changes with respect to the previous edition:
a) scope is modified to cover all surface-mounted devices discrete semiconductors with lead count of greater or equal to 8;
b) editorial modifications on several pages; and
c) technical revision to ball grid array package (BGA) especially its geometrical drawing format. (two types of BGA would unify as one type as a result of revising drawing format.

Normalisation mécanique des dispositifs à semi-conducteurs - Partie 6: Règles générales pour la préparation des dessins d'encombrement des boîtiers pour dispositifs à semi-conducteurs pour montage en surface

La CEI 60191-6:2009 donne les règles générales pour la préparation des dessins d'encombrement des dispositifs à semi-conducteurs pour montage en surface. Elle complète la CEI 60191-1 et la CEI 60191-3. Elle couvre tous les dispositifs pour montage en surface à semi-conducteurs discrets dotés d'au moins 8 sorties, ainsi que les circuits intégrés classés "de forme E" dans l'Article 3 de la CEI 60191-4. Cette troisième édition de la CEI 60191-6 annule et remplace la deuxième édition parue en 2004 dont elle constitue une révision technique. La présente édition contient les modifications majeures suivantes par rapport à l'édition précédente:
a) le domaine d'application est modifié pour couvrir tous les dispositifs pour montage en surface à semi-conducteurs discrets dotés d'au moins 8 sorties;
b) des modifications éditoriales sur plusieurs pages; et
c) une révision technique du boîtier matriciel à billes (BGA) particulièrement son format de dessin géométrique. (la révision du format de dessin permettrait d'unifier deux types de boîtier BGA pour n'avoir qu'un seul type.)

General Information

• Status: Published
• Publication Date: 25-Nov-2009
• ICS: 01 - GENERALITIES. TERMINOLOGY. STANDARDIZATION. DOCUMENTATION
• ICS: 31.080.01 - Semiconductor devices in general
• Technical Committee: SC 47D - Semiconductor devices packaging
• Drafting Committee: WG 2 - TC 47/SC 47D/WG 2
• Current Stage: PPUB - Publication issued
• Completion Date: 26-Nov-2009

Relations

• Revises: IEC 60191-6:2004 - Mechanical standardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages
• Effective Date: 05-Sep-2023

Standards Content (Sample)

IEC 60191-6 ®
Edition 3.0 2009-11
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Mechanical standardization of semiconductor devices –
Part 6: General rules for the preparation of outline drawings of surface mounted
semiconductor device packages
Normalisation mécanique des dispositifs à semi-conducteurs –
Partie 6: Règles générales pour la préparation des dessins d'encombrement des
boîtiers pour dispositifs à semi-conducteurs pour montage en surface

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IEC 60191-6 ®
Edition 3.0 2009-11
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Mechanical standardization of semiconductor devices –
Part 6: General rules for the preparation of outline drawings of surface mounted
semiconductor device packages
Normalisation mécanique des dispositifs à semi-conducteurs –
Partie 6: Règles générales pour la préparation des dessins d'encombrement des
boîtiers pour dispositifs à semi-conducteurs pour montage en surface

INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
W
CODE PRIX
ICS 31.080.01 ISBN 978-2-88910-063-7
– 2 – 60191-6 © IEC:2009
CONTENTS
FOREWORD.4
1 Scope.6
2 Normative references .6
3 Terms and definitions .6
4 Design rules .7
5 Dimensions to be specified.8
6 Notes .8
Annex A (informative) Illustration of the rules.12
Annex B (informative) Optional table format.36
Bibliography.38

Figure A.1 – Illustrations of terminal projection zone.13
Figure A.2 – Isometric view of an example of gauge .13
Figure A.3a – Top view .14
Figure A.3b – Side view .14
Figure A.3c – Lead section .14
Figure A.3d – Lead side view.14
Figure A.4 – Pattern of terminal position areas .14
Figure A.5a – Top view .17
Figure A.5b – Side view .17
Figure A.5c – Lead section .17
Figure A.5d – Lead side view.17
Figure A.6 – Pattern of terminal position areas .17
Figure A.7a – Top view .20
Figure A.7b – Side view .20
Figure A.7c – Lead section .20
Figure A.7d – Lead side view.20
Figure A.8 – Pattern of terminal position areas .20
Figure A.9a – Top view .23
Figure A.9b – Side view .23
Figure A.9c – Side view .23
Figure A.9d – Lead shape.23
Figure A.9e – Lead side view.23
Figure A.9f – Lead section .23
Figure A.10 – Pattern of terminal position areas .23
Figure A.11a – Top view .26
Figure A.11b – Side view .26
Figure A.11c – Side view .26
Figure A.11d – Lead section .27
Figure A.11e – Lead shape .27
Figure A.11f – Lead side view.27

60191-6 © IEC:2009 – 3 –
Figure A.12 – Pattern of terminal position areas .27
Figure A.13a – Top View.30
Figure A.13b – Side View.30
Figure A.13c – Bottom view .30
Figure A.14 – Pattern of terminal position areas .30
Figure A.15a – Top view .33
Figure A.15b – Side view .33
Figure A.15c – Bottom view .33
Figure A.16 – Pattern of terminal position areas .33

Table 1 – Dimensions to be specified for Group 1 .9
Table 2 – Dimensions to be specified for Group 2 .10

– 4 – 60191-6 © IEC:2009
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
MECHANICAL STANDARDIZATION
OF SEMICONDUCTOR DEVICES –
Part 6: General rules for the preparation of outline drawings
of surface mounted semiconductor device packages

FOREWORD
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