Semiconductor devices - Non-destructive recognition criteria of defects in silicon carbide homoepitaxial wafer for power devices - Part 2: Test method for defects using optical inspection

IEC 63068-2:2019(E) provides definitions and guidance in use of optical inspection for detecting as-grown defects in commercially available 4H-SiC (Silicon Carbide) epitaxial wafers. Additionally, this document exemplifies optical images to enable the detection and categorization of the defects for SiC homoepitaxial wafers. This document deals with a non-destructive test method for the defects so that destructive methods such as preferential etching are out of scope in this document.

General Information

Status
Published
Publication Date
29-Jan-2019
Technical Committee
Current Stage
PPUB - Publication issued
Completion Date
30-Jan-2019
Ref Project

Buy Standard

Standard
IEC 63068-2:2019 - Semiconductor devices - Non-destructive recognition criteria of defects in silicon carbide homoepitaxial wafer for power devices - Part 2: Test method for defects using optical inspection
English language
25 pages
sale 15% off
Preview
sale 15% off
Preview

Standards Content (sample)

IEC 63068-2
Edition 1.0 2019-01
INTERNATIONAL
STANDARD
Semiconductor devices – Non-destructive recognition criteria of defects in
silicon carbide homoepitaxial wafer for power devices –
Part 2: Test method for defects using optical inspection
IEC 63068-2:2019-01(en)
---------------------- Page: 1 ----------------------
THIS PUBLICATION IS COPYRIGHT PROTECTED
Copyright © 2019 IEC, Geneva, Switzerland

All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form

or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from

either IEC or IEC's member National Committee in the country of the requester. If you have any questions about IEC

copyright or have an enquiry about obtaining additional rights to this publication, please contact the address below or

your local IEC member National Committee for further information.
IEC Central Office Tel.: +41 22 919 02 11
3, rue de Varembé info@iec.ch
CH-1211 Geneva 20 www.iec.ch
Switzerland
About the IEC

The International Electrotechnical Commission (IEC) is the leading global organization that prepares and publishes

International Standards for all electrical, electronic and related technologies.
About IEC publications

The technical content of IEC publications is kept under constant review by the IEC. Please make sure that you have the

latest edition, a corrigendum or an amendment might have been published.

IEC publications search - webstore.iec.ch/advsearchform Electropedia - www.electropedia.org

The advanced search enables to find IEC publications by a The world's leading online dictionary on electrotechnology,

variety of criteria (reference number, text, technical containing more than 22 000 terminological entries in English

committee,…). It also gives information on projects, replaced and French, with equivalent terms in 16 additional languages.

and withdrawn publications. Also known as the International Electrotechnical Vocabulary

(IEV) online.
IEC Just Published - webstore.iec.ch/justpublished

Stay up to date on all new IEC publications. Just Published IEC Glossary - std.iec.ch/glossary

details all new publications released. Available online and 67 000 electrotechnical terminology entries in English and

once a month by email. French extracted from the Terms and Definitions clause of

IEC publications issued since 2002. Some entries have been

IEC Customer Service Centre - webstore.iec.ch/csc collected from earlier publications of IEC TC 37, 77, 86 and

If you wish to give us your feedback on this publication or CISPR.
need further assistance, please contact the Customer Service
Centre: sales@iec.ch.
---------------------- Page: 2 ----------------------
IEC 63068-2
Edition 1.0 2019-01
INTERNATIONAL
STANDARD
Semiconductor devices – Non-destructive recognition criteria of defects in
silicon carbide homoepitaxial wafer for power devices –
Part 2: Test method for defects using optical inspection
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 31.080.99 ISBN 978-2-8322-6480-5

Warning! Make sure that you obtained this publication from an authorized distributor.

® Registered trademark of the International Electrotechnical Commission
---------------------- Page: 3 ----------------------
– 2 – IEC 63068-2:2019 © IEC 2019
CONTENTS

FOREWORD ........................................................................................................................... 4

INTRODUCTION ..................................................................................................................... 6

1 Scope .............................................................................................................................. 7

2 Normative references ...................................................................................................... 7

3 Terms and definitions ...................................................................................................... 7

4 Optical inspection method ............................................................................................. 11

4.1 General ................................................................................................................. 11

4.2 Principle ............................................................................................................... 12

4.3 Requirements ....................................................................................................... 12

4.3.1 Illumination .................................................................................................... 12

4.3.2 Wafer positioning and focusing ...................................................................... 13

4.3.3 Image capturing ............................................................................................. 13

4.3.4 Image processing .......................................................................................... 13

4.3.5 Image analysis .............................................................................................. 13

4.3.6 Image evaluation ........................................................................................... 13

4.3.7 Documentation .............................................................................................. 13

4.4 Parameter settings ................................................................................................ 14

4.4.1 General ......................................................................................................... 14

4.4.2 Parameter setting process ............................................................................. 14

4.5 Procedure ............................................................................................................. 14

4.6 Evaluation ............................................................................................................. 14

4.6.1 General ......................................................................................................... 14

4.6.2 Mean width of planar and volume defects ...................................................... 14

4.6.3 Evaluation process ........................................................................................ 15

4.7 Precision ............................................................................................................... 15

4.8 Test report ............................................................................................................ 15

Annex A (informative) Optical inspection images of defects ................................................ 16

A.1 General ................................................................................................................. 16

A.2 Micropipe .............................................................................................................. 16

A.3 TSD ...................................................................................................................... 17

A.4 TED ...................................................................................................................... 17

A.5 BPD ...................................................................................................................... 18

A.6 Scratch trace ........................................................................................................ 18

A.7 Stacking fault ........................................................................................................ 19

A.8 Propagated stacking fault ...................................................................................... 19

A.9 Stacking fault complex .......................................................................................... 20

A.10 Polytype inclusion ................................................................................................. 21

A.11 Particle inclusion ................................................................................................... 23

A.12 Bunched-step segment ......................................................................................... 23

Bibliography .......................................................................................................................... 25

Figure A.1 – Micropipe .......................................................................................................... 16

Figure A.2 – TSD .................................................................................................................. 17

Figure A.3 – TED .................................................................................................................. 18

Figure A.4 – Scratch trace .................................................................................................... 18

Figure A.5 – Stacking fault .................................................................................................... 19

---------------------- Page: 4 ----------------------
IEC 63068-2:2019 © IEC 2019 – 3 –

Figure A.6 – Propagated stacking fault ................................................................................. 20

Figure A.7 – Stacking fault complex ...................................................................................... 21

Figure A.8 – Polytype inclusion ............................................................................................. 22

Figure A.9 – Particle inclusion .............................................................................................. 23

Figure A.10 – Bunched-step segment ................................................................................... 24

---------------------- Page: 5 ----------------------
– 4 – IEC 63068-2:2019 © IEC 2019
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES –
NON-DESTRUCTIVE RECOGNITION CRITERIA OF DEFECTS IN SILICON
CARBIDE HOMOEPITAXIAL WAFER FOR POWER DEVICES –
Part 2: Test method for defects using optical inspection
FOREWORD

1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising

all national electrotechnical committees (IEC National Committees). The object of IEC is to promote

international co-operation on all questions concerning standardization in the electrical and electronic fields. To

this end and in addition to other activities, IEC publishes International Standards, Technical Specifications,

Technical Reports, Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC

Publication(s)”). Their preparation is entrusted to technical committees; any IEC National Committee interested

in the subject dealt with may participate in this preparatory work. International, governmental and non-

governmental organizations liaising with the IEC also participate in this preparation. IEC collaborates closely

with the International Organization for Standardization (ISO) in accordance with conditions determined by

agreement between the two organizations.

2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international

consensus of opinion on the relevant subjects since each technical committee has representation from all

interested IEC National Committees.

3) IEC Publications have the form of recommendations for international use and are accepted by IEC National

Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC

Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any

misinterpretation by any end user.

4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications

transparently to the maximum extent possible in their national and regional publications. Any divergence

between any IEC Publication and the corresponding national or regional publication shall be clearly indicated in

the latter.

5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity

assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any

services carried out by independent certification bodies.

6) All users should ensure that they have the latest edition of this publication.

7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and

members of its technical committees and IEC National Committees for any personal injury, property damage or

other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and

expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC

Publications.

8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is

indispensable for the correct application of this publication.

9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of

patent rights. IEC shall not be held responsible for identifying any or all such patent rights.

International Standard IEC 63068-2 has been prepared by IEC technical committee 47:

Semiconductor devices.
The text of this International Standard is based on the following documents:
CDV Report on voting
47/2475/CDV 47/2522A/RVC

Full information on the voting for the approval of this International Standard can be found in

the report on voting indicated in the above table.

This document has been drafted in accordance with the ISO/IEC Directives, Part 2.

---------------------- Page: 6 ----------------------
IEC 63068-2:2019 © IEC 2019 – 5 –

A list of all parts in the IEC 63068 series, published under the general title Semiconductor

devices – Non-destructive recognition criteria of defects in silicon carbide homoepitaxial wafer

for power devices, can be found on the IEC website.

The committee has decided that the contents of this document will remain unchanged until the

stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to

the specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
A bilingual version of this publication may be issued at a later date.
---------------------- Page: 7 ----------------------
– 6 – IEC 63068-2:2019 © IEC 2019
INTRODUCTION

Silicon carbide (SiC) is widely used as a semiconductor material for next-generation power

semiconductor devices. SiC, as compared with silicon (Si), has superior physical properties

such as a higher breakdown electric field, higher thermal conductivity, lower thermal

generation rate, higher saturated electron drift velocity, and lower intrinsic carrier

concentration. These attributes realize SiC-based power semiconductor devices with faster

switching speeds, lower losses, higher blocking voltages, and higher temperature operation

relative to standard Si-based power semiconductor devices.

SiC-based power semiconductor devices are not fully realized due to some issues including

high costs, low yield, and low long-term reliability. In particular, one of the serious issues lies

in the defects existing in SiC homoepitaxial wafers. Although efforts of decreasing defects in

SiC homoepitaxial wafers are actively implemented, there are a number of defects in

commercially available SiC homoepitaxial wafers. Therefore, it is indispensable to establish

an international standard regarding the quality assessment of SiC homoepitaxial wafers.

The IEC 63068 series of standards is planned to comprise Part 1, Part 2, and Part 3, as

detailed below. This document provides definitions and guidance in use of optical inspection

for detecting defects in commercially available silicon carbide (SiC) homoepitaxial wafers.

Part 1: Classification of defects
Part 2: Test method for defects using optical inspection
Part 3: Test method for defects using photoluminescence
---------------------- Page: 8 ----------------------
IEC 63068-2:2019 © IEC 2019 – 7 –
SEMICONDUCTOR DEVICES –
NON-DESTRUCTIVE RECOGNITION CRITERIA OF DEFECTS IN SILICON
CARBIDE HOMOEPITAXIAL WAFER FOR POWER DEVICES –
Part 2: Test method for defects using optical inspection
1 Scope

This part of IEC 63068 provides definitions and guidance in use of optical inspection for

detecting as-grown defects in commercially available 4H-SiC (Silicon Carbide) epitaxial

wafers. Additionally, this document exemplifies optical images to enable the detection and

categorization of the defects for SiC homoepitaxial wafers.

This document deals with a non-destructive test method for the defects so that destructive

methods such as preferential etching are out of scope in this document.
2 Normative references

The following documents are referred to in the text in such a way that some or all of their

content constitutes requirements of this document. For dated references, only the edition

cited applies. For undated references, the latest edition of the referenced document (including

any amendments) applies.
There are no normative references in this document.
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.

ISO and IEC maintain terminological databases for use in standardization at the following

addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
3.1
optical inspection

morphological inspection of wafers using optical imaging where an optical image sensor

scans the wafer surface under a non-contact test method for obtaining features of defects, e.g.

size and shape of defects
3.2
optical imaging

technique for capturing, processing and analysing images of defects using light source for

illumination, optical components, optical image sensor and computer systems
3.3
illumination

application of light to defects and their surroundings so that they can be observed

---------------------- Page: 9 ----------------------
– 8 – IEC 63068-2:2019 © IEC 2019
3.4
reflective illumination

illumination for observing the reflected light from defects by irradiating light onto the wafer

surface
3.5
directional lighting
lighting in which the light to the wafer is incident from a particular direction
3.6
diffused lighting
lighting in which the irradiation direction of the light to the wafer is random
3.7
bright-field observation

method of image capturing in which an optical image sensor detects both lights reflected and

scattered from defects
3.8
dark-field observation

method of image capturing in which an optical image sensor detects only light scattered from

defects
3.9
differential interference contrast observation

method of image capturing in which contrast derives from the difference in optical path

between adjacent points on the wafer surface by irradiating two orthogonal polarized lights

which are spatially displaced
3.10
polarized light observation

method of image capturing in which an optical image sensor detects a polarized light using

polarizing plates in a path from defects by irradiating polarized light
3.11
optical image sensor
device to transform an optical image into digital data
3.12
optical component

lenses, mirrors, filters and other components, which comprise an optical system and are used

to capture optical images
3.13
image capturing

process of creating a two-dimensional original digital image of defects on the wafer surface

3.14
original digital image

digitized image taken by an optical image sensor, without performing any image processing

Note 1 to entry: Original digital images are divided into pixels by a grid, and one grey level is assigned to each

pixel.
3.15
charge-coupled device
CCD

light-sensitive integrated circuit that stores and displays the data for optical images

---------------------- Page: 10 ----------------------
IEC 63068-2:2019 © IEC 2019 – 9 –

Note 1 to entry: CCD chips are subdivided into fine elements, each of which corresponds to a pixel of original

digital images.
3.16
pixel

smallest formative element of original digital images, to which a grey level is assigned

3.17
resolution
number of pixels per unit length (or area) of original digital images

Note 1 to entry: If resolutions in the X- and Y- directions are different, both values have to be recorded.

3.18
grey level
shade of grey assigned to each pixel

Note 1 to entry: Shade of grey is usually a positive integer taken from grey scale.

3.19
grey scale
range of grey shades from black to white

EXAMPLE: 8-bit grey scale has two-to-the-eighth-power (= 256) grey levels. Grey level 0 (the 1 level)

corresponds to black, grey level 255 (the 256 level) to white.
3.20
image processing

software manipulation of original digital images to prepare for subsequent image analysis

Note 1 to entry: For example, image processing can be used to eliminate mistakes generated during image

capturing or to reduce image information to the essential.
3.21
binary image
image in which either 0 (black) or 1 (white) is assigned to each pixel
3.22
brightness
average grey level of a specified part of optical images
3.23
contrast
difference between the grey levels of two specified parts of optical images
3.24
shading correction

software method for correcting non-uniformity of the illumination over the wafer surface

3.25
thresholding

process of creating a binary image out of a grey scale image by setting exactly those pixels

whose value is greater than a given threshold to white and setting the other pixels to black.

Note 1 to entry: To make a binary image, grey level 0 (black) or 1 (white) is assigned to each pixel in the grey-

scale image, depending on whether the pixel indicates a grey level greater than or less than or equal to a given

threshold.
3.25.1
edge detection

method of isolating and locating edges of defects and surface features in a given digital image

---------------------- Page: 11 ----------------------
– 10 – IEC 63068-2:2019 © IEC 2019
3.26
image analysis
extraction of imaging information from processed digital images by software
3.27
image evaluation

process of relating a series of values resulting from image analysis of one or more

characteristic images via a classification scheme of defects
3.28
reference wafer

specified wafer used for parameter settings, which has already been evaluated for checking

the reproducibility and repeatability of optical inspection process for defects
3.29
test wafer
SiC homoepitaxial wafers provided to evaluate defects
3.30
crystal direction

direction, usually denoted as [uvw], representing a vector direction in multiples of the basis

vectors describing the a, b and c crystal axes

Note 1 to entry: In 4H-SiC showing a hexagonal symmetry, four-digit indices [uvtw] are frequently used for crystal

directions.
[SOURCE: ISO 24173: 2009, 3.3, modified – Note 1 to entry has been added.]
3.31
defect
crystalline imperfection
3.32
micropipe
hollow tube extending approximately normal to the basal plane
3.33
threading screw dislocation
TSD

screw dislocation penetrating through the crystal approximately normal to the basal plane

3.34
threading edge dislocation
TED

edge dislocation penetrating through the crystal approximately normal to the basal plane

3.35
basal plane dislocation
BPD
dislocation lying on the basal plane
3.36
scratch trace
dense low of dislocations caused by mechanical damages on the substrate surface
---------------------- Page: 12 ----------------------
IEC 63068-2:2019 © IEC 2019 – 11 –
3.37
stacking fault

planar crystallographic defect in monocrystalline material, characterized by an error in the

stacking sequence of crystallographic planes
3.38
propagated stacking fault
stacking fault propagating from substrate toward the homoepitaxial layer surface
3.39
stacking fault complex

stacking fault complex consisting of a basal plane stacking fault and a prismatic fault

3.40
polytype inclusion

volume crystal defect showing different polytypes from that of the homoepitaxial layer

3.41
particle inclusion
macroscopic size particle existing in the homoepitaxial layer
3.42
bunched-step segment
surface morphological roughness consisting of bunched-steps
3.43
surface particle
particle deposited on the epitaxial layer surface after epitaxial growth
4 Optical inspection method
4.1 General

Defects with surface morphological features shall be detected by optical inspection method.

The following descriptions concern such defects in n/n+-type 4H-SiC homoepitaxial wafers

with an off-cut angle of 4° along the direction of [11 2 0]:

– individual defects exhibiting hexagonal-shaped or round-shaped large holes on the wafer

surface, e.g. micropipe (Figure A.1);

– individual minute defects giving rise to a pit less than 50 µm in diameter on the wafer

surface, e.g. TSD (Figure A.2), TED (Figure A.3);

– individual linear defects extending in various directions, e.g. scratch trace (Figure A.4);

– individual planar defects providing needle-shaped features on the wafer surface, which

extend along the off-cut direction, e.g. stacking fault complex (Figure A.7);

– individual planar defects providing faintly-outlined features on the wafer surface, which

extend diagonally to the off-cut direction, e.g. stacking fault (Figure A.5), propagated

stacking fault (Figure A.6);

– individual volume defects giving rise to triangle-shaped features on the wafer surface,

which extend along the off-cut direction, e.g. polytype inclusion (Figure A.8);

– individual volume defects, e.g. particle inclusions (Figure A.9), surface particle;

– individual surface defects exhibiting obtuse triangle-shaped or trapezoid-shaped features

on the wafer surface, e.g. bunched-step segment (Figure A.10).

Defects without surface morphological features should be evaluated by other test methods

such as photoluminescence and X-ray topography. Those defects include BPDs, TSDs
---------------------- Page: 13 ----------------------
– 12 – IEC 63068-2:2019 © IEC 2019

without surface morphological features, TEDs without surface morphological features,

stacking faults without surface morphological features, and propagated stacking faults without

surface morphological features.
4.2 Principle

A grey scale image (or colour image) is produced from the original digital image of defects on

the wafer surface. This image is converted into a binary image (thresholding). The size and

shape of defects are measured, and the distribution and number of defects within a specified

area of wafer are calculated.

First, an optical image of defects has to be captured and transformed into a digital format. An

optical image is captured via an optical image sensor such as a charge-coupled device. Then,

the obtained digital image is processed by manipulating the grey levels of the image. Through

a specified scheme of image analysis, the image information is reduced to a set of values

which are specific to the application.

NOTE The size of planar and volume defects extending along the off-cut direction depends on the thickness of

homoepitaxial layer. Details of such defects and the method of estimating the size of their optical images are

described in 4.6.2 and Annex A, respectively.
4.3 Requirements
4.3.1 Illumination
4.3.1.1 Types of observations

Different wafer surface conditions and defect types will require an optimum setup of optics

and illumination to acquire distinct surface features in an image that are to be analysed.

Therefore, a combination of optics and illumination for a specific application has to be

prepared. Generally, the following types of lightings and observations are used.
a) Types of lightings are:
1) directional lighting;
2) diffused lighting;
3) mixture of directional and diffused lightings.
b) Types of observations are:
1) bright-field observation;
2) dark-field observation;
3) differential interference contrast observation;
4) polarized light observation.

All the types of observations can be done under reflective illumination. Influences from wafer

backsides shall be eliminated in any observations.
4.3.1.2 Uniformity and constancy

A combination of light source and optical components is used to achieve sufficient uniformity

of the illuminance on the wafer surface. The illuminance at each point to be inspected on the

wafer surface is adjusted in an appropriate range so that defects are clearly detected.

Illumination uniformity can be achieved using hardware and/or software.

The illuminance and spectral – power distribution are kept constant during the whole

measurement period.
---------------------- Page: 14 ----------------------
IEC 63068-2:2019 © IEC 2019 – 13 –
4.3.2 Wafer positioning and focusing

Wafers shall be positioned in the plane of two mutually perpendicular axes X and Y. The third

axis (Z) is the optical axis of image capturing system. The Z-axis is perpendicular to the X-Y

plane and its point of intersection with the wafer surface shall be the point of focus. The

distance between the front-end portion of image-capturing optics and the wafer surface shall

be constant, independent of the thickness of the wafers, so that focussing and magnification

are not mutually adversely affected.
4.3.3 Image cap
...

Questions, Comments and Discussion

Ask us and Technical Secretary will try to provide an answer. You can facilitate discussion about the standard in here.