IEC 62271-101:2012

High-voltage switchgear and controlgear - Part 101: Synthetic testing

IEC 62271-101:2012 mainly applies to a.c. circuit-breakers within the scope of IEC 62271-100. It provides the general rules for testing a.c. circuit-breakers, for making and breaking capacities over the range of test duties described in 6.102 to 6.111 of IEC 62271-100:2008, by synthetic methods. This second edition cancels and replaces the first edition published in 2007 and its Amendment 1 published in 2011. It constitutes a technical revision. This edition includes the following significant technical changes with respect to the first edition:
- addition of the new rated voltages of 1 100 kV and 1 200 kV;
- revision of Annex F regarding circuit-breakers with opening resistors;
- alignment with the second edition of IEC 62271-100:2008 and its Amendment 1 (2012).
This publication is to be read in conjunction with IEC 62271-100:2008.

Appareillage à haute tension - Partie 101: Essais synthétiques

La CEI 62271-101:2012 s'applique principalement aux disjoncteurs à courant alternatif définis dans le domaine d'application de la CEI 62271-100. Elle donne les règles générales d'essais de ces disjoncteurs, pour les pouvoirs de fermeture et de coupure dans la gamme des séquences d'essais décrites de 6.102 à 6.111 de la CEI 62271-100:2008, à l'aide de méthodes d'essais synthétiques. Cette deuxième édition annule et remplace la première édition parue en 2007 et l'Amendement 1 paru en 2011. Elle constitue une révision technique. Les principales modifications par rapport à la précédente édition sont les suivantes:
- ajout des nouvelles tensions assignées 1 100 kV et 1 200 kV;
- révision de l'Annexe F qui traite des disjoncteurs équipés de résistances d'ouverture;
- alignement avec la deuxième édition de la CEI 62271-100:2008 et Amendement 1 (2012).
Cette publication doit être lue conjointement avec la CEI 62271-100:2008.

General Information

• Status: Published
• Publication Date: 11-Oct-2012
• ICS: 01 - GENERALITIES. TERMINOLOGY. STANDARDIZATION. DOCUMENTATION
• ICS: 29.130.10 - High voltage switchgear and controlgear
• Technical Committee: SC 17A - Switching devices
• Current Stage: DELPUB - Deleted Publication
• Completion Date: 27-Jul-2021

Standards Content (sample)

IEC 62271-101
Edition 2.0 2012-10
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
High-voltage switchgear and controlgear –
Part 101: Synthetic testing
Appareillage à haute tension –
Partie 101: Essais synthétiques
IEC 62271-101:2012
---------------------- Page: 1 ----------------------
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---------------------- Page: 2 ----------------------
IEC 62271-101
Edition 2.0 2012-10
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
High-voltage switchgear and controlgear –
Part 101: Synthetic testing
Appareillage à haute tension –
Partie 101: Essais synthétiques
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
CODE PRIX XH
ICS 29.130.10 ISBN 978-2-83220-421-4

Warning! Make sure that you obtained this publication from an authorized distributor.

Attention! Veuillez vous assurer que vous avez obtenu cette publication via un distributeur agréé.

® Registered trademark of the International Electrotechnical Commission
Marque déposée de la Commission Electrotechnique Internationale
---------------------- Page: 3 ----------------------
– 2 – 62271-101 © IEC:2012
CONTENTS

FOREWORD ........................................................................................................................... 7

1 Scope ............................................................................................................................... 9

2 Normative references ....................................................................................................... 9

3 Terms and definitions ....................................................................................................... 9

4 Synthetic testing techniques and methods for short-circuit breaking tests ....................... 11

4.1 Basic principles and general requirements for synthetic breaking test

methods ................................................................................................................ 11

4.1.1 General ..................................................................................................... 11

4.1.2 High-current interval .................................................................................. 12

4.1.3 Interaction interval ..................................................................................... 12

4.1.4 High-voltage interval .................................................................................. 13

4.2 Synthetic test circuits and related specific requirements for breaking tests ............ 14

4.2.1 Current injection methods .......................................................................... 14

4.2.2 Voltage injection method ........................................................................... 15

4.2.3 Duplicate circuit method (transformer or Skeats circuit) ............................. 15

4.2.4 Other synthetic test methods ..................................................................... 16

4.3 Three-phase synthetic test methods ...................................................................... 16

5 Synthetic testing techniques and methods for short-circuit making tests ......................... 19

5.1 Basic principles and general requirements for synthetic making test methods ....... 19

5.1.1 General ..................................................................................................... 19

5.1.2 High-voltage interval .................................................................................. 19

5.1.3 Pre-arcing interval ..................................................................................... 19

5.1.4 Latching interval and fully closed position .................................................. 20

5.2 Synthetic test circuit and related specific requirements for making tests ................ 20

5.2.1 General ..................................................................................................... 20

5.2.2 Test circuit ................................................................................................ 20

5.2.3 Specific requirements ................................................................................ 20

6 Specific requirements for synthetic tests for making and breaking performance

related to the requirements of 6.102 through 6.111 of IEC 62271-100:2008 ................... 21

Annex A (informative) Current distortion .............................................................................. 42

Annex B (informative) Current injection methods.................................................................. 58

Annex C (informative) Voltage injection methods ................................................................. 62

Annex D (informative) Skeats or duplicate transformer circuit .............................................. 65

Annex E (normative) Information to be given and results to be recorded for synthetic

tests ..................................................................................................................................... 68

Annex F (normative) Synthetic test methods for circuit-breakers with opening resistors ....... 69

Annex G (informative) Synthetic methods for capacitive-current switching ........................... 76

Annex H (informative) Re-ignition methods to prolong arcing .............................................. 88

Annex I (normative) Reduction in di/dt and TRV for test duty T100a .................................... 91

Annex J (informative) Three-phase synthetic test circuits ................................................... 100

Annex K (normative) Test procedure using a three-phase current circuit and one

voltage circuit ..................................................................................................................... 107

Annex L (normative) Splitting of test duties in test series taking into account the

associated TRV for each pole-to-clear ................................................................................ 127

Annex M (normative) Tolerances on test quantities for type tests ....................................... 147

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62271-101 © IEC:2012 – 3 –

Annex N (informative) Typical test circuits for metal-enclosed and dead tank circuit-

breakers ............................................................................................................................. 150

Annex O (informative) Combination of current injection and voltage injection methods ....... 160

Bibliography ........................................................................................................................ 163

Figure 1 – Interrupting process – Basic time intervals ........................................................... 33

Figure 2 – Examples of evaluation of recovery voltage .......................................................... 34

Figure 3 – Equivalent surge impedance of the voltage circuit for the current injection

method ................................................................................................................................. 35

Figure 4 – Making process – Basic time intervals .................................................................. 36

Figure 5 – Typical synthetic making circuit for single-phase tests.......................................... 37

Figure 6 – Typical synthetic making circuit for out-of-phase .................................................. 38

Figure 7 – Typical synthetic make circuit for three-phase tests (k = 1,5) ............................ 39

Figure 8 – Comparison of arcing time settings during three-phase direct tests (left)

and three-phase synthetic (right) for T100s with k = 1,5 .................................................... 40

Figure 9 – Comparison of arcing time settings during three-phase direct tests (left)

and three-phase synthetic (right) for T100a with k = 1,5 .................................................... 41

Figure A.1 – Direct circuit, simplified diagram ....................................................................... 49

Figure A.2 – Prospective short-circuit current ....................................................................... 49

Figure A.3 – Distortion current .............................................................................................. 49

Figure A.4 – Distortion current .............................................................................................. 50

Figure A.5 – Simplified circuit diagram .................................................................................. 51

Figure A.6 – Current and arc voltage characteristics for symmetrical current ........................ 52

Figure A.7 – Current and arc voltage characteristics for asymmetrical current ...................... 53

Figure A.8 – Reduction of amplitude and duration of final current loop of arcing ................... 54

Figure A.9 – Reduction of amplitude and duration of final current loop of arcing ................... 55

Figure A.10 – Reduction of amplitude and duration of final current loop of arcing ................. 56

Figure A.11 – Reduction of amplitude and duration of final current loop of arcing ................. 57

Figure B.1 – Typical current injection circuit with voltage circuit in parallel with the test

circuit-breaker ....................................................................................................................... 59

Figure B.2 – Injection timing for current injection scheme with circuit B.1 .............................. 60

Figure B.3 – Examples of the determination of the interval of significant change of arc

voltage from the oscillograms ............................................................................................... 61

Figure C.1 – Typical voltage injection circuit diagram with voltage circuit in parallel

with the auxiliary circuit-breaker (simplified diagram) ............................................................ 63

Figure C.2 – TRV waveshapes in a voltage injection circuit with the voltage circuit in

parallel with the auxiliary circuit-breaker ............................................................................... 64

Figure D.1 – Transformer or Skeats circuit ............................................................................ 66

Figure D.2 – Triggered transformer or Skeats circuit ............................................................. 67

Figure F.1 – Test circuit to verify thermal re-ignition behaviour of the main interrupter .......... 73

Figure F.2 – Test circuit to verify dielectric re-ignition behaviour of the main interrupter ....... 73

Figure F.3 – Test circuit on the resistor interrupter ................................................................ 74

Figure F.4 – Example of test circuit for capacitive current switching tests on the main

interrupter ............................................................................................................................. 75

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– 4 – 62271-101 © IEC:2012

Figure F.5 – Example of test circuit for capacitive current switching tests on the

resistor interrupter ................................................................................................................ 75

Figure G.1 – Capacitive current circuits (parallel mode) ........................................................ 79

Figure G.2 – Current injection circuit ..................................................................................... 80

Figure G.3 – LC oscillating circuit ......................................................................................... 81

Figure G.4 – Inductive current circuit in parallel with LC oscillating circuit ............................. 82

Figure G.5 – Current injection circuit, normal recovery voltage applied to both

terminals of the circuit-breaker .............................................................................................. 83

Figure G.6 – Synthetic test circuit (series circuit), normal recovery voltage applied to

both sides of the test circuit breaker ..................................................................................... 84

Figure G.7 – Current injection circuit, recovery voltage applied to both sides of the

circuit-breaker ....................................................................................................................... 85

Figure G.8 – Making test circuit ............................................................................................ 86

Figure G.9 – Inrush making current test circuit ...................................................................... 87

Figure H.1 – Typical re-ignition circuit diagram for prolonging arc-duration ........................... 89

Figure H.2 – Combined Skeats and current injection circuits ................................................. 89

Figure H.3 – Typical waveforms obtained during an asymmetrical test using the circuit

in Figure H.2 ......................................................................................................................... 90

Figure J.1 – Three-phase synthetic combined circuit ........................................................... 102

Figure J.2 – Waveshapes of currents, phase-to-ground and phase-to phase voltages

during a three-phase synthetic test (T100s; k = 1,5 ) performed according to the

three-phase synthetic combined circuit ............................................................................... 103

Figure J.3 – Three-phase synthetic circuit with injection in all phases for k = 1,5............. 104

Figure J.4 – Waveshapes of currents and phase-to-ground voltages during a three-

phase synthetic test (T100s; k =1,5) performed according to the three-phase

synthetic circuit with injection in all phases ......................................................................... 104

Figure J.5 – Three-phase synthetic circuit for terminal fault tests with k = 1,3

(current injection method) ................................................................................................... 105

Figure J.6 – Waveshapes of currents, phase-to-ground and phase-to-phase voltages
during a three-phase synthetic test (T100s; k =1,3 ) performed according to the

three-phase synthetic circuit shown in Figure J.5 ................................................................ 105

Figure J.7 – TRV voltages waveshapes of the test circuit described in Figure J.5 ............... 106

Figure K.1 – Example of a three-phase current circuit with single-phase synthetic

injection .............................................................................................................................. 118

Figure K.2 – Representation of the testing conditions of Table K.1 ..................................... 119

Figure K.3 – Representation of the testing conditions of Table K.2 ..................................... 120

Figure K.4 – Representation of the testing conditions of Table K.3 ..................................... 121

Figure K.5 – Representation of the testing conditions of Table K.4 ..................................... 122

Figure K.6 – Representation of the testing conditions of Table K.5 ..................................... 123

Figure K.7 – Representation of the testing conditions of Table K.6 ..................................... 124

Figure K.8 – Representation of the testing conditions of Table K.7 ..................................... 125

Figure K.9 – Representation of the testing conditions of Table K.8 ..................................... 126

Figure L.1 – Graphical representation of the test shown in Table L.6 .................................. 137

Figure L.2 – Graphical representation of the test shown in Table L.7 .................................. 138

Figure N.1 – Test circuit for unit testing (circuit-breaker with interaction due to gas

circulation) .......................................................................................................................... 151

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62271-101 © IEC:2012 – 5 –

Figure N.2 – Half-pole testing of a circuit-breaker in test circuit given by Figure N.1 –

Example of the required TRVs to be applied between the terminals of the unit(s) under

test and between the live parts and the insulated enclosure ................................................ 152

Figure N.3 – Synthetic test circuit for unit testing (if unit testing is allowed as per

6.102.4.2 of IEC 62271-100:2008) ...................................................................................... 153

Figure N.4 – Half-pole testing of a circuit-breaker in the test circuit of Figure N.3 –

Example of the required TRVs to be applied between the terminals of the unit(s) under

test and between the live parts and the insulated enclosure ................................................ 154

Figure N.5 – Capacitive current injection circuit with enclosure of the circuit-breaker

energized ............................................................................................................................ 155

Figure N.6 – Capacitive synthetic circuit using two power-frequency sources and with

the enclosure of the circuit-breaker energized ..................................................................... 156

Figure N.7 – Capacitive synthetic current injection circuit – Example of unit testing on

half a pole of a circuit-breaker with two units per pole – Enclosure energized with d.c.

voltage source .................................................................................................................... 157

Figure N.8 – Symmetrical synthetic test circuit for out-of-phase switching tests on a

complete pole of a circuit-breaker ....................................................................................... 158

Figure N.9 – Full pole test with voltage applied to both terminals and the metal

enclosure ............................................................................................................................ 159

Figure O.1 – Example of combined current and voltage injection circuit with application

of full test voltage to earth .................................................................................................. 161

Figure O.2 – Example of combined current and voltage injection circuit with separated

application of test voltage ................................................................................................... 162

Table 1 – Test circuits for test duties T100s and T100a ........................................................ 17

Table 2 – Test parameters during three-phase interruption for test-duties T10, T30,

T60 and T100s, k = 1,5 ..................................................................................................... 17

Table 3 – Test parameters during three-phase interruption for test-duties T10, T30,

T60 and T100s, k = 1,3 ..................................................................................................... 18

Table 4 – Test parameters during three phase interruption for test-duties T10, T30,

T60 and T100s, k = 1,2 ..................................................................................................... 18

Table 5 – Synthetic test methods for test duties T10, T30, T60, T100s, T100a, SP,

DEF, OP and SLF ................................................................................................................. 31

Table I.1 – Last loop di/dt reduction for 50 Hz for k = 1,3 and 1,5 ...................................... 91

Table I.2 – Last loop di/dt reduction for 50 Hz for k = 1,2 .................................................. 92

Table I.3 – Last loop di/dt reduction for 60 Hz for k = 1,3 and 1,5 ...................................... 93

Table I.4 – Last loop di/dt reduction for 60 Hz for k = 1,2 .................................................. 94

Table I.5 – Corrected TRV values for the first pole-to-clear for k = 1,3 and f = 50 Hz ....... 95

pp r

Table I.6 – Corrected TRV values for the first pole-to-clear for k = 1,3 and f = 60 Hz ....... 96

pp r

Table I.7 – Corrected TRV values for the first pole-to-clear for k = 1,5 and f = 50 Hz ....... 97

pp r

Table I.8 – Corrected TRV values for the first pole-to-clear for k = 1,5 and f = 60 Hz ....... 98

pp r

Table I.9 – Corrected TRV values for the first pole-to-clear for k = 1,2 and f = 50 Hz ....... 98

pp r

Table I.10 – Corrected TRV values for the first pole-to-clear for k = 1,2 and f =

pp r

60 Hz .................................................................................................................................... 99

Table K.1 – Demonstration of arcing times for k = 1,5 ..................................................... 108

Table K.2 – Alternative demonstration of arcing times for k = 1,5 .................................... 109

Table K.3 – Demonstration of arcing times for k = 1,3 ..................................................... 110

Table K.4 – Alternative demonstration of arcing times for k = 1,3 .................................... 111

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– 6 – 62271-101 © IEC:2012

Table K.5 – Demonstration of arcing times for k = 1,5 ..................................................... 112

Table K.6 – Alternative demonstration of arcing times for k = 1,5 .................................... 113

Table K.7 – Demonstration of arcing times for k = 1,3 ..................................................... 114

Table K.8 – Alternative demonstration of arcing times for k = 1,3 .................................... 115

Table K.9 – Procedure for combining k = 1,5 and 1,3 during test-duties T10, T30,

T60 and T100s(b) ............................................................................................................... 116

Table K.10 – Procedure for combining k = 1,5 and 1,3 during test-duty T100a ................ 117

Table L.1 – Test procedure for k = 1,5............................................................................. 129

Table L.2 – Test procedure for k = 1,3............................................................................. 130

Table L.3 – Simplified test procedure for k = 1,3 ............................................................. 131

Table L.4 – Test procedure for k = 1,2............................................................................. 132

Table L.5 – Simplified test procedure for k = 1,2 ............................................................. 133

Table L.6 – Test procedure for asymmetrical currents in the case of k = 1,5 .................... 134

Table L.7 – Test procedure for asymmetrical currents in the case of k = 1,3 .................... 135

Table L.8 – Test procedure for asymmetrical currents in the case of k = 1,2 .................... 136

Table L.9 – Required test parameters for different asymmetrical conditions in the case

of k = 1,5 , f = 50 Hz ...................................................................................................... 139

pp r

Table L.10 – Required test parameters for different asymmetrical conditions in the

case of a k = 1,3 , f = 50 Hz ........................................................................................... 140

pp r

Table L.11 – Required test parameters for different asymmetrical conditions in the

case of k = 1,2 , f = 50 Hz .............................................................................................. 141

pp r

Table L.12 – Required test parameters for different asymmetrical conditions in the

case of k = 1,5 , f = 60 Hz .............................................................................................. 142

pp r

Table L.13 – Required test parameters for different asymmetrical conditions in the

case of k = 1,3 , f = 60 Hz .............................................................................................. 143

pp r

Table L.14 – Required test parameters for different asymmetrical conditions in the

case of k = 1,2, f = 60 Hz ............................................................................................... 144

pp r

Table L.15 – Procedure for combining k = 1,5 and 1,3 during test-duties T10, T30,

T60 and T100s(b) ............................................................................................................... 145

Table L.16 – Procedure for combining k = 1,5 and 1,3 during test-duty T100a ................. 146

Table M.1 – Tolerances on test quantities for type tests (1of 2) .......................................... 148

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62271-101 © IEC:2012 – 7 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
___________
HIGH-VOLTAGE SWITCHGEAR AND CONTROLGEAR –
Part 101: Synthetic testing
FOREWORD

1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising

all national electrotechnical committees (IEC National Committees). The object of IEC is to promote

international co-operation on all questions concerning standardization in the electrical and electronic f

...