ISO/IEC 14576:1999
(Main)Information technology — Synchronous Split Transfer Type System Bus (STbus) — Logical Layer
Information technology — Synchronous Split Transfer Type System Bus (STbus) — Logical Layer
This International Standard specifies the logical specifications of STbus which is a highperformance and highly reliable system bus. STbus adopts a synchronous transfer method with a high-speed clock and a split transfer method enabling to minimize bus holding time during one bus operation and to use a bus efficiently. The contents given in this specifications are as follows: a) System bus interface signal provisions; b) Bus operations and transfer protocol for each bus operation; c) Copyback cache coherency control for maintaining consistency between a shared memory and a cache memory of each processor in a multiprocessor system; d) Fault detection function using parity check and duplex configuration for control signals.
Technologies de l'information — Bus de système de type de transfert de fente synchrone (STbus) — Couche logique
General Information
Standards Content (Sample)
INTERNATIONAL ISO/IEC
STANDARD
14576
First edition
1999-12
Information technology –
Synchronous split transfer type system bus
(STbus) – Logical layer
Technologies de l'information –
Bus de système de transfert de fente synchrone (STbus) –
Couche logique
Reference number
ISO/IEC 14576:1999(E)
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INTERNATIONAL ISO/IEC
STANDARD
14576
First edition
1999-12
Information technology –
Synchronous split transfer type system bus
(STbus) – Logical layer
Technologies de l'information –
Bus de système de transfert de fente synchrone (STbus) –
Couche logique
ISO/IEC 1999
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– ii – 14576 © ISO/IEC:1999(E)
Contents
1. Overview . 1
1.1 Scope . 1
1.2 Applicability . 1
2. Definitions . 3
2.1 Explanation of Terms . 3
2.2 Notation . 5
3. Interface Specifications . 6
3.1 Interface Signals . 6
4. Bus Operations . 11
4.1 Protocol for Basic Operations . 11
4.2 Transfer Protocol . 16
4.2.1 Bus operation types . 16
4.2.2 Command format . 16
4.2.3 Transfer sequence . 25
4.3 Arbitration . 27
4.4 Status Reports . 27
4.5 Data Transfer . 29
4.5.1 Memory access (write) . 29
4.5.2 Memory access (read) . 35
4.5.3 Control space access (write) . 38
4.5.4 Control space access (read) . 40
4.5.5 Message transfer . 42
4.5.6 Control register access (write) . 44
4.5.7 Control register access (read) . 46
4.6 Lock Operations . 48
4.7 Cache-related Operations . 50
4.7.1 Cache invalidation . 50
4.7.2 Retry indication . 53
4.7.3 Copyback and steal operations after retry indication . 55
4.7.4 Steal inhibit operation . 57
4.8 Error Handling . 59
4.8.1 Handling errors notified in answer . 59
4.8.2 Other error detection . 61
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14576 © ISO/IEC:1999(E) – iii –
5. Cache Coherency Control . 62
5.1 Cache Control Methods . 62
5.2 Cache Block Attributes . 62
5.3 Operations on System Bus . 63
5.4 Retry Indication . 65
5.5 Steal Operation . 66
5.6 Cache Data Management and State Transition . 67
5.6.1 Write-through cache . 67
5.6.2 Copyback cache . 70
5.7 Notes on Memory Access . 75
6. Functions for Enhanced Reliability . 76
6.1 Redundancy . 76
6.2 Detecting Faults . 77
6.3 Preventing Faults from Spreading . 77
6.4 Supporting Fault Handling and Diagnosis . 78
Annex A (informative) Performance (Estimated) . 79
Annex B (informative) Return of answer in a lock transfer .80
Annex C (informative) Lock transfer and write back of copyback cache .81
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Figures
Figure 1 - STbus Applications .2
Figure 2 - Connection interface between function units (basic pattern) .7
Figure 3 - Concept of bus operation protocol (for 1-cycle or 2-cycle transfer:
8-byte bus width specification, write operation) .11
Figure 4 - Concept of bus operation protocol (for transfer of 3-cycles or more:
8-byte bus width specification, read operation) .13
Figure 5 - Concept of bus operation protocol (for 1-cycle or 2-cycle transfer:
4-byte bus width specification, write operation) .15
Figure 6 - Pipeline operation.20
Figure 7 - BCT field.21
Figure 8 - RA and byte alignment.23
Figure 9 a) - One-word memory write (no-answer transaction) .31
Figure 9 b) - One-word memory write (basic transaction).32
Figure 9 c) - n-word memory write (no-answer transaction) .33
Figure 9 d) - n-word memory write (basic transaction) .34
Figure 10 a) - One-word memory read.36
Figure 10 b) - n-word memory read.37
Figure 11 - n-word write: control space access.39
Figure 12 - n-word read: control space access .41
Figure 13 - n-word message transfer.43
Figure 14 - One-word write: control register access .45
Figure 15 - One-word read: control register access .47
Figure 16 - Bus lock transfer.49
Figure 17 - Cache invalidation.52
Figure 18 - Retry indication .54
Figure 19 - Copyback and steal operations after retry indication .56
Figure 20 - Steal inhibit operation .58
Figure 21 - Error report in answer transaction when DUT detects error .60
Figure 22 - When function unit (0#) detects time out.61
Figure 23 - Relation between CPU operation and commands on system bus .64
Figure 24 - STbus write-through cache coherency control protocol.69
Figure 25 - STbus copyback cache coherency control protocol .74
Figure A.1 - STbus performance (in 8-byte bus width and 32-bit addressing mode).79
Figure B.1 - Example of dead lock problem .80
Figure C.1 - Example of lock transfer to EM cache data.81
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14576 © ISO/IEC:1999(E) – v –
Tables
Table 1 - Basic Interface Signals (function unit interfaces other than bus handler) .6
Table 2 - Optional Interface Signals (function unit interfaces other than bus handler) .6
Table 3 - Command Format for Information Transfer Bus.17
Table 4 - OPT Code Definitions .18
Table 5 - M Bit Definition .19
Table 6 - Message Sequence .22
Table 7 - Answer Code Definition .28
Table 8 - System Bus Command Types.63
Table 9 - Semantics of Discrepancy between Base and Spare Signals.76
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INFORMATION TECHNOLOGY –
SYNCHRONOUS SPLIT TRANSFER TYPE
SYSTEM BUS (STbus) –
LOGICAL LAYER
FOREWORD
ISO (the International Organization for Standardization) and IEC (the International
Electrotechnical Commission) form the specialized system for worldwide
standardization. National bodies that are members of ISO or IEC participate in the
development of International Standards through technical committees established by
the respective organization to deal with particular fields of technical activity. ISO and
IEC technical committees collaborate in fields of mutual interest. Other international
organizations, governmental and non-governmental, in liaison with ISO and IEC, also
take part in the work.
In the field of information technology, ISO and IEC have established a joint technical
committee, ISO/IEC JTC 1. Draft International Standards adopted by the joint
technical committee are circulated to national bodies for voting. Publication as an
International Standard requires approval by at least 75 % of the national bodies casting
a vote.
International Standard ISO/IEC 14576 was prepared by subcommittee 26:
Microprocessor systems, of ISO/IEC joint technical committee 1: Information
technology.
International Standards are drafted in accordance with the rules given in the ISO/IEC
Directives, Part 3.
Annexes A, B and C are for information only.
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14576 © ISO/IEC:1999(E) – 1 –
INFORMATION TECHNOLOGY –
SYNCHRONOUS SPLIT TRANSFER TYPE
SYSTEM BUS (STbus) –
LOGICAL LAYER
1. Overview
1.1 Scope
This International Standard specifies the logical specifications of STbus which is a high-
performance and highly reliable system bus. STbus adopts a synchronous transfer method with a
high-speed clock and a split transfer method enabling to minimize bus holding time during one
bus operation and to use a bus efficiently.
The contents given in this specifications are as follows:
a) System bus interface signal provisions;
b) Bus operations and transfer protocol for each bus operation;
c) Copyback cache coherency control for maintaining consistency between a shared memory and
a cache memory of each processor in a multiprocessor system;
d) Fault detection function using parity check and duplex configuration for control signals.
1.2 Applicability
This International Standard is Applicable to a high-performance system bus or an I/O bus in a
multiprocessor system. Typical STbus applications are indicated in Figure 1:
a) A System bus and an I/O bus in a TCMP system;
b) A System bus in an LCMP system.
- TCMP: tightly coupled multiprocessor system
(A system consisting of two or more processors sharing the same memory, with the
entire system controlled by one OS.)
- LCMP: loosely coupled multiprocessor system
(A system in which each processor is connected by a shared memory or other medium,
with each processor operated by an individual OS.)
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– 2 – 14576 © ISO/IEC:1999(E)
Processor Processor
Shared
.
CPU
CPU
memory
System
bus
TCMP
system
I/O bus
.
I/O I/O
Processor
Processor
Local memory
Local memory
.
LCMP
system
CPU Local I/O
CPU Local I/O
System bus
Figure 1 - STbus Applications
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14576 © ISO/IEC:1999(E) – 3 –
2. Definitions
2.1 Explanation of Terms
For the purposes of this International Standard, the following terms and definitions apply.
1) Answer transaction
An information transfer operation by which a function unit receiving a command returns
answer information, to notify the unit issuing the command that the command has been
completed (in some cases the requested data is appended) and to indicate status information.
2) Basic signal
Those bus interface signals that must be implemented in every STbus system, and thus for
which compatibility is assured among different systems.
3) Block
The minimum unit registered in cache memory. In STbus this is limited to 32 bytes.
4) Bus handler (BH)
A concentrated bus control mechanism for sorting out competing bus requests from different
function units, selecting one of the requests, and granting the bus right to that function unit.
5) Bus master
A function unit that has the bus right (a grant signal has been asserted) and is transferring
information on the bus.
6) Bus slave
A function unit to which information is being transferred by the bus master.
7) Bus snoop
Monitoring of the bus for read operations from external memory and write operations to
external memory.
8) Cache invalidation
A request to invalidate a block in cache memory. For example, when a write access is made
to a Shared & Unmodified (SU) area, this is used to invalidate the same area in another
cache.
9) CPU
A central processing element with functions for interpreting and executing instructions. In
these specifications, cache memory is included with the CPU.
10) Copyback scheme
A cache updating method in which data written by the processor or instruction execution
part is updated only in the cache, without being reflected directly in memory. The copyback
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cache supported in STbus has the following three internal states: Invalid state (I), Shared &
Unmodified state (SU), Exclusive & Modified state (EM).
11) DUT (Destination Unit)
A function unit performing an answer transaction.
12) Exclusive & Modified state (EM)
An internal state in a copyback cache, whereby the only place in the system an access area is
registered is in cache memory, and the contents are not the same as shared memory. In this
state, only the cache has been updated.
13) Function unit
A hardware unit connected to the bus and having a mechanism for bus interface control.
Normally one function unit consists of one board.
14) I/O adapter
A function unit that controls I/O devices under control of a processor.
15) Invalid state (I)
A state in which an area accessed by the processor is not registered in cache memory.
16) Modified read command
A command issued to the system bus by a copyback cache memory when a write access by
the processor results in a write miss.
17) Optional signal
Those bus interface signals that users are free to adopt or not in system implementation.
18) Order transaction
An information transfer operation for sending a command and requesting processing by
another function unit.
19) Parity
When not otherwise noted in these specifications, parity is always odd. Here odd parity
means that when a given signal (e.g., 8 bits) is augmented by a parity bit (e.g., 8 + 1 = 9
bits), then if the sum of 1-bits in the augmented set is an even number (including 0) an error
is detected.
20) Processor
A function unit with the capability of executing instructions and controlling the various I/O
adapters. Processor consists of CPU and memory in general.
21) Read hit/read miss
When an instruction or operand to be read by the processor is registered in cache memory,
this is called a read hit. If not, it is a read miss.
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14576 © ISO/IEC:1999(E) – 5 –
In the case of a read miss, if the object of the read is cacheable, one block containing the
object is newly registered in the cache.
22) Retry indication
The temporary suspension of access by external devices to a copyback cache area that has
been updated without the change having been reflected in main memory.
23) Shared & Unmodified state (SU)
An internal state in a write-through or copyback cache, whereby an access area is registered
in a cache and has the same contents as shared memory. Sharing by more than one cache is
possible.
24) SUT (Source Unit)
A function unit performing an order transaction.
25) Write hit/write miss
If an area to be written by the processor is registered in cache memory, this is called a write
hit. If not, it is a write miss.
In the case of a write-through cache, the write data is immediately reflected in shared
memory.
If a copyback cache scheme is used, in the case of a write hit the write data is reflected in the
cache only. If a write miss occurs, one block of the write area is read from shared memory
and newly registered, then the write data is written over that area in the cache only.
26) Write-through scheme
A cache updating method in which data written by the processor or instruction execution
part is reflected directly in memory. The internal states are: Invalid state (I), Shared &
Unmodified state (SU).
2.2 Notation
The following symbols and other notation are used in these specifications.
- Function unit numbers are indicated by (#n), and control signals to each unit are written as
[signal line name + (function unit number)], e.g., RQL*(#n), GR*(#n).
- When the values of control signals are indicated, the following notation is used.
- When indicating the logical value of a signal line: 1 and 0 are used, with 1 meaning assert
and 0 meaning negate.
- When indicating the actual value on a signal line: "H" and "L" are used, with "H"
meaning high and "L" meaning low signal potential.
- Hexadecimal notation in these specifications is indicated by H'## (e.g., H'FF, H'00).
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3. Interface Specifications
3.1 Interface Signals
The STbus basic interface signals are listed in Table 1, as seen from one function unit.
In this table, RQL*, RQH*, GR*, and ET* are signals connected individually to each function
unit.
Table 1 - Basic Interface Signals (function unit interfaces other than bus handler)
No. Signal name Count Functional category Connection type
1RQL (Request low) 1
*
2RQH (Request high) 1 Arbitration control Individually
*
connected
3GR (Grant) 1
*
4ET (End of bus transaction) 1
*
5BS (Bus transaction start) 1
*
6BUR (Burst) 1 Transfer control
*
7CSP (Control signal parity) 1
*
8LCK (Lock) 1 Bus connection
*
9 AD [00.63] (Command/address/data) 64 Command/address/data
*
10 ADP [0.7] (AD parity) 8
*
11 RTY (Retry) 1 Cache coherency control
*
12 RST (Reset) 1 Reset signal
*
13 CK (Clock) 1 Clock See Note 2.
Total number of signals 83
Note 1: A after a signal name indicates negative logic.
*
Note 2: For clock connection, a connection configuration must be adopted that can guarantee
the skew specified in the physical specifications.
The optional interface signal lines as seen from one function unit are listed in Table 2. Since
these signals are optional, the system implementor can choose whether or not to use them.
Table 2 - Optional Interface Signals (function unit interfaces other than bus handler)
No. Signal name Count Functional category Connection type
14 LCKS* (Lock spare) 1 Transfer control
15 RTYS* (Retry spare) 1 Bus connection
16 STI* (Steal inhibit) 1 Cache coherency control
17 STIS* (Steal inhibit spare) 1
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14576 © ISO/IEC:1999(E) – 7 –
Connection structure
Function
Function
Function
Clock generator
....
unit(#n)
unit(#1)
unit(#0)
(CK)
Bus handler
(BH)
RQL*
(#0)
ET*
RQH*
RQL*
(#1)
ET*
.
RQH*
.
.
.
.
.
RQL* .
.
(#n)
ET*
RQH*
GR*(#0)
GR*(#1)
.
.
.
.
GR*(#n)
BS*
BUR*
CSP*
LCK*
RTY*
RST*
AD[00.63]*
ADP[0.7]*
n+1: Connected function unit count
CK signal: lndividual signal or bus signal
For clock connection, a connection configuration must be adopted
that can guarantee the skew specified in the physical specifications.
Figure 2 - Connection interface between function units (basic pattern)
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– 8 – 14576 © ISO/IEC:1999(E)
Explanation of each signal
1) RQL* (Request low)
This signal is used by a source unit (SUT) to request the bus. Each unit asserts this signal
when performing an order transaction, for requesting the bus right from the bus handler. A
function unit for which the GR signal is asserted, granting the right to use the bus, must
*
negate this signal.
This signal is notified to the bus handler by each function unit using individual lines.
This signal has a lower priority than that of RQH , RQL and RQH cannot be asserted
* * *
simultaneously.
2) RQH* (Request high)
This signal is used by a destination unit (DUT) to request the bus. Each unit asserts this
signal when performing an answer transaction, in order to request the bus right from the bus
handler. A function unit for which the GR signal is asserted, granting the right to use the
*
bus, must negate this signal.
This signal is notified to the bus handler by each function unit using individual lines.
This signal has a higher priority than that of RQL , RQH and RQL cannot be asserted
* * *
simultaneously.
While a LCK signal is asserted, the bus handler will not assert GR in response to a RQL
* * *
signal from another function unit. However, GR will be asserted in response to RQH , so
* *
any unit is capable of executing an answer transaction.
3) GR* (Grant)
This signal is for granting the bus right to a bus master in response to a RQL or RQH bus
* *
request signal. Only while this signal is asserted, a function unit enables bus drivers (Nos. 5
- 7, 9,10, in Table 1) and send information on the bus. This signal is supplied to each
function unit by the bus handler on individual lines.
4) ET* (End of bus transaction)
This signal is issued by the bus master to give advance notice of the end of transfer data.
This signal is negated two cycles prior to the actual end of a data transfer.
If this signal is not asserted at the same time as RQL or RQH , this is taken to mean that
* *
the requested transaction is a one-cycle transfer.
For a transfer of two cycles or more, ET is asserted at the same time as RQL or RQH .
* * *
This signal is notified to the bus handler by each function unit using individual lines.
5) BS* (Bus transaction start)
When a function unit that has obtained the bus right performs an order transaction or answer
transaction, this signal is asserted at the same time as the command or answer information is
sent on the bus, indicating to the destination function unit the start of transfer information.
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14576 © ISO/IEC:1999(E) – 9 –
This signal is asserted only during the first bus cycle of an order transaction or answer
transaction.
When data is sent following the initial command or answer information, information receipt
must be performed at the initiative of the receiving function unit, using the BS signal as a
*
reference.
6) BUR* (Burst)
This signal indicates burst transfer mode, consisting of two or more data transfer cycles.
The sending function unit asserts this signal, and while it is asserted the receiving function
unit continues to receive data.
This signal is negated one cycle prior to the end of data transfer. When the receiving
function unit detects the negation of this signal, it ends the receiving operation after one
cycle.
If a BS signal is asserted and BUR is not asserted, one-cycle transfer is indicated.
* *
7) CSP* (Control signal parity)
This is a parity signal for the transfer control signals BS and BUR . It indicates odd parity.
* *
8) LCK* (Lock)
This is a bus lock signal. It is asserted at the same time as the SUT starts an order
transaction, and is negated when the SUT itself indicates the end of a transaction.
Split transfer is the main method adopted for STbus, but interlock transfer using this signal
is also possible.
9) AD [00.63]* (Command / address / data 00-63)
This is a 64-bit two-way information transfer bus for time division transfer of control
information, address information, and data.
10) ADP [0.7]* (AD parity 0-7)
These are parity signals for each byte of AD[00-63] . They indicate odd parity.
*
11) RTY* (Retry)
This signal is used for coherency control when a copyback cache scheme is used in a TCMP
system. When this signal is asserted, the bus master must retry the current transaction. See
5.4 Retry Indication for details.
12) RST* (Reset)
A function unit connected to STbus uses this signal to indicate a reset to other function
units. While this signal is asserted, reset is in effect. Assertion time of this signal is
specified to be 5 μs-10 μs. Assertion timing shall be synchronized with the bus clock.
13) CK (Clock)
This is the STbus common clock signal. Bus operations are synchronized with the falling
edge of this signal.
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14) LCKS*(Lock spare)
This is a spare LCK* signal. When this signal is used, LCK* must also be used at the same
time. If either LCK* or this signal is asserted alone, the lock transfer is not effective. The
lock transfer is performed, only when both LCK* and this signal are asserted. This signal is
optional.
15) RTYS* (Retry spare)
This is a spare RTY signal. When this signal is used, RTY must also be used at the same
* *
time. If either RTY or this signal is asserted alone, the bus master must retry the current
*
transaction. This signal is optional.
16) STI* (Steal inhibit)
This is a signal used in copyback cache coherency control. It is connected only between
function units. This signal is optional.
When this signal is asserted, the bus master prohibits a steal operation during copyback of
data concerned. See 5.5 Steal Operation for details.
17) STIS* (Steal inhibit spare)
This is a spare STI signal. When this signal is used, STI must also be used at the same
* *
time. If either STI or this signal is asserted alone, the bus master prohibits a steal operation
*
during copyback of data concerned. This signal is optional.
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14576 © ISO/IEC:1999(E) – 11 –
4. Bus Operations
4.1 Protocol for Basic Operations
Examples of basic STbus ope
...
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