ISO/IEC 10861:1994
(Main)Information technology — Microprocessor systems — High-performance synchronous 32-bit bus: MULTIBUS II
Information technology — Microprocessor systems — High-performance synchronous 32-bit bus: MULTIBUS II
Defines the operation, functions, and attributes of the IEEE 1296 bus standard. Defines a high-performance 32-bit synchronous bus standard. Intended for general purpose applications to optimize block transfers, including protocol for message passing. Intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system and heterogeneous processor types in the same system.
Technologies de l'information — Systèmes à microprocesseurs — Bus 32 bits synchrone à haute performance: MULTIBUS II
General Information
Standards Content (Sample)
ISO/IEC
INTERNATIONAL
10861
STANDARD
ANWIEEE
Std 1296
First edition
1994-04-27
Information technology-
Microprocessor systems-
High-Performance synchronous 32-bit bus:
MULTIBUS ll
Technologies de I ’information -
Sysfemes 2 microprocesseurs -
Bus 32 bits synchrone ti haute Performance:
MlJL TlBlJS ll
Reference number
ISO/IEC 10861 : 1994(E)
ANSVIEEE
Std 1296, 1994 Edition
---------------------- Page: 1 ----------------------
Abstract: The Operation, functions, and attributes of a parallel System bus (PSB), called MULTI-
BUS II, are defined. A high-performance backplane bus intended for use in multiple processor sys-
tems, the PSB incorporates synchronous, 32-bit multiplexed address/data, with error detection, and
uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art Operation and
to allow the implementation of tost-effective, high-performance VLSI for the bus interface. Memory,
WO, message, and geographic address spaces are defined. Error detection and retry are provided
for messages. The message-passing design allows a VLSI implementation, so that virtually all mod-
ules on the bus will utilize the bus at its highest petformance-32 to 40 Mbyte/s. An overview of
PSB, Signal descriptions, the PSB protocol, electrical characteristics, and mechanical specifications
are covered.
Keywords: high-performance synchronous 32-bit bus, MULTIBUS II, System bus architectures
The Institute of Electrical and Electronics Engineers, Inc.
345 East 47th Street, New York, NY 10017-2394, USA
Copyright 0 1994 by the Institute of Electrical and Electronics Engineers, Inc.
United States of America.
All rights reserved . Published 1994. Printed in the
ISBN 1-55937-368-7
in any form, in an electronie re trieval the Prior
No part of this publication may be reproduced System or o therwise, without
written permission of the publisher.
April 27, 1994 SH16766
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ISO/IEC 10861 : 1994
[ANWIEEE Std 1296,1994 Edition]
Information technology-
Microprocessor systems-
High-Performance synchronous
32-bit bus: MULTIBUS ll
Sponsor
Technical Committee on Microprocessors and Microcomputers
of the
IEEE Computer Society
Adopted as an International Standard by the
International Organization for Standardization
and by the
International Electrotechnical Commission
- American National Standard
Published by
The Institute of Electrical and Electronics Engineers, Inc.
---------------------- Page: 3 ----------------------
Foreword
ISO (the International Organization for Standardization) and IEC (the International
Electrotechnical Commission) form the specialized System for worldwide standard-
ization. National bodies that are members of ISO or IEC participate in the develop-
ment of International Standards through technical committees established by the
respective organization to deal with particular fields of technical activity. ISO and
IEC technical committees collaborate in fields of mutual interest. Other international
organizations, governmental and nongovernmental, in liaison with ISO and IEC, also
take part in the work.
In the field of information technology, ISO and IEC have established a joint technical
committee, ISO/IEC JTC 1. Draft International Standards adopted by the joint tech-
nical committee are circulated to national bodies for voting. Publication as an Inter-
national Standard requires approval by at least 75% of the national bodies casting a
vote.
In 1990, ANSUIEEE Std 1296-1987 was adopted by ISO/IEC JTC 1, as draft Interna-
tional Standard ISO/IEC/DIS 10861. This draft was subsequently approved by ISO/
IEC JTC 1 in the form of this edition, which is published as International Standard
ISO/IEC 10861 : 1994.
International Organization for Standardization/International Electrotechnical Commission
Case postale 56 l CH-1211 Geneve 20 l Switzerland
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Introduction
(This introduction is not a normative part of ISO/IEC 10861 : 1994 [ANSMEEE Std 1296, 1994 Edition], but is
included for information only.)
In the last decade, the avalanche of new microcomputer technology, especially VLSI, threatened to obsolete
products almost before they went into production. To buffer users from this onrush of technology, Intel
helped develop Standard interfaces. One of the most notable was the MULTIBUS 1 System bus, which was
used as the basis for a Standard by the IEEE in 1983 as IEEE Std 796-1983 (after going through a 5-year
review and revision process).
In the early 1980s Intel recognized that the trends toward multiprocessing and more sophisticated micro-
computer-based Systems called for an advanced 32-bit System bus architecture. Intel called this new bus
MULTIBUS 11. In continuing to pioneer the open Systems technology, which included multiprocessing, four
critical requirements were observed: technical credibility, processor independence, standardization, and
openness to all levels of integration. Early in the development of the new bus, Intel established a “MULTI-
” The consortium gave the new bus a technical credibility that few buses,
BUS 11 Development Consortium.
especially those defined only among board vendors, tan match. The companies in the consortium also repre-
sented all microprocessor families; included in the group were 68020, 32032, 80386, and 28000 board and
System users, thus ensuring that the bus is easily adaptable to virtually any manufacturer ’s processor.
The primary benefits being sought in the creation of this new bus were high-performance multiprocessing,
high System reliability, ease-of-use System desi .gners, and improved cost/performance.
bY
Specific bus features were developed in response to these objectives. The 32 Mbyte/s message passing of the
bus provides a bus that acts like a very high-speed network connection for multiple processors (or processor
equivalents). There is a recognition that the bus is no longer to interconnect a CPU with its memory and I/O;
instead the bus is to interconnect whole stand-alone processors with each other and with intelligent “sub-
Systems-on-a-board.”
System reliability is enhanced by the features of bus parity, synchronous Operation, negative acknowledge,
transfer retries, geographic addressing, and advanced backplane design. Ease-of-use by System designers is
implemented primarily through the geographic addressing, which provides for dynamic System configura-
tion. The bus encourages the use of Software programmable configuration Options (and discourages any use
of mechanical jumpers). The standardization of the high-level message-passing protocol also gives the
System designer an easy-to-use capability for interprocessor communication.
The costiperformance objective of the bus is delivered through its specification of a realizable 32 to
40 Mbytels bus bandwidth. Virtually all boards designed to the bus tan achieve this bus utilization factor
and thus the availability of Standard, high-
due to the high-level protocol called out in the specification,
Performance and tost-effective VLSI components to actually implement this level of Performance. For
example, this specification and the VLSI make it possible for eight concurrent 4 megabyte/second transfers
to take place on the bus. This, or other combinations of transfers that add up to 32 Mbyte/s, demonstrate the
real cost/performance advantages of the bus for multiprocessor applications.
In 1983 MULTIBUS 11 was introduced to the IEEE Standards process as a part of the considerations for the
P896 (Future Bus) working group activities. In the 1984/1985 time frame the MSC (Microcomputer Stan-
dards Committee, of the TCMM) formed an independent study group for MULTIBUS 11. During this time
the many active participants of the group proceeded to thoroughly review and make changes to the proposed
draft. In early 1986 the group was assigned a formal project number P1296. During the remainder of 1986,
the draft was passed by the Working Group and the MSC after thorough review, discussion, and changes. In
1987, the draft was presented for Sponsor ballot and, after passing, presented to the June 1987 meeting of
the IEEE Standards Board.
1v
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The IEEE Standards Board calls attention to the fact that there are Patents claimed and/or pending on many
aspects of this bus by Intel Corporation. IEEE takes no Position with respect to patent validity. Intel Corpo-
ration has assured the IEEE that it is willing to grant a license for these Patents on reasonable and nondis-
criminatory terms to anyone wishing to obtain such a license. The general terms of the license are a one-time
administration fee of $100 for a nonexclusive perpetual license. Intel Corporation ’s undertakings in this
respect are on file obtained from the legal department of Intel Corporation whose address is Intel Corpora-
tion, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97 124.
There were many contributors to the Standards review process, but the following members deserve special
menti on for their active participation:
Task Forte Coordinators: Jack Blevins
Maurice Hubert
Hubert Kirrmann
Jim Nebus
Secretary of Working Group: Steve Cooper
Original Study Group Chairman: Paul Borrill
Original Draft Editor: Scott Tetrick
The Pl296 Working Group that prepared this Standard had the following membership:
Richard W. Boberg, Chair
Web Augustine Gene Freehauf Ken Smith
Jack Blevins Maurice Hubert Michael Thompson
Paul Borrill Hubert Kirrmann Scott Tetrick
Steve Cooper Klaus Mueller Eike Waltz
Tom Crawford Jim Nebus Janusz Zalewski
Don Nickel
The following members of the Technical Committee on Microprocessors and Microcomputers were on the
balloting body:
Andrew Allison Martin Freeman
Deene Ogden
Peter J. Ashenden David Gustavson Tom Pittman
Matt Biewer Tom Harkaway
Shlomo Pri-Tal
John Black Dave Hawley P. Reghunathan
David James
Jack Blevins Richard Rawson
Richard Boberg Laure1 Kaleda Bill Shields
Paul Borrill Richard Karpinski Michael Smolin
Bradley Brown Hubert Kirrman Robert Stewart
Clyde Camp Doug Kraft Subramanganesan
John D. Charlton Tom Kurihara Michael Teener
Steve Cooper Glen Langdon Scott Tetrick
Randy Davis Gerry Laws Eike Waltz
J. Robert Davis Tom Leonard Carl Warren
Shirish P Deodhar Rollie Linser George White
Jim Dunlay Gary Lyons Fritz Whittington
Wayne Fischer James Nebus Tom Wicklund
Jim Flournoy Gary Nelson Andrew Wilson
Gordon Forte Anthony Winter
V
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When the IEEE Standards Board approved this Standard on June 11, 1987, it had the following membership:
Donald C. Fleckenstein, Chair Marco W. Migliaro, Kce Chair
Andrew G. Salem, Secretary
James H. Beall Leslie R. Kerr L. John Rankine
Dennis Bodson Jack Kinn John I? Riganati
Marshall L. Cain Irving Kolodny Gary S. Robinson
James M. Daly Joseph L. Koepfinger* Frank L. Rose
Stephen R. Dillon Edward Lohse Robert E. Rountree
Eugene I? Fogarty John May Sava 1. Sherr*
Jay Forster Lawrence V. McCall William R. Tackaberry
Kenneth D. Hendrix L. Bruce McClung William B. Wilkens
Irvin N. Howell Donald T. Michael* Helen M. Wood
*Member Emeritus
IEEE Std 1296-1987 was approved by the American National Standards Institute on February 8, 1987 and
was reaffirmed by IEEE on March 17, 1994.
vi
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Contents
PAGE
CLAUSE
1
General overview to the IEEE 1296 Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.
1
............................................................................................................................................
1.1 Scope
1
1.2 Normative references .
3
. . . . . . . . . . . . . . . .*.
2. Definitions
7
..................................................................................................................................
3. Guide to notation
7
.........................................................................................................................................
3.1 General
7
.............................................................................................................................
3.2 Signal notation
7
.............................................................................................................................
3.3 Figure notation
8
...................................................................................................
3.4 Notation in state-flow diagrams
9
...............................................................................
3.5 Notation for multiple bit data representation
10
PSB overview .
4.
10
.......................................................................................................................................
4.1 General
11
...........................................................................
4.2 Address/data path and System control Signals
11
............................................................................................................
4.3 Message-passing facility
11
...................................................................................................................
4.4 Interconnect facility
11
............................................................................................
4.5 Synchronous Operation of the PSB
11
.........................................................................................................
4.6 Bus operations on the PSB
15
.............................................................................................................
4.7 Central Services module
16
.............................................................................................................................
5. Signal descriptions
16
.......................................................................................................................................
5.1 General
16
.............................................................................................................................
5.2 Signal groups
25
......................................................................................................................................
6. PSB protocol
25
6.1 General .
25
..................................................................................................................
6.2 Arbitration Operation
36
6.3 Transfer Operation .
54
...................................................................................................................
6.4 Exception Operation
58
............................................................................................................
6.5 Central control functions
64
6.6 State-flow diagrams .
76
Electrical characteristics .
7.
76
7.1 General .
77
7.2 AC timing specifications .
84
.....................................................................................................
7.3 DC specifications for Signals
85
..............................................................................................
7.4 Current limitations per connector
86
..........................................................................................................................
7.5 Pin assignments
88
..................................................................................................................
8. Mechanical specifications
88
.......................................................................................................................................
8.1 General
89
8.2 Board sizes and dimensions .
........................................................................................... 90
8.3 Printed board layout considerations
90
8.4 Front Panel .
90
8.5 Connectors .
91
8.6 Backplanes .
vii
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PAGE
CLAUSE
100
IEEE 1296 System Interface specification .
9.
100
9.1 Overview .
101
9.2 Interconnect space Operation .
115
9.3 I/O space Operation .
115
9.4 Memory space operations .
116
9.5 Message space operations .
127
IEEE 1296 capabilities .
10.
127
10.1 Characteristic Codes .
ANNEX
129
Recommended documentation practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Annex A
. . .
VI11
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Information technology-Microprocessor
Systems-High-Performance synchronous
32-bit Bus: MULTIBUS II
1. General overview
1.1 Scope
This International Standard defines the Operation, functions, and attributes of the IEEE 1296 bus
Standard.
a) This Standard defines a high-performance 32-bit synchronous bus Standard.
b) The bus Standard must have a design-in lifetime of 10 years with backward compatibility.
c) The Standard is intended for general purpose applications to optimize block transfers, including
protocol for message passing. For real-time applications, the bus will provide a means of ensuring
an upper limit to message delivery time.
d) The Standard is intended to be compatible with existing IEC mechanical Standards (IEC Pub
297-1,’ 297-3, and 603-2) with recognition of the need for special front Panels to address ESD,
EMI, and RF1 requirements.
e) Options within the Standard will be clearly identified.
f) The Standard is intended to support multiple processor modules in a functionally partitioned
configuration and heterogeneous processor types in the same System.
g) The Standard is intended to support heterogeneous processor types in the same System.
h) Message-passing format and protocol is intended for future migration to a serial System bus.
1.2 Normative references
The following Standards contain provisions which, through references in this text, constitute provisions of
this International Standard. At the time of publication, the editions indicated were valid. All Standards are
subject to revision, and Parties to agreements based on this International Standard are encouraged to investi-
gate the possibility of applying the most recent edition of the Standards listed below. Members of IEC and
ISO maintain registers of currently valid International Standards.
DIN 41612, Two Part Connectors for Printed Board, GRIB, to 54 mm, Common Mounting Features, Survey
of Types.
* Information on references tan be found in 1.2.
2 DIN publications are available from the Deutsches Institut für Normung, Burggrafenstrasse 6, D- 1000 Berlin 30, Germany.
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ISO/IEC 10861 : 1994
[ANSVIEEE Std 1296, 1994 Edition] HIGH-PERFORMANCE SYNCHRONOUS 32-BIT BUS:
IEC 297-1 : 1986, Dimensions of mechanical structures of the 482,6 mm (19 in) series-Part 1: Panels and
racks.3
IEC 297-3 : 1984, Dimensions of mechanical structures of the 482,6 mm (19 in) series-Part 3: Subracks
and associated plug-in units.
IEC 603-2 : 1988, Connectors for frequences below 3 MHz for use with printed boards-Part 2: Two-par-t
connectors for printed boards, for basic grid of 2,54 mm (0,l in), with common mounting features.
IEEE Std 1 lOl- 1987, IEEE Standard for Mechanical Core Specifications for Microcomputers (ANSI).4
31EC Standards are available from the IEC Sales Department, Case Postale 131, 3 rue de Varembe, CH-121 1, Geneve 20, Switzerland/
Suisse.
41EEE publications are available from the Institute of Electrical and Electronics Engineers, Service Center, 445 Hoes Lane, P.O. Box
133 1, Piscataway, NJ 08855133 1, USA.
2
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ISO/IEC 10861 : 1994
MULTIBUS II [ANSVIEEE Std 1296, 1994 Edition]
2. Def initions
The following definitions apply to all clauses of this International Standard.
2.1 acquisition Phase: The final Phase of the arbitration Operation entered after determining that an
agent has the highest priority and the bus is available. See: arbitration Operation; agent.
from
2.2 address transfer: The passing of address information over the multiplexed address/ data bus
the bus owner in Order to select the replying agent(s). See: bus owner; replying
2.3 address/data bus Signal group: A set of thirty-six (36) Signals, consisting of 32 address/ data Signals
and four parity si 1s that are used for address and data transfers.
gna
2.4 agent: A physical unit that has an interface to the parallel System bus, for example, a Single-board
Computer.
2.5 agent error: An agent Status that indicates an error condition in a replying agent.
2.6 agent Status: The condition of the replying agent, transmitted during the reply Phase of a transfer
Operation. See: reply Phase; transfer Operation.
to the
2.7 arbitration Operation: The bus Operation in which agents attempt to gain exclusive access
parallel System bus.
2.8 backplane: The physical mechanism by which Signals are routed between agents.
2.9 bit (b): A binary digit.
2.10 broadcast message: A sequence of one or more data transfers from the bus owner to all replying
agents, with uninterrupted bus ownership.
2.11 bus clock cycle: An amount of time equal to one bus clock period, nominally 100 nanoseconds.
2.12 bus 10s~: The amount of time required fo r a valid sign al tran .sition to occur at every Point on the
backplane. This value is equivalent to two bus propagation delays plus the clock skew.
2.1 3 bus Operation: The basic unit of processing whereby digital Signals effect the transfer of data across
an interface by means of a sequence of control Signals and an integral number of bus clock cycles.
2.1 4 bus owner: The agent that enters the acq uisition Phase of the arbitration Operation and initiates one
or more transfer operations. See: acquisition Phase; arbitration Operation; transfer Operation.
that simul-
2.15 bus request sequence: A set of 0 ne or more arbitration operations in which all agents
tane ously request the bus become the bus owner, one at a time. See: arbitration Operation; bus owner.
2.16 byte (B): A group of eight adjacent bits operated on as a unit.
2.17 central Services module (CSM): A specific module that is required in all Systems using the parallel
System bus. Its Services, such as starting certain bus operations and guaranteeing uniform initialization of
all agents, are required by all agents on the parallel System bus. It is always located in a specific slot in the
System backplane. See: parallel System bus.
Services of a server. See: server.
2.18 client: An agent that requests
2.19 cold-Start: A sequence of events performed on the application of power that ensures a uniform
initialization period for all agents, giving them the ability to begin Operation from a known state.
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ISO/IEC 10861 : 1994
[ANSVIEEE Std 1296, 1994 Edition] HIGH-PERFORMANCE SYNCHRONOUS 32-BIT BUS:
2.20 command transfer: The passing of command information over the System control Signal group,
from the bus owner to the replying agent(s), during the request Phase of a transfer Operation. Command
information includes Parameters for the impending transfer Operation, as well as additional address space
information not transmitted with the address transfer. See: request Phase; System control Signal group.
2.21 data transfer: The passing of data over the multiplexed address/data bus, between the bus owner
and the replying agent(s), during the reply Phase of a transfer Operation.
2.22 driving agent: The agent that is permitted to assert or negate a Signal on the bus.
.t t hat supports both memory-mode and mess age-mode communication
2.23 dual-mode agent: An agen
on the parallel System bus. See: m .emory-mode agent; message-mode agent.
2.24 dual-mode System: A System that supports both memory-mode and message-mode communica-
tion. A mixture of both communication types is used on the parallel System bus.
2.25 end of transfer (EOT) Status: A handshake Status that indicates the last data transfer of the transfer
Operation. See: handshake Status.
2.26 exception: An abnormal condition on the bus caused by either a bus parity error, a bus time-out, a
protocol Violation, or a bus
...
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