SIST EN 60821:1994

IEC 60821 VMEbus - Microprocessor system bus for 1 byte to 4 byte data

This document specifies a high performance backplane bus for  use in microcomputer systems that employ single or multiple  microprocessors. The bus supports 4 sub-buses: Data  Transfer Bus, Priority Interrupt Bus, Arbitration Bus and Utility  Bus. Data transfer is supported for 8-, 16- and 32-bits data  using asynchronous and fully handshaken protocols.

IEC 60821 VMEbus - Mikroprozessor-Systembus für 1- bis 4-Byte-Daten

Bus CEI 60821 VMEbus - Bus système de microprocesseurs pour données de 1 octet à 4 octets

Décrit un bus de fond de panier à haute performance utilisable dans les systèmes à microprocesseurs. Ce bus parallèle permet des cycles de transfert, soit uniques, soit par blocs, sur une voie d'adresses et de données de 32 bits non multiplexées. La transmission est gérée par un protocole de dialogue asynchrone. L'allocation du bus permet une architecture multiprocesseur. Ce bus permet également l'utilisation d'interruptions entre modules, facilitant une réponse rapide à des événements internes ou externes. La mécanique des cartes et des châssis est conçue à partir de la EN 60297. Notes: 1. Ce bus est similaire au bus VME. 2. Pour le prix de cette publication, veuillez consulter la liste du code-prix ISO/CEI.

IEC 60821 VMEbus – Mikroprocesorsko sistemsko vodilo za 1- do 4-bajtne podatke (IEC 60821:1991, spremenjen)

General Information

• Status: Published
• Publication Date: 30-Nov-1994
• ICS: 35.160 - Microprocessor systems
• Technical Committee: KIN - Mains communicating systems
• Current Stage: 6060 - National Implementation/Publication (Adopted Project)
• Start Date: 01-Dec-1994
• Due Date: 01-Dec-1994
• Completion Date: 01-Dec-1994
• Ref Project: EN 60821:1994 - IEC 60821 VMEbus - Microprocessor system bus for 1 byte to 4 byte data

Standards Content (Sample)

SLOVENSKI SIST EN 60821:1994

STANDARD
december 1994
IEC 60821 VMEbus – Mikroprocesorsko sistemsko vodilo za 1- do 4-bajtne
podatke (IEC 60821:1991, spremenjen)
IEC 60821 VMEbus - Microprocessor system bus for 1 byte to 4 byte data (IEC
60821:1991, modified)
ICS 35.160 Referenčna številka
SIST EN 60821:1994(en)
©  Standard je založil in izdal Slovenski inštitut za standardizacijo. Razmnoževanje ali kopiranje celote ali delov tega dokumenta ni dovoljeno

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NORME
CEI
INTERNATIONALE IEC
60821
INTERNATIONAL
Deuxième édition
STANDARD
Second edition
1991-12
Bus CEI 821 VMEbus
—
Bus système à microprocesseurs
Pour données de 1 octet à 4 octets
IEC 821 VMEbus —
Microprocessor system bus
fir 1 byte to 4 byte data
© CEI/ISO 1991 Droits de reproduction réservés — Copyright - all rights reserved
Aucune partie cette
de publication ne peut être reproduite ni No part of this publication may be reproduced or utilized in
utilisée sous
quelque forme que ce soit et par aucun any form or by any means, electronic or mechanical,
procédé, électronique ou mécanique, y compris la photo- including photocopying and microfilm, without permission in
copie les
et microfilms, sans l'accord écrit de l'éditeur. writing from the publisher.
Intern
ational Electrotechnical Commission 3, rue de Varembé Geneva, Switzerland
Telefax: [phone] e-mail: [e-mail] IEC web site http: //www.iec.ch
IEC
ISO
•

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821 © IEC -3-
CONTENTS
Page
FOREWORD 21
CHAPTER 0: INTRODUCTION
Section
0.1 Scope 23
0.2 Normative references 23
0.3 Note to the reader 23
CHAPTER 1: INTRODUCTION TO THE IEC 821 BUS STANDARD
1.1 IEC 821 BUS standard objectives 25
1.2 IEC 821 BUS interface system elements 25
1.2.1 Basic definitions 25
1.2.1.1 Terms used to describe the IEC 821 BUS mechanical structure 25
1.2.1.2 Terms used to describe the IEC 821 BUS functional structure 27
1.2.1.3 Types of cycles on the IEC 821 Bus 31
1.2.2 Basic IEC 821 BUS structure 33
1.3 IEC 821 BUS standard diagrams 41
1.4 Standard terminology 41
1.4.1 Signal line states 43
1.4.2 Use of the asterisk (*) 45
1.5 Protocol specification 45
1.5.1 Interlocked bus signals 47
1.5.2 Broadcast bus signal 47
1.6 System examples and explanations 49
CHAPTER 2: IEC 821 BUS DATA TRANSFER BUS
2.1 Introduction 51
2.2 Data Transfer Bus lines 51
2.2.1 Addressing lines 55
2.2.2 Address modifier lines 57
2.2.3 Data lines 61
2.2.4 Data Transfer Bus control lines 63
2.2.4.1 AS* 63
2.2.4.2 DSO* and DS1* 63
2.2.4.3 OTACY.* 65
2.2.4.4 BERR* 65
2.2.4.5 WRITE* 67
2.3 DTB modules - Basic description 67
2.3.1 MASTER 67
2.3.2 SLAVE 73
2.3.3 BUS TIMER 77
2.3.4 LOCATION MONITOR 81
2.3.5 Addressing modes 83
2.3.6 Basic data transfer capabilities 87
2.3.7 Block transfer capabilities 93
2.3.8 Read-modify-write capabilities 99
2.3.9 Unaligned transfer capabilities 103

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- 5 -
821 © IEC
Section Page
2.3.10 ADDRESS-ONLY capability 109
2.3.11 Interaction between DTB functional modules 109
2.4 Typical operation 113
2.4.1 Typical data transfer cycles 113
2.4.2 Address pipelining 123
2.5 Data Transfer Bus acquisition 125
2.6 DTB timing rules and observations 129
CHAPTER 3: IEC 821 BUS DATA TRANSFER BUS ARBITRATION
3.1 Bus arbitration philosophy 203
3.1.1 Types of arbitration 203
3.2 Arbitration bus lines 207
3.2.1 Bus request and bus grant lines 211
3.2.2 Bus busy line (BBSY*) 211
3.2.3 Bus clear line (BCLR*) 211
3.3 Functional modules 213
3.3.1 ARBITER 213
3.3.2 REQUESTER 221
3.3.3 Data Transfer Bus MASTER 229
3.3.3.1 Release of the DTB 229
3.3.3.2 Acquisition of the DTB 231
3.3.3.3 Other information 231
3.4 Typical operation 231
3.4.1 Arbitration of two different levels of bus request 231
3.4.2 Arbitration of two bus requests on the same bus request line 241
3.5 Race conditions between MASTER requests and ARBITER grants 249
CHAPTER 4: IEC 821 BUS PRIORITY INTERRUPT BUS
4.1 Introduction 251
4.1.1 Single handler systems 251
4.1.2 Distributed systems 251
4.2 Priority Interrupt Bus lines 259
4.2.1 Interrupt request lines 259
4.2.2 Interrupt acknowledge line 259
4.2.3 Interrupt acknowledge daisy-chain - IACKIN*/IACKOUT* 259
4.3 Priority Interrupt Bus modules - Basic description 261
4.3.1 INTERRUPT HANDLERS 263
4.3.2 INTERRUPTER 267
4.3.3 IACK DAISY-CHAIN DRIVER 275
4.3.4 Interrupt handling capabilities 277
4.3.5 Interrupt request capabilities 279
4.3.6 STATUS/ID transfer capabilities 279
4.3.7 Interrupt release capabilities 281
4.3.8 Interaction between Priority Interrupt Bus modules 285
4.4 Typical operation 293
4.4.1 Single handler interrupt operation 293
4.4.2 Distributed interrupt operation 295
4.4.2.1 Distributed interrupt systems with seven INTERRUPT HANDLERS 295
4.4.2.2 Distributed interrupt systems with two to
six INTERRUPT HANDLERS 297

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821 © IEC
Section Page
4.4.3 Example: typical single handler interrupt system operation 299
4.4.4 Example: prioritization of two interrupts in a distributed interrupt system 307
4.5 Race conditions 311
4.6 Priority Interrupt Bus timing RULES and OBSERVATIONS 311
CHAPTER 5: IEC 821 BUS UTILITY BUS
5.1 Introduction 361
5.2 Utility Bus signal lines 361
5.3 Utility Bus modules 361
5.3.1 The SYSTEM CLOCK DRIVER 361
5.3.2 The SERIAL CLOCK DRIVER 361
5.3.3 The POWER MONITOR 361
5.4 System initialization and diagnostics 371
5.5 Power pins 377
5.6 RESERVED line 377
CHAPTER 6: IEC 821 BUS ELECTRICAL SPECIFICATIONS
6.1 Introduction 381
6.2 Power distribution 381
6.2.1 D.C. voltage specifications 383
6.2.2 Pin and socket connector electrical ratings 385
6.3 Electrical signal characteristics 385
6.4 Bus driving and receiving requirements 387
6.4.1 Bus driver definitions 387
6.4.2 Driving and loading RULES for all IEC 821 BUS lines 389
6.4.2.1 Driving and loading RULES for high current three-state lines
(AS*, DSO*, DS1*) 389
6.4.2.2 Driving and loading RULES for standard three-state lines
(A01-A31, D00-D31, AMO-AM5, IACK*, LWORD*, WRITE*) 391
6.4.2.3 Driving and loading RULES for high current totem-pole lines
(SERCLK, SYSCLK, BCLR*) 393
6.4.2.4 Driving and loading RULES for standard totem-pole lines
(BGOOUT*-BG3OUT*/BGOIN*-BG3IN*, IACKOUT*/IACKIN*) 395
6.4.2.5 Driving and loading RULES for open-collector lines
(BRO*-BR3*, BBSY*, IRQ1*-IRQ7*, DTACK*, BERR*, SYSFAIL*, SYSRESET*,
ACFAIL*, IACK*) 397
6.5 Backplane signal line interconnections 397
6.5.1 Termination networks 399
6.5.2 Characteristic impedance 401
6.5.3 Additional information 407
6.6 User defined signals 409
6.7 Signal line drivers and terminations 409
CHAPTER 7: IEC 821 BUS MECHANICAL SPECIFICATIONS
7.1 Introduction 413
7.2 IEC 821 BUS boards 415
7.2.1 Single height boards 417
7.2.2 Double height boards 417

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821©IEC
Section Page
7.2.3 Board connectors 419
7.2.4 Board assemblies 421
7.2.5 Board widths 421
7.2.6 IEC 821 BUS board warpage, lead length and component height 421
7.3 Front panels 423
7.3.1 Handles 425
7.3.2 Front panel mounting 427
7.3.3 Front panel dimensions 427
7.3.4 Filler panels 429
7.3.5 Board ejectors/injectors 429
7.4 Backplanes 431
7.4.1 Backplane dimensional requirements 433
7.4.2 Signal line termination networks 433
7.5 Assembly of IEC 821 BUS subracks 435
7.5.1 Subracks and slot widths 435
7.5.2 Subrack dimensions 435
7.6 IEC 821 BUS backplane connectors and IEC 821 BUS board connectors 477
7.6.1 Pin assignments for the J1/P1 connector 477
7.6.2 Pin assignments for the J2 /P2 connector 479
APPENDIX A - Glossary of IEC 821 BUS terms 481
APPENDIX B - IEC 821 BUS connector/pin description 493
APPENDIX C - Use of the SERCLK and SERDAT* lines 499
APPENDIX D - Metastability and resynchronization 503
APPENDIX E - Permissible capability subsets 545
Figures
1-1: System elements defined by this standard 37
1-2: Functional modules and buses defined by this standard 39
1-3: Signal timing notation 49
2-1: Data Transfer Bus functional block diagram 53
2-2: Block diagram: MASTER 69
2-3: Block diagram: SLAVE 73
2-4: Block diagram: BUS TIMER 77
2-5: Block diagram: LOCATION MONITOR 81
2-6: Four ways that 32 bits of data might be stored in memory 103
2-7: Four ways that 16 bits of data might be stored in memory 105
2-8: An example of a single byte read cycle 117
2-9: An example of a double byte write cycle 119
2-10: An example of a quad byte write cycle 121
2-11: Data Transfer Bus MASTER exchange sequence 127
2-12: MASTER, SLAVE and LOCATION MONITOR - Address broadcast timing
ALL CYCLES 165
2-13: MASTER, SLAVE and LOCATION MONITOR - Address broadcast timing
Single even byte transfers)
single odd byte transfers)
double byte transfers;
quad byte transfers)
unaligned transfers 167

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821 © IEC
Figures Page
2-14: MASTER, SLAVE and LOCATION MONITOR - Address broadcast timing
Single byte block transfers;
double byte block transfers;
quad byte block transfers 169
2-15: MASTER, SLAVE and LOCATION MONITOR - Address broadcast timing
Single byte RMW cycles;
double byte RMW cycles;
quad byte RMW cycles 171
2-16: MASTER, SLAVE and LOCATION MONITOR - Data transfer timing
BYTE(0) READ;
BYTE(1) READ;
BYTE(2) READ;
BYTE(3) READ;
BYTE(0-2) READ;
BYTE(1-3) READ;
SINGLE BYTE BLOCK READ 173
2-17: MASTER, SLAVE and LOCATION MONITOR - Data transfer timing
BYTE(0-1) READ;
BYTE(2-3) READ;
BYTE(0-3) READ;
BYTE(1-2) READ;
DOUBLE BYTE BLOCK READ;
QUAD BYTE BLOCK READ 177
2-18: MASTER, SLAVE and LOCATION MONITOR - Data transfer timing
BYTE(0) WRITE;
BYTE(1) WRITE;
BYTE(2) WRITE;
BYTE(3) WRITE;
BYTE(0-2) WRITE;
BYTE(1-3) WRITE;
SINGLE BYTE BLOCK WRITE 181
2-19: MASTER, SLAVE and LOCATION MONITOR - Data transfer timing
BYTE(0-1) WRITE;
BYTE(2-3) WRITE;
BYTE(0-3) WRITE;
BYTE(1-2) WRITE;
DOUBLE BYTE BLOCK WRITE;
QUAD BYTE BLOCK WRITE 185
2-20: MASTER, SLAVE and LOCATION MONITOR - Data transfer timing
Single byte RMW cycle 189
2-21: MASTER, SLAVE and LOCATION MONITOR - Data transfer timing
Double byte RMW cycles
quad byte RMW cycles 191
2-22: Address strobe inter-cycle timing 193
2-23: Data strobe inter-cycle timing
A cycle where both data strobes go low followed by
a cycle where one or both data strobes go low 195
2-24: Data strobe inter-cycle timing
A cycle where one data strobe goes low followed by
a cycle where one or both data strobes go low 197
2-25: MASTER, SLAVE and BUS TIMER - Data transfer timing
Timed-out cycle 199
2-26: MASTER - DTB control transfer timing 201
3-1: Arbitration bus functional block diagram 205
3-2: Illustration of the daisy-chained bus grant lines 209
3-3: Block diagram: ARBITER 219
3-4: Block diagram: REQUESTER 227
3-5: Arbitration flow diagram: two REQUESTERS, two request levels 235
3-6: Arbitration sequence diagram: two REQUESTERS, two request levels 239
3-7: Arbitration flow diagram: two REQUESTERS, same request level 243
3-8: Arbitration sequence diagram:
two REQUESTERS, same request level 247

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—13—
821 © IEC
Figures Page
4-1: Priority Interrupt Bus functional block diagram 253
4-2: Interrupt subsystem structure: single handler system 255
4-3: Interrupt subsystem structure: distributed system 257
4-4: IACKIN*/IACKOUT* DAISY-CHAIN 261
4-5: Block diagram: INTERRUPT HANDLER 265
4-6: Block diagram: INTERRUPTER 273
4-7: Block diagram: IACK DAISY-CHAIN DRIVER 277
4-8: Release of the interrupt request lines by ROAK and RORA INTERRUPTERS 285
4-9: An IACK DAISY-CHAIN DRIVER and an INTERRUPTER on the same board 289
4-10: Two INTERRUPTERS on the same board 291
4-11: The three phases of an interrupt sequence 293
4-12: Two INTERRUPT HANDLERS, each monitoring one interrupt request line 297
4-13: Two INTERRUPT HANDLERS, each monitoring several interrupt request lines 299
4-14: Typical single handler interrupt system operation flow diagram 303
4-15: Typical distributed interrupt system with two INTERRUPT HANDLERS,
flow diagram 309
4-16: INTERRUPT HANDLER and INTERRUPTER - INTERRUPTER selection timing
SINGLE, DOUBLE and QUAD BYTE
INTERRUPT ACKNOWLEDGE CYCLE 343
4-17: IACK DAISY-CHAIN DRIVER - INTERRUPTER selection timing
SINGLE, DOUBLE and QUAD BYTE
INTERRUPT ACKNOWLEDGE CYCLE 345
4-18: Participating INTERRUPTER - INTERRUPTER selection timing
SINGLE, DOUBLE and QUAD BYTE
INTERRUPT ACKNOWLEDGE CYCLE 347
4-19: Responding INTERRUPTER - INTERRUPTER selection timing
SINGLE, DOUBLE and QUAD BYTE
INTERRUPT ACKNOWLEDGE CYCLE 349
4-20: INTERRUPT HANDLER - STATUS/ID transfer timing
SINGLE BYTE INTERRUPT ACKNOWLEDGE CYCLE 351
4-21: INTERRUPT HANDLER - STATUS/ID transfer timing
DOUBLE BYTE INTERRUPT ACKNOWLEDGE CYCLE;
QUAD BYTE INTERRUPT ACKNOWLEDGE CYCLE 353
4-22: Responding INTERRUPTER - STATUS/ID transfer timing
SINGLE BYTE INTERRUPT ACKNOWLEDGE CYCLE 355
4-23: Responding INTERRUPTER - STATUS/ID transfer-timing
DOUBLE BYTE INTERRUPT ACKNOWLEDGE CYCLE;
QUAD BYTE INTERRUPT ACKNOWLEDGE CYCLE 357
4-24:
IACK DAISY-CHAIN DRIVER, responding INTERRUPTER,
and participating INTERRUPTER - IACK daisy-chain inter-cycle timing 359
5-1: Utility Bus block diagram 365
5-2: SYSTEM CLOCK DRIVER timing diagram 367
5-3: Block diagram of POWER MONITOR module 367
5-4: POWER MONITOR power failure timing 369
5-5: POWER MONITOR system restart timing 369
5-6: SYSRESET* and SYSFAIL* timing diagram 375

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821©IEC
Figures Page
5-7: Current rating for power pins 379
6-1: IEC 821 BUS signal levels 385
6-2: Standard bus termination 401
6-3: Backplane microstrip signal line cross section 403
6
-4: Z versus line width 405
0
6-5: Co versus line width 405
7-1: Subrack with mixed board sizes 437
7-2: Single height board: basic dimensions 439
7-3: Double height board: basic dimensions 441
7-4: Connector position on single and double height boards 443
7-5: Cro
ss sectional view of board, connector, backplane, and front panel 445
7-6: Component height, lead length and board warpage 447
7
-7: Single height, single width, front panel 449
7-8: Double height, single width, front panel 451
7-9: Front panel mounting brackets and dimensions of single height board 453
7-10: Front panel mounting brackets and dimensions of double height board 455
7-11: Single height filler panel 457
7-12: Double height filler panel 459
7-13: Overall dimensions of a J 1 and J2 backplane 461
7-14: Detailed dimensions of a J 1 and J2 backplane
463
7-15: Overall dimensions of a J1/J2 backplane 465
7-16: Detailed dimensions of a J1
/J2 backplane 467
7-17: "Off board type" backplane termination
(view from top of backplane) 469
7-18: "On board type" backplane termination
(view from top of backplane) 471
7-19: 21-slot subrack 473
7-20: Board guide detail 475
C-1: SERCLK timing diagram 501
D-1: Basic RS flip-flop 505
D-2: Critical input conditions 507
D-3: The two types of metastability 509
D-4: Different interpretations of a metastable output 511
D-5: VMEbus arbitration structure 527
D-6:
Handling the arbitration daisy-chain asynchronously 529
D-7: Handling the arbitration daisy-chain synchronously 533
D-8: Handling the interrupt daisy-chain asynchronously 537
D-9: Asynchronous VMEbus arbiter 541
Tables
2-1: The four categories of byte location 55
2-2: Use of DSO*, DS1*, A01, and LWORD* to select byte locations 57
2-3: Address modifier codes 59
2-4: Use of the data lines to access byte locations 63
2-5: MASTERS: RULES and PERMISSIONS for driving and monitoring the dotted lines 71
2-6: SLAVES: RULES and PERMISSIONS for driving and monitoring the dotted lines 75

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821 © IEC
Tables Page
2-7: Use of the BTO() mnemonic to specify the time-out period of BUS TIMERS 79
2-8: LOCATION MONITORS: RULES and PERMISSIONS for driving and monitoring
the dotted lines 83
2-9: Mnemonics that specify addressing capabilities 85
2-10: Mnemonics that specify basic data transfer capabilities 93
2-11: Mnemonic that specifies block transfer capabilities 99
2-12: Mnemonic that specifies read-modify-write capabilities 101
2-13: Transferring 32 bits of data using multiple byte transfer cycles 105
2-14: Transferring 16 bits of data using multiple byte transfer cycles 107
2-15: Mnemonic that specifies unaligned transfer capability 107
2-16: Mnemonic that specifies ADDRESS-ONLY capability 109
2-17: Timing diagrams that define MASTER, SLAVE and LOCATION MONITOR operation 133
2-18: Definitions of mnemonics used in Tables 2-19, 2-20 and 2-21 135
2-19: Use of the address lines to select a 4-byte group 137
2-20: Use of DS1*, DSO*, AO1, and LWORD* during the various cycles 139
2-21: Use of the data lines to transfer data 141
2-22: MASTER, SLAVE, and LOCATION MONITOR timing parameters 145
2-23: BUS TIMER timing parameters 145
2-24: MASTER - Timing RULES and OBSERVATIONS 147
2-25: SLAVE - Timing RULES and OBSERVATIONS 155
2-26: LOCATION MONITOR - Timing OBSERVATIONS 161
2-27: BUS TIMER - Timing RULES 163
3-1: ARBITERS: RULES and PERMISSIONS for driving and monitoring the dotted lines 221
3-2: REQUESTERS: RULES and PERMISSIONS for driving and monitoring the dotted lines . 227
4-1: INTERRUPT HANDLERS: RULES and PERMISSIONS for driving and monitoring
the dotted lines 267
4-2: INTERRUPTERS: RULES and PERMISSIONS for driving and monitoring
the dotted lines 275
4-3: Use of the IH() mnemonic to specify interrupt handling capabilities 277
4-4: Use of the I() mnemonic to specify interrupt request generation capabilities 279
4-5: Mnemonics that specify STATUS/ID transfer capabilities 279
4-6: Mnemonics that specify interrupt request release capabilities 285
4-7: 3-bit interrupt acknowledge code 307
4-8: Timing diagrams that define INTERRUPT HANDLER and INTERRUPTER operation 317
4-9: Timing diagrams that define IACK DAISY-CHAIN DRIVER operation 317
4-10: Timing diagrams that define participating INTERRUPTER operation 319
4-11: Timing diagrams that define responding INTERRUPTER operation 319
4-12: Definitions of mnemonics used in Tables 4-13, 4-14
and 4-15 321
4-13: Use of A01-A03 and TACK* during interrupt acknowledge cycles 321

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821 © IEC
Tables Page
4-14: Use of the DS1*, DSO*, LORD*, and WRITE* lines during interrupt
acknowledge cycles 323
4-15: Use of D08-031 to transfer the STATUS/ID 323
4-16: INTERRUPT HANDLER, INTERRUPTER, and IACK DAISY-CHAIN DRIVER timing parameters 325
4-17: INTERRUPT HANDLER - Timing RULES and OBSERVATIONS 327
4-18: INTERRUPTER - Timing RULES and OBSERVATIONS 333
4-19: IACK DAISY-CHAIN DRIVER - Timing RULES and OBSERVATIONS 339
5-1: Module drive during power-up and power-down sequences 373
6-1: Bus voltage specifications 383
6-2: Bus driving and receiving requirements 387
6-3: Bus driver summary 411
7-1: J1/P1 pin assignments 477
7-2: J2/P2 pin assignments 479
C-1: SERCLK timing values 501
D-1: Metastability data 521
E-1: Permissible subsets of adressing capabilities 547
E-2: Interoperability among the permissible adressing subsets 549
E-3: MASTER: Permissible subsets of data transfer capabilities 553
E-4: SLAVE: Permissible subsets of data transfer capabilities 553
E-5:
LOCATION MONITOR: Permissible subsets of data transfer detection
capabilities 555
E-6: Interoperability among the permissible data transfer subsets 555
E-7: Interoperability among ARBITERS and REQUESTERS 557
E-8:
Interoperability of INTERRUPTERS and INTERRUPT HANDLERS 561

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–21 – 821©IEC
(0-1)
INTERNATIONAL ELECTROTECHNICAL COMMISSION
IEC 821 VMEbus -
MICROPROCESSOR SYSTEM BUS FOR 1 BYTE
TO 4 BYTE DATA
FOREWORD
1)
The formal decisions or agreements of the IEC on technical matters, prepared by Technical
Committees on which all the National Committees having a special interest therein are
represented, express, as nearly as possible, an inte rnational consensus of opinion on the
subjects dealt with.
2) They have the form of recommendations for international use and they are accepted by the
National Committees in that sense.
3) In order to promote intern
ational unification, the IEC expresses the wish that all
National Committees should adopt the text of the IEC recommendation for their national
rules in so far as national conditions will permit. Any divergence between the IEC
recommendation and the corresponding national rules should, as far as possible, be clearly
indicated in the latter.
4) The IEC has not laid down any procedure concerning marking as an indication of approval
and has no responsibility when an item of equipment is declared to comply with one of its
recommendations.
This standard has been prepared by Joint Technical Committee ISO/IEC
JTC 1: Information technology, SC 26: Microprocessor systems.
This second edition of IEC 821 replaces the first edition issued in 1987,
and constitutes a technical revision.
The text of this standard is based on the following documents:
DIS Report on Voting
ISO/IEC DIS 821 1/SC 26 N 36
JTC
Full information on the voting for the approval of this standard can be
found in the Voting Report indicated in the above table.

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821 © IEC – 23 –
(0-1)
IEC 821 VMEbus -
MICROPROCESSOR SYSTEM BUS FOR 1 BYTE TO 4 BYTE DATA
CHAPTER 0: INTRODUCTION
0.1 Scope
This standard specifies a high performance backplane bus for use in
microcomputer systems that employ single or multiple microprocessors.
It is based on the VMEbus specification, released by the VME Manu-
facturers Group in August of 1982. The bus includes four sub-buses:
the Data Transfer Bus, the Priority Interrupt Bus, the Arbitration
Bus and the Utility Bus. The Data Transfer Bus supports 8-, 16- and
32-bits transfers over a non-multiplexed 32-bit data and address
highway. The transfer protocols are asynchronous and fully hand-
shaken. The Priority Interrupt Bus provides real-time interrupt
services to the system. The allocation of bus mastership is performed
by the Arbitration Bus, which allows to implement both Round Robin
and Prioritized arbitration algorithms. The Utility bus provides the
system with power-up and power-down synchronization. The mechanical
specifications of boards, backplanes, subracks and enclosures are
based on IEC Publication 297.
0.2 Normative references
The following !EC publications are quoted in this standard:
Publication Nos. 297-1 (1982): Dimensions of mechanical structures of the 482.6 mm (19 in)
series, Part 1: Panels and racks.
297-3 (1984): Subracks and associated plug-in units.
603-2 (1980: Connectors for frequencies below 3 MHz for use with printed
boards, Part 2: Two-part connectors for printed boards for
basic grid of 2.54 mm (0.1 in), with common mounting
features.
822 (1988): IEC 822 VSB - Parallel sub-system bus of the IEC 821
VMEbus.
823 (1990): Microprocessor system bus (VMSbus) - Serial sub-system bus
of the IEC 821 Bus (VMEbus).
0.3 Note to the reader
IEC 822 BUS has been standardized by Sub-Committee 47B as a
sub-system bus of the IEC 821 BUS which constitutes this standard.
IEC 823 BUS represents the bus which has been standardized by
JTC 1/SC 26 as the serial bus of this IEC 821 BUS.

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—25— 821©IEC (1-1)
CHAPTER 1: INTRODUCTION TO THE IEC 821 BUS STANDARD
1 1 /EC
821 BUS standard objectives
This IEC 821 BUS standard defines an interfacing system used to
interconnect data processing, data storage and peripheral control
devices in a closely coupled hardware configuration. The system has
been conceived with the following objectives:
a) To allow communication between devices on the IEC 821 BUS with-
out disturbing the internal activities of other devices interfaced to
the IEC 821 BUS.
b) To specify the electrical and mechanical system characteristics
required to design devices that will reliably and unambiguously
communicate with other devices interfaced to the IEC 821 BUS.
c) To specify protocols that precisely define the interaction between
the IEC 821 BUS and devices interfaced to it.
d) To provide terminology and definitions that describe the system
protocol .
e) To allow a broad range of design latitude so that the designer can
optimize cost and/or performance without affecting system compa-
tibility.
To provide a system where performance is primarily device limited,
f)
rather than system interface limited
1 2 /EC 821 BUS interface system elements
1 2.1 Basic definitions
The IEC 821 BUS structure can be described from two points of
view: its mechanical structure and its functional structure. The
mechanical specification describes the physical dimensions of subracks,
backplanes, front panels, plug-in boards, etc. The IEC 821 BUS
functional specification describes how the bus works, what functional
modules are involved in each transaction, and the rules which govern
their behavior. This paragraph provides informal definitions for some
basic terms used to describe both the physical and the mechanical
structure of the IEC 821 BUS.
1.2.1.1 Terms used to describe the IEC 821 BUS mechanical structure
IEC 821 BUS BACKPLANE
A printed circuit (PC) board with 96-pin connectors and signal paths
that bus the connector pins. Some IEC 821 BUS systems have a single
PC board, called the J 1 backplane. It provides the signal paths needed
for basic operation. Other IEC 821 BUS systems also have an optional
second PC board, called a J2 backplane. It provides the additional
96-pin connectors and signal paths needed for wider data and address
transfers. Still others have .a single PC board, called a J1/J2
backplane, that provides the signal conductors and connectors of both
the J 1 and J 2 backplanes.

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821 © IEC (1-2)
BOARD
A printed circuit (PC) board, its collection of electronic components,
and either one or two 96-pin connectors that can be plugged into IEC
821 BUS backplane connectors.
SLOT
A position where a board can be inserted into an IEC 821 BUS back-
plane. If the IEC 821 BUS system has both a J 1 and a J 2 backplane
(or a combination J 1/J 2 backplane) each slot provides a pair of 96-pin
1 backplane, then each slot
connectors. If the system has only a J
provides a single 96-pin connector.
SUBRACK
A rigid framework that provides mechanical support for boards
inserted into the backplane, ensuring that the connectors mate pro-
perly and that adjacent boards do not contact each other. It also
guides the cooling airflow through the system, and ensures that
inserted boards do not disengage themselves from the backplane due to
vibration or shock.
1.2.1.2 Terms used to describe the IEC 821 BUS functional structure
Figure 1-1, page 37, shows a simplified block diagram of the func-
tional structure, including the IEC 821 BUS signal lines, backplane
interface logic, and functional modules.
BACKPLANE INTERFACE LOGIC
Special logic that takes into account the characteristics of the back-
plane: its signal line impedance, propagation time, termination values,
etc. The IEC 821 BUS standard prescribes certain rules for the design
of this logic based on the maximum length of the backplane and its
maximum number of board slots.
FUNCTIONAL MODULE
A collection of electronic circuitry that resides on one IEC 821 BUS
board and works together to accomplish a task.
DATA TRANSFER BUS
One of the four buses provided by the IEC 821 BUS backplane. The
Data Transfer Bus allows MASTERS to direct the transfer of binary
data between themselves and SLAVES. (Data Transfer Bus is often
abbreviated DTB.)
DATA TRANSFER BUS CYCLE
A sequence of level transitions on the signal lines of the DTB that
result in the transfer of an address or an address and data between a
MASTER and a SLAVE. The Data Transfer Bus cycle is divided into
two portions, the address broadcast and then zero or more data trans-
fers. There are 34 types of Data Transfer Bus cycles. They are
defined later in this chapter.
MASTER
A functional module that initiates DTB cycles in order to transfer
data between itself and a SLAVE module.

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SLAVE
A functional module that detects DTB cycles initiated by a MASTER
and, when those cycles specify its participation, transfers data be-
tween itself and the MASTER.
LOCATION MONITOR
A functional module that monitors data transfers over the DTB in
order to detect accesses to the locations it has been assigned to
watch. When an access to one of these assigned locations occurs, the
LOCATION MONITOR generates an on-board signal.
BUS TIMER
A functional module that measures how long each data transfer takes
on the DTB and terminates the DTB cycle if a transfer takes too long.
Without this module, if the MASTER tries to transfer data to or from a
non-existent SLAVE location it might wait forever. The BUS TIMER
prevents this by terminating the cycle.
PRIORITY INTERRUPT BUS
One of the four buses provided by the IEC 821 BUS backplane. The
Priority Interrupt Bus allows INTERRUPTER modules to send interrupt
requests to INTERRUPT HANDLER modules.
INTERRUPTER
A functional module that generates an interrupt request on the
Priority Interrupt Bus and then provides STATUS/ID information when
the INTERRUPT HANDLER requests it.
INTERRUPT HANDLER
A functional module that detects interrupt requests generated by
INTERRUPTE
...