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CLC

CLC/SR 93 - Design automation

Design automation

General Information

Status
Inactive
Sector
V30 - DESIGN AUTOMATION
Parent
CLC - CLC TC
Standardization Organization
ICS
Directive
Mandate
50
CLC
EN 61691-1:1997(Main)
Design automation - Part 1: VHDL language reference manual
SIST EN 61691-1:2002

This standard is based on IEEE Std 1076. It describes the Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL)

  • Standard
    254 pages
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CLC
EN 61523-2:2002(Main)
Delay and power calculation standards - Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries
SIST EN 61523-2:2004

Applies to CMOS ASIC libraries which contain cell based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification and logic synthesis.The delay calculation method addressed in this standard consists of 1) estimation of wire capacitance 2 ) Delay calculation method based on tablelook-up. With use of DCL and SDF, this delay calculation method helps the user have a unified timing model for various EDA tools in the pre-layout design phase.

  • Standard
    41 pages
    English language
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CLC
ES 59011:2001(Main)
Specification for the representation of Quality rules and metrics for Hardware and Software Design Languages
SIST ES 59011:2004

D116/196: TC 217 disbanded * D124/C049: Withdrawn

  • Standardization document
    18 pages
    English language
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CLC
ENV 50247-1:1998(Main)
Pinnacles Component Information Standard 1.2 - The PCIS tag library
SIST ENV 50247-1:2002

Document jointly prepared by the Pinnacles Group and TC 217 * D116/196: TC 217 disbanded * D124/C049: Withdrawn

  • Standardization document
    417 pages
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ENV 50247-2:1998(Main)
Pinnacles Component Information Standard 1.2 - The SGML declaration and SGML Document Type Definitions (DTDs)
SIST ENV 50247-2:2004

Document jointly prepared by the Pinnacles Group and TC 217 * D116/196: TC 217 disbanded * D124/C049: Withdrawn

  • Standardization document
    60 pages
    English language
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ENV 50218:1996(Main)
Description of a parametrized European mini test chip
SIST ENV 50218:2002

D116/196: TC 217 disbanded * D124/C049: Withdrawn

  • Standardization document
    19 pages
    English language
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ENV 50219:1996(Main)
Description of the reliability test structures of the European mini test chip
SIST ENV 50219:2002

D116/196: TC 217 disbanded * D124/C049: Withdrawn

  • Standardization document
    35 pages
    English language
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CLC
R217-020:2001(Main)
Electronic system specification languages - VHDL modelling guidelines
SIST-TP CLC/R217-020:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    47 pages
    English language
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R217-015:1999(Main)
Pinnacles Component Information Standard 1.2 - PCIS Tutorial
SIST-TP CLC/R217-015:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    66 pages
    English language
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R217-016:1999(Main)
Pinnacles Component Information Standard 1.2 - PCIS Sample Documents
SIST-TP CLC/R217-016:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    84 pages
    English language
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CLC
R217-018:1997(Main)
Report on the Viability of EDIF PCB Version (3 5 0)
SIST-TP CLC/R217-018:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    19 pages
    English language
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CLC
R217-017:1997(Main)
Evaluation techniques of the reliability test structures of the European mini test chip
SIST-TP CLC/R217-017:2004

Based on JESSI document * D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    22 pages
    English language
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R217-013:1997(Main)
Interchange formats - Evaluation of EDIF Version 3 0 0 level 0
SIST-TP CLC/R217-013:2004

Based on ESIP document * D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    18 pages
    English language
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R217-012:1996(Main)
Electronic system specification languages - VHDL 93 information core model
SIST-TP CLC/R217-012:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    270 pages
    English language
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CLC
R217-011:1996(Main)
Electronic system specification language - Express information model VHDL 87
SIST-TP CLC/R217-011:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    292 pages
    English language
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CLC
R217-014:1996(Main)
EDA framework - Task and session information model
SIST-TP CLC/R217-014:2004

Previous prENV 50224 * D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    21 pages
    English language
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CLC
R217-010:1996(Main)
Measurement techniques of the reliability test structures of the European mini test chip
SIST-TP CLC/R217-010:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    43 pages
    English language
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CLC
R217-001:1996(Main)
Basic information on submicron CMOS technology assessment flow
SIST-TP CLC/R217-001:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    8 pages
    English language
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R217-008:1995(Main)
Language requirements for high-level synthesis
SIST-TP CLC/R217-008:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    2 pages
    English language
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CLC
R217-002:1995(Main)
Comparison of different information modelling approaches and styles
SIST-TP CLC/R217-002:2004

Based on ECIP document * D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    2 pages
    English language
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R217-003:1995(Main)
Validation of EXPRESS models
SIST-TP CLC/R217-003:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    2 pages
    English language
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R217-007:1995(Main)
Recommendations on necessary concepts to model behavioural semantics
SIST-TP CLC/R217-007:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    2 pages
    English language
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CLC
R217-005:1995(Main)
Measurement techniques for the characterization of the European mini test chip
SIST-TP CLC/R217-005:2004

Based on JESSI document * D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    2 pages
    English language
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CLC
R217-004:1995(Main)
JESSI 0.8µm CMOS transistor model for analogue and digital circuit simulation
SIST-TP CLC/R217-004:2004

D116/196: TC 217 disbanded * D122/065: Withdrawn

  • Technical report
    2 pages
    English language
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CLC
EN 61691-3-2:2001(Main)
Behavioural languages - Part 3-2: Mathematical operation in VHDL
SIST EN 61691-3-2:2007

This set of packages provides a standard for the declaration of most frequently used real and complex elementary functions required for numerically oriented modeling applications. Use of these packages with their defined data types, constants, and functions is intended to provide a mechanism for writing VHDL models (compliant with IEEE Std 1076-1993) that are portable and interoperable with other VHDL models adhering to this standard. The standard serves a broad class of applications with reasonable ease of use and requires implementations that are of high quality. This standard includes package bodies, as described in annex B, which are available in electronic format either on a diskette affixed to the back cover, or as a downloadable file from the IEC Web Store.

  • Standard
    42 pages
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ENV 50208-6:1997(Main)
Data Interchange format for Simulated and Measured Data (ISMD)
SIST ENV 50208-6:2002

D116/196: TC 217 disbanded * D124/C049: Withdrawn

  • Standardization document
    20 pages
    English language
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50