prEN IEC 62228-6:2022

Integrated circuit - EMC Evaluation of transceivers - Part 6: PSI5 transceivers

This document specifies test and measurement methods for EMC evaluation of Peripheral Sensor Interface 5 (PSI5) transceiver integrated circuits (ICs) under network condition. It defines test configurations, test conditions, test signals, failure criteria, test procedures, test setups and test boards. It is applicable for PSI5 satellite ICs (e.g. sensors) and ICs with embedded PSI5 transceivers (e.g. PSI5 Electronic control unit IC). The document covers - the emission of RF disturbances, - the immunity against RF disturbances, - the immunity against impulses and - the immunity against electrostatic discharges (ESD).

Circuits intégrés - Évaluation de la CEM des émetteurs-récepteurs - Partie 6: Émetteurs-récepteurs PSI5

Integrirana vezja - Vrednotenje elektromagnetne združljivosti (EMC) oddajnikov-sprejemnikov - 6. del: Oddajniki-sprejemniki PSI5

General Information

• Status: Not Published
• ICS: 31.200 - Integrated circuits. Microelectronics
• Technical Committee: CLC/SR 47A - Integrated circuits
• Drafting Committee: IEC/SC 47A - IEC_SC_47A
• Current Stage: 4020 - Enquiry circulated
• Due Date: 18-Mar-2022
• Completion Date: 18-Mar-2022
• Ref Project: oSIST prEN IEC 62228-6:2022 - Integrated circuit - EMC Evaluation of transceivers - Part 6: PSI5 transceivers

Standards Content (sample)

SLOVENSKI STANDARD
oSIST prEN IEC 62228-6:2022
01-maj-2022
Integrirana vezja - Vrednotenje elektromagnetne združljivosti (EMC) oddajnikov-
sprejemnikov - 6. del: Oddajniki-sprejemniki PSI5
Integrated circuit - EMC Evaluation of transceivers - Part 6: PSI5 transceivers

Circuits intégrés - Évaluation de la CEM des émetteurs-récepteurs - Partie 6: Émetteurs-

récepteurs PSI5
Ta slovenski standard je istoveten z: prEN IEC 62228-6:2022
ICS:
31.200 Integrirana vezja, Integrated circuits.
mikroelektronika Microelectronics
33.100.01 Elektromagnetna združljivost Electromagnetic compatibility
na splošno in general
oSIST prEN IEC 62228-6:2022 en

2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

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oSIST prEN IEC 62228-6:2022
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oSIST prEN IEC 62228-6:2022
47A/1132/CDV
COMMITTEE DRAFT FOR VOTE (CDV)
PROJECT NUMBER:
IEC 62228-6 ED1
DATE OF CIRCULATION: CLOSING DATE FOR VOTING:
2022-03-18 2022-06-10
SUPERSEDES DOCUMENTS:
47A/1123/CD, 47A/1125A/CC
IEC SC 47A : INTEGRATED CIRCUITS
SECRETARIAT: SECRETARY:
Japan Mr Yoshinori FUKUBA
OF INTEREST TO THE FOLLOWING COMMITTEES: PROPOSED HORIZONTAL STANDARD:
Other TC/SCs are requested to indicate their interest, if any,
in this CDV to the secretary.
FUNCTIONS CONCERNED:
EMC ENVIRONMENT QUALITY ASSURANCE SAFETY

SUBMITTED FOR CENELEC PARALLEL VOTING NOT SUBMITTED FOR CENELEC PARALLEL VOTING

Attention IEC-CENELEC parallel voting
The attention of IEC National Committees, members of
CENELEC, is drawn to the fact that this Committee Draft for
Vote (CDV) is submitted for parallel voting.
The CENELEC members are invited to vote through the
CENELEC online voting system.

This document is still under study and subject to change. It should not be used for reference purposes.

Recipients of this document are invited to submit, with their comments, notification of any relevant patent rights of which

they are aware and to provide supporting documentation.
TITLE:
Integrated circuit – EMC Evaluation of transceivers – Part 6: PSI5 transceivers
PROPOSED STABILITY DATE: 2027
NOTE FROM TC/SC OFFICERS:

The comments for 47A/1123/CD were reviewed in SC 47A WG 9 meeting which was held on 2021-10-01 and

2021-12-01 and all technical issues were resolved and addressed in 47A/1125A/CC, so the project will move

forward as CDV.

Copyright © 2022 International Electrotechnical Commission, IEC. All rights reserved. It is permitted to download this

electronic file, to make a copy and to print out the content for the sole purpose of preparing National Committee positions.

You may not copy or "mirror" the file or printed version of the document, or any part of it, for any other purpose without

permission in writing from IEC.
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oSIST prEN IEC 62228-6:2022
IEC CDV 62228-6 © IEC (E) – 2 – 47A/1132/CDV
1 CONTENTS

3 FOREWORD ........................................................................................................................... 5

4 INTRODUCTION ..................................................................................................................... 7

5 1 Scope .............................................................................................................................. 8

6 2 Normative references ...................................................................................................... 8

7 3 Terms and definitions ...................................................................................................... 8

8 4 General ........................................................................................................................... 9

9 5 Test and operating conditions ........................................................................................ 11

10 5.1 Supply and ambient conditions ............................................................................. 11

11 5.2 Test operation modes ........................................................................................... 12

12 5.3 Test configuration ................................................................................................. 13

13 5.3.1 General test configuration for functional test .................................................. 13

14 5.3.2 General test configuration for unpowered ESD test ........................................ 14

15 5.3.3 Coupling ports for functional tests .................................................................. 15

16 5.3.4 Coupling ports for unpowered ESD tests........................................................ 16

17 5.4 Test signals .......................................................................................................... 17

18 5.4.1 General ......................................................................................................... 17

19 5.4.2 Test signals for asynchronous mode .............................................................. 17

20 5.4.3 Test signal for Synchronous parallel bus mode .............................................. 19

21 5.5 Evaluation criteria ................................................................................................. 19

22 5.5.1 General ......................................................................................................... 19

23 5.5.2 Evaluation criteria in functional operation modes during exposure to

24 disturbances .................................................................................................. 20

25 5.5.3 Evaluation criteria in unpowered condition after exposure to

26 disturbances .................................................................................................. 20

27 6 Test and measurement .................................................................................................. 21

28 6.1 Emission of RF disturbances ................................................................................. 21

29 6.1.1 Test method .................................................................................................. 21

30 6.1.2 Test setup ..................................................................................................... 21

31 6.1.3 Test procedure and parameters ..................................................................... 22

32 6.2 Immunity to RF disturbances ................................................................................. 23

33 6.2.1 Test method .................................................................................................. 23

34 6.2.2 Test setup ..................................................................................................... 23

35 6.2.3 Test procedure and parameters ..................................................................... 24

36 6.3 Immunity to impulses ............................................................................................ 25

37 6.3.1 Test method .................................................................................................. 25

38 6.3.2 Test setup ..................................................................................................... 25

39 6.3.3 Test procedure and parameters ..................................................................... 27

40 6.4 Electrostatic Discharge (ESD) ............................................................................... 28

41 6.4.1 Test method .................................................................................................. 28

42 6.4.2 Test setup ..................................................................................................... 28

43 6.4.3 Test procedure and parameters ..................................................................... 30

44 7 Test report ..................................................................................................................... 31

45 Annex A (normative) PSI5 test circuits ................................................................................. 32

46 A.1 General ................................................................................................................. 32

47 A.2 Test circuit for emission and immunity tests on a PSI5 ECU IC ............................. 32

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48 A.3 Test circuit for emission and immunity tests on a PSI5 Satellite IC ........................ 34

49 A.4 Test circuit for an unpowered ESD test on a PSI5 IC ............................................ 35

50 Annex B (normative) Test circuit boards .............................................................................. 37

51 B.1 Test circuit board for emissions and immunity tests .............................................. 37

52 B.2 ESD test ............................................................................................................... 37

53 Annex C (informative) Examples of test limits for PSI5 transceiver in automotive

54 applications ................................................................................................................... 38

55 C.1 General ................................................................................................................. 38

56 C.2 Emission of RF disturbances ................................................................................. 38

57 C.3 Immunity to RF disturbances ................................................................................. 39

58 C.4 Immunity to Impulses ............................................................................................ 41

59 C.5 ESD ...................................................................................................................... 41

60 Bibliography .......................................................................................................................... 42

62 Figure 1 – PSI5 system overview ............................................................................................ 9

63 Figure 2 – Example PSI5 wiring diagram with a single sensor and equivalent model ............. 10

64 Figure 3 – PSI5-A configuration with a single sensor connection with two wires .................... 12

65 Figure 4 – PSI5-P configuration with two sensor connection ................................................. 13

66 Figure 5 – General test configuration for tests in functional operation modes ........................ 14

67 Figure 6 – General test configuration for unpowered ESD test of an ECU IC ......................... 14

68 Figure 7 – General test configuration for unpowered ESD test of a Satellite IC ..................... 15

69 Figure 8 – Coupling ports for transceiver emission and immunity tests .................................. 15

70 Figure 9 – Coupling ports for unpowered ESD tests .............................................................. 16

71 Figure 10 – Example drawing of the maximum deviation on an I-V characteristic .................. 21

72 Figure 11 – Test setup for measurement of RF disturbances ................................................ 22

73 Figure 12 – Test setup for DPI tests ...................................................................................... 23

74 Figure 13 – Test setup for impulse immunity tests ................................................................ 26

75 Figure 14 – Test setup for direct ESD tests ........................................................................... 29

76 Figure A.1 General circuit diagram of the PSI5 test network for emissions and

77 immunity tests on ECU IC ..................................................................................................... 34

78 Figure A.2 General circuit diagram of the PSI5 test network for emissions and

79 immunity tests on Satellite IC ................................................................................................ 35

80 Figure A.3 General circuit diagram of the PSI5 ECU IC for testing of direct ESD in

81 unpowered mode .................................................................................................................. 35

82 Figure A.1 General circuit diagram of the PSI5 Sensor IC for testing of direct ESD in

83 unpowered mode .................................................................................................................. 35

84 Figure C.1 – Example of limits for RF emission – PSI5 with ECU filter .................................. 38

85 Figure C.2 – Example of limits for RF emission – Other global pins ...................................... 39

86 Figure C.3 –Example of limits for RF immunity for functional status class A ...................... 40

87 Figure C.4 –Example of limits for RF immunity for functional status class C or D ........... 40

IC IC

89 Table 1 – PSI5 Physical layer electrical characteristics ......................................................... 10

90 Table 2 – Overview of required measurements and tests ...................................................... 11

91 Table 3 –Supply and ambient conditions for functional operation .......................................... 12

92 Table 4 – Sensor sink current specification ........................................................................... 13

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93 Table 5 – Definitions for component values of coupling ports for transceiver emission

94 and immunity tests ................................................................................................................ 15

95 Table 6 – Definitions of coupling ports for unpowered ESD tests ........................................... 17

96 Table 7 – Communication test signal TX1 for Asynchronous mode (125 kbps) ...................... 17

97 Table 8 – Communication test signal TX2 for Asynchronous mode (189 kbps) ...................... 18

98 Table 9 – Communication test signal TX3 for Asynchronous Low-power mode ...................... 18

99 Table 10 – Communication test signal TX4 for Synchronous parallel bus mode .................... 19

100 Table 11 – Communication test signal TX5 for Synchronous parallel bus mode .................... 19

101 Table 12 – Evaluation criteria for standalone and embedded PSI5 transceiver IC in

102 functional operation modes ................................................................................................... 19

103 Table 13 – Parameters for emission measurements .............................................................. 22

104 Table 14 – Settings of the RF measurement equipment ........................................................ 22

105 Table 15 – Specifications for DPI tests ................................................................................. 24

106 Table 16 – Required DPI tests for functional status class A evaluation of Standard

107 PSI5 transceiver ICs and embedded PSI5 transceiver ICs .................................................... 25

108 Table 17 – Required DPI tests for functional status class C or D evaluation of

IC IC

109 Standard PSI5 transceiver ICs and ICs with embedded PSI5 transceiver .............................. 25

110 Table 18 – Specifications for impulse immunity tests ............................................................ 27

111 Table 19 - Parameters for impulse immunity test................................................................... 27

112 Table 20 – Required impulse immunity tests for functional status class A evaluation

113 of Standard and embedded PSI5 transceiver ICs .................................................................. 28

114 Table 21 – Required impulse immunity tests for functional status class C or D

IC IC

115 evaluation of Standard PSI5 transceiver ICs and ICs with embedded PSI transceiver ........... 28

116 Table 22 – Specifications for direct ESD tests ....................................................................... 30

117 Table B.1 – Parameter ESD test circuit board ....................................................................... 37

118 Table C.1 – Example of limits for impulse immunity for functional status class C or

119 D ...................................................................................................................................... 40

120
121
122
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oSIST prEN IEC 62228-6:2022
IEC CDV 62228-6 © IEC (E) – 5 – 47A/1132/CDV
123
124 INTERNATIONAL ELECTROTECHNICAL COMMISSION
125 ____________
126
127 INTEGRATED CIRCUIT – EMC EVALUATION OF TRANSCEIVERS
128
129 Part 6: PSI5 transceivers
130
131
132 FOREWORD

133 1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising

134 all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international

135 co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and

136 in addition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports,

137 Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC Publication(s)”). Their

138 preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with

139 may participate in this preparatory work. International, governmental and non-governmental organizations liaising

140 with the IEC also participate in this preparation. IEC collaborates closely with the International Organization for

141 Standardization (ISO) in accordance with conditions determined by agreement between the two organizations.

142 2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international

143 consensus of opinion on the relevant subjects since each technical committee has representation from all

144 interested IEC National Committees.

145 3) IEC Publications have the form of recommendations for international use and are accepted by IEC National

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147 Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any

148 misinterpretation by any end user.

149 4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications

150 transparently to the maximum extent possible in their national and regional publications. Any divergence between

151 any IEC Publication and the corresponding national or regional publication shall be clearly indicated in the latter.

152 5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity

153 assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any

154 services carried out by independent certification bodies.

155 6) All users should ensure that they have the latest edition of this publication.

156 7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and

157 members of its technical committees and IEC National Committees for any personal injury, property damage or

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159 expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC

160 Publications.

161 8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is

162 indispensable for the correct application of this publication.

163 9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent

164 rights. IEC shall not be held responsible for identifying any or all such patent rights.

165 IEC 62228-6 has been prepared by subcommittee 47A: Integrated circuit, of IEC technical

166 committee 47: Semiconductor Device. It is an International Standard.
167 The text of this International Standard is based on the following documents:
Draft Report on voting
47A/XX/CD 47A/XX/RVD
168

169 Full information on the voting for its approval can be found in the report on voting indicated in

170 the above table.

171 The language used for the development of this International Standard is English.

172 This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in

173 accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available

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IEC CDV 62228-6 © IEC (E) – 6 – 47A/1132/CDV

174 at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are

175 described in greater detail at www.iec.ch/standardsdev/publications.

176 The committee has decided that the contents of this document will remain unchanged until the

177 stability date indicated on the IEC website under webstore.iec.ch in the data related to the

178 specific document. At this date, the document will be
179 • reconfirmed,
180 • withdrawn,
181 • replaced by a revised edition, or
182 • amended.
183
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184 INTRODUCTION

185 The International Electrotechnical Commission (IEC) draws attention to the fact that it is claimed

186 that compliance with this document may involve the use of a patent. IEC takes no position

187 concerning the evidence, validity, and scope of this patent right.

188 The holder of this patent right has assured IEC that s/he is willing to negotiate licences under

189 reasonable and non-discriminatory terms and conditions with applicants throughout the world.

190 In this respect, the statement of the holder of this patent right is registered with IEC. Information

191 may be obtained from the patent database available at patents.iec.ch/.

192 Attention is drawn to the possibility that some of the elements of this document may be the

193 subject of patent rights other than those in the patent database. IEC shall not be held

194 responsible for identifying any or all such patent rights.
195
196
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197 INTEGRATED CIRCUITS –
198 EMC EVALUATION OF TRANSCEIVERS
199
200 Part 6: PSI5 transceivers
201
202
203
204 1 Scope

205 This document specifies test and measurement methods for EMC evaluation of Peripheral

206 Sensor Interface 5 (PSI5) transceiver integrated circuits (ICs) under network condition. It

207 defines test configurations, test conditions, test signals, failure criteria, test procedures, test

208 setups and test boards. It is applicable for PSI5 satellite ICs (e.g. sensors) and ICs with

209 embedded PSI5 transceivers (e.g. PSI5 Electronic control unit IC). The document covers

210 • the emission of RF disturbances,
211 • the immunity against RF disturbances,
212 • the immunity against impulses and
213 • the immunity against electrostatic discharges (ESD).
214 2 Normative references

215 The following documents are referred to in the text in such a way that some or all of their content

216 constitutes requirements of this document. For dated references, only the edition cited applies.

217 For undated references, the latest edition of the referenced document (including any

218 amendments) applies.

219 IEC 61967-1, Integrated circuits − Measurement of electromagnetic emissions – Part 1:

220 General conditions and definitions

221 IEC 61967-4, Integrated circuits − Measurement of electromagnetic emissions – Part 4:

222 Measurement of conducted emissions – 1 Ω /150 Ω direct coupling method

223 IEC 62132-1, Integrated circuits − Measurement of electromagnetic immunity – Part 1: General

224 and definitions

225 IEC 62132-4, Integrated circuits − Measurement of electromagnetic immunity 150 kHz to 1 GHz

226 – Part 4: Direct RF Power Injection Method

227 IEC 62215-3, Integrated circuits – Measurement of impulse immunity - Part 3: Non-synchronous

228 transient injection method

229 IEC 62228-1, Integrated circuits – EMC evaluation of transceivers – Part 1: General conditions and

230 definitions

231 ISO 7637-2, Road vehicles, electrical disturbances by conduction and coupling – Part 2: Electrical

232 transients along supply lines only

233 ISO 10605, Road vehicles - Test methods for electrical disturbances from electrostatic

234 discharge
235 3 Terms and definitions

236 For the purposes of this document, the following terms and definitions apply.

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237 ISO and IEC maintain terminological databases for use in standardization at the following

238 addresses:
239 • IEC Electropedia: available at https://www.electropedia.org/
240 • ISO Online browsing platform: available at https://www.iso.org/obp
241 3.1
242 global pin

243 carries a signal or power, which enters or leaves the application board without any active

244 component in between
245 3.2
246 mandatory components, pl

247 components needed for proper function and/or technical requirements of IC as specified by the

248 IC manufacturer
249 3.3
250 PSI5 satellite IC (sensor device)
251 PSI5 satellite or sensor transceiver with access to PSI5 signal
252 3.4
253 IC with embedded PSI5 transceiver (ECU device)

254 IC with integrated PSI5 transceiver cell and PSI5 protocol handler with access to PSI5 signal

255
256
257 4 General

258 The intention of this document is to evaluate the EMC performance of PSI5 transceiver ICs

259 under application in minimal operating conditions (or in a minimal network). PSI5 transceiver

260 ICs are in general available in two types as PSI5 satellite IC and as IC with embedded PSI5

261 transceiver.
262 PSI5 transceiver system overview is shown in Figure 1.
(A)
(B)
2 4 3
6 6
(C)
6 6 6
263
Key
1 Electronic Control Unit (ECU) 6 PSI5 Sensor ICs
2 Microcontroller (A) Point-to-Point topology
3 IC with embedded PSI5 (B) Daisy-chain topology
4 Digital interface (C) Bus topology
5 Two wire current interface (PSI5)
264 Figure 1 – PSI5 system overview
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265 The sensors are connected to the ECU with two wires, using the same lines for power supply

266 and data transmission. The IC with embedded PSI5 (e.g. transceiver ASIC in the ECU) provides

267 a pre-regulated voltage to the sensors and reads in the transmitted sensor data.

268 The physical layer of PSI5 for EMC evaluation shall have the following characteristics, as shown

269 in Table 1 [1].
270 Table 1 – PSI5 Physical layer electrical characteristics
No. Parameter Variable Minimum Typical Maximum Unit
1 Supply Voltage V , V 4 16,5 V
SSmax CEmax
2 Reverse polarity t < 80 ms -105 mA
protection (standard)
3 Reverse polarity t < 50 ms -130 mA
protection
(extended)
4 Internal ECU R 9 10 Ω
resistance
5 PSI5 ECU Filter C 9 10 11 nF
capacitor
6 PSI5 ECU Filter R 2 2,2 2,5 Ω
resistor
7 PSI5 ECU Filter C 9 10 11 nF
capacitor

Symmetrical values for C and C are proposed to have a balanced filter on PSI5.

E L

271 An example of the typical PSI5 network, with a single sensor and the equivalent model, is shown

272 in Figure 2. Most implementations will have a mandatory PSI5 ECU filter (PSI5 bus filter) used

273 on the ECU side as shown in Figure 2. Sensor side may also have additional filter components

274 as per the IC manufacturer specifications.
2 3
I I
E S
- C C
E L
275
Key
1 PSI5 ECU IC
2 PSI5 ECU Filter (PSI5 bus filter)
3 Two-wire PSI5 interface
4 PSI5 Satellite IC / Sensor

276 Figure 2 – Example PSI5 wiring diagram with a single sensor and equivalent model

277 The evaluation of the EMC characteristics of PSI5 transceivers shall be performed in functional

278 operation modes for RF emission, RF immunity and impulse immunity tests and on a single

279 unpowered transceiver IC for electrostatic discharge tests.
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280 The approach of these tests is to determine the EMC performance on dedicated global pins of

281 the PSI5 transceiver which are considered as EMC relevant in the application. For a PSI5

282 satellite IC or for an embedded PSI5 transceiver IC these pins are at least PSI+ (PSI_DATA),

283 PSI- (PSI_GND) and V , if available.
BAT

284 The test methods used for the EMC characterization are based on the international standards

285 for IC EMC tests and are described in Table 2.
286 Table 2 – Overview of required measurements and tests
Transceiver Required Test method Evaluation Functional
mode test operation
mode
Asynchronous
150 Ω direct coupling
RF emission Spectrum
(IEC 61967-4)
Synchronous
Synchronous
DPI
RF immunity Function
Functional
Asynchronous
(IEC 62132-4)
(powered)
Low-power
Synchronous
Non-synchronous transient
Impulse
injection Function
Asynchrono
...