IEC TS 62804-1:2015

Photovoltaic (PV) modules - Test methods for the detection of potential-induced degradation - Part 1: Crystalline silicon

IEC TS 62804-1:2015(E) defines procedures to test and evaluate the durability of crystalline silicon photovoltaic (PV) modules to the effects of short-term high-voltage stress including potential-induced degradation (PID). Two test methods are defined that do not inherently produce equivalent results. They are given as screening tests; neither test includes all the factors existing in the natural environment that can affect the PID rate. The methods describe how to achieve a constant stress level. The testing in this Technical Specification is designed for crystalline silicon PV modules with one or two glass surfaces, silicon cells having passivating dielectric layers, for degradation mechanisms involving mobile ions influencing the electric field over the silicon semiconductor, or electronically interacting with the silicon semiconductor itself.

General Information

• Status: Published
• Publication Date: 05-Aug-2015
• ICS: 01 - GENERALITIES. TERMINOLOGY. STANDARDIZATION. DOCUMENTATION
• ICS: 27.160 - Solar energy engineering
• Technical Committee: TC 82 - Solar photovoltaic energy systems
• Drafting Committee: WG 2 - TC 82/WG 2
• Current Stage: PPUB - Publication issued
• Start Date: 30-Nov-2015
• Completion Date: 06-Aug-2015

Standards Content (Sample)

IEC TS 62804-1 ®
Edition 1.0 2015-08
TECHNICAL
SPECIFICATION
colour
inside
Photovoltaic (PV) modules – Test methods for the detection of potential-induced
degradation –
Part 1: Crystalline silicon
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IEC TS 62804-1 ®
Edition 1.0 2015-08
TECHNICAL
SPECIFICATION
colour
inside
Photovoltaic (PV) modules – Test methods for the detection of potential-induced

degradation –
Part 1: Crystalline silicon
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 27.160 ISBN 978-2-8322-2835-7

– 2 – IEC TS 62804-1:2015 © IEC 2015
CONTENTS
FOREWORD . 3
INTRODUCTION . 5
1 Scope . 6
2 Normative references . 6
3 Samples . 7
4 Test procedures . 8
4.1 General . 8
4.2 Pre-stress tests . 9
4.3 Voltage stress test procedures . 9
4.3.1 Apparatus . 9
4.3.2 Stress method a), testing in damp heat using an environmental chamber . 10
4.3.3 Stress method b), contacting the surfaces with a conductive electrode . 12
4.4 Post-stress tests . 13
5 Test report . 14

Figure 1 – PID test flow . 8
Figure 2 – Example test time-temperature-humidity-voltage profile for application of
stress in an environmental chamber . 12
Figure 3 – Test time-temperature-voltage profile for stress method performed in 25 °C
ambient. 13

INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
PHOTOVOLTAIC (PV) MODULES –
TEST METHODS FOR THE DETECTION
OF POTENTIAL-INDUCED DEGRADATION –

Part 1: Crystalline silicon
FOREWORD
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Technical specifications are subject to review within three years of publication to decide
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IEC TS 62804-1, which is a technical specification, has been prepared by IEC technical
committee 82: Solar photovoltaic energy systems.

– 4 – IEC TS 62804-1:2015 © IEC 2015
The text of this standard is based on the following documents:
DTS Report on voting
82/885/DTS 82/921A/RVC
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all parts in the IEC 62804 series, published under the general title Photovoltaic (PV)
modules – Test methods for the detection of potential-induced degradation, can be found on
the IEC website.
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INTRODUCTION
This part of IEC 62804 is for testing and evaluating the durability of crystalline silicon
photovoltaic modules to stresses that induce potential-induced degradation (PID). The applied
stresses, mainly system voltage, manifest themselves in different degradation mechanisms
depending on the module technology. A series of Technical Specifications is therefore
proposed to define PID tests for different photovoltaic module technologies.
IEC TS 62804-1 defines test methods for evaluating PID in crystalline silicon PV modules.
IEC TS 62804-2 defines test methods for evaluating PID in thin-film PV modules.
Additional Technical Specifications in the series may be introduced in the future for emerging
module technologies.
Voltage potential that exists between the active circuit and the grounded module surfaces can
lead to module degradation by multiple mechanisms including ionic transport in the
encapsulant, superstrate or substrate; hot carriers in the cell; redistribution of charges that
degrade the active layer of the cell or its surfaces; failure of adhesion at interfaces, and
corrosion of module components. These degradation mechanisms in crystalline silicon
photovoltaic modules caused by voltage stress and promoted by high temperature and
humidity have been labeled potential-induced degradation, polarization, electrolytic corrosion,
and electrochemical corrosion. They are most active in wet or damp environments, and in
environments prone to soiling of modules with conductive, acidic, caustic, or ionic species
that lead to increased conduction on the module surfaces. In the field, modules have been
observed to degrade in positive as well as negative polarity strings depending on the cell
construction, module materials, and design. The testing in this Technical Specification
therefore specifies the evaluation of the effects of voltage stress in both polarities for modules
that may be operated in either polarity, or in the polarity defined by the manufacturer’s
documented specifications. Some crystalline silicon module designs undergoing system
voltage bias stress have shown degradation manifested by junction failure, leading to changes
in the reverse-bias breakdown characteristics and a resulting degradation in safety because
of the increased potential for development of hot spots in the module. This Technical
Specification describes two methods to measure the ability of a module to withstand
degradation from system voltage effects that manifest in the relatively short term.
The stress-test levels in this Technical Specification have not been related to those of the
natural environment. Modules types undergoing damp heat chamber testing with a 60 °C and
85 % relative humidity stress level with the temperature, humidity, and bias voltage ramped
simultaneously at the start of a 96 h stress test were found resistant to PID in outdoor tests in
Florida, USA. However, to improve reproducibility, test details including environmental
chamber temperature and humidity ramps and tolerances have been tightened, which very
significantly reduce the total stress applied and invalidate t
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