IEC 62530-2:2021

SystemVerilog - Part 2: Universal Verification Methodology Language Reference Manual

IEC 62530-2:2021(E) establishes the Universal Verification Methodology (UVM), a set of application programming
interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™. This publication has the status of a double logo IEC/IEEE standard.

General Information

• Status: Published
• Publication Date: 25-Jul-2021
• ICS: 25.040.01 - Industrial automation systems in general
• ICS: 35.060 - Languages used in information technology
• Technical Committee: TC 91 - Electronics assembly technology

Relations

• Revised: IEC 62530-2:2023 - SystemVerilog - Part 2: Universal Verification Methodology Language Reference Manual
• Effective Date: 05-Sep-2023

Standards Content (Sample)

IEC 62530-2
®

Edition 1.0 2021-07
™
IEEE Std 1800.2
INTERNATIONAL

STANDARD



SystemVerilog –
Part 2: Universal Verification Methodology Language Reference Manual

IEC 62530-2:2021-07(en)  IEEE Std 1800.2-2017

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IEC 62530-2

®


Edition 1.0 2021-07




IEEE Std 1800.2™
INTERNATIONAL



STANDARD




















SystemVerilog –

Part 2: Universal Verification Methodology Language Reference Manual



























INTERNATIONAL

ELECTROTECHNICAL

COMMISSION






ICS 25.040.01; 35.060 ISBN 978-2-8322-9974-6



  Warning! Make sure that you obtained this publication from an authorized distributor.


® Registered trademark of the International Electrotechnical Commission

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IEC 62530-2:2021 © IEC 2021
IEEE Std 1800.2 ™-2017
Contents
1. Overview. 13
1.1 Scope. 13
1.2 Purpose. 13
1.3 Conventions used. 13
2. Normative references. 16
3. Definitions, acronyms, and abbreviations. 16
3.1 Definitions . 16
3.2 Acronyms and abbreviations . 17
4. UVM class reference . 18
5. Base classes.
...