IEC 61523-1:2023

Delay and power calculation standards - Part 1: Integrated Circuit (IC) Open Library Architecture (OLA)

IEC 61523-1:2023 focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.
The standard specifications covered in this document are as follows:
- Description language for timing and power modeling, called the “delay calculation language” (DCL)
- Software procedural interface (PI) for communications between EDA applications and compiled libraries of DCL descriptions
- Standard file exchange format for parasitic information about the chip design: Standard Parasitic Exchange Format (SPEF)
- Informative usage examples
- Informative notes.
This is an IEC/IEEE dual logo standard.

General Information

• Status: Published
• Publication Date: 10-Oct-2023
• ICS: 25.040.01 - Industrial automation systems in general
• ICS: 35.060 - Languages used in information technology
• Technical Committee: TC 91 - Electronics assembly technology
• Drafting Committee: WG 13 - TC 91/WG 13
• Current Stage: PPUB - Publication issued
• Start Date: 11-Oct-2023
• Completion Date: 08-Sep-2023

Relations

• Revises: IEC 61523-1:2012 - Delay and power calculation standards - Part 1: Integrated circuit delay and power calculation systems
• Effective Date: 05-Sep-2023

Overview

IEC 61523-1:2023 - Delay and power calculation standards, Part 1: Integrated Circuit (IC) Open Library Architecture (OLA) - is an IEC/IEEE dual‑logo standard (published as IEEE Std 1481) that defines a common architecture and data interfaces for delay and power calculation in integrated circuit design. The standard supports modeling of logical behavior and signal integrity, and specifies language, procedural interfaces, and parasitic data formats to improve interoperability between EDA tools and compiled library descriptions.

Key topics and requirements

• Delay Calculation Language (DCL): A descriptive language for timing and power modeling. DCL defines syntax, data types, mathematical statements, and timing propagation mechanisms used to express delay, slew, and power characterization.
• Procedural Interface (PI): A standardized software API for communications between EDA applications and compiled libraries of DCL descriptions, enabling tool-to-library interoperability and consistent invocation of timing/power models.
• Standard Parasitic Exchange Format (SPEF): A file exchange format for parasitic information about chip designs (resistances, capacitances, net topology) used in delay and signal‑integrity calculations.
• Informative examples and notes: Usage examples, context and conventions, and guidance to help implementers adopt DCL, PI and SPEF consistently.
• Scope and structure: Includes lexical rules, predefined types/variables, built-in functions, timing checks, and library/application parallelism considerations.

Keywords: IEC 61523-1, IC Open Library Architecture, delay calculation language, DCL, SPEF, procedural interface, delay and power calculation, signal integrity.

Practical applications

• Standardizing timing and power characterization of standard cell and IP libraries for use across multiple EDA tools.
• Enabling accurate delay, slew and power estimation during static timing analysis, signoff flows, and early architecture studies.
• Facilitating exchange of parasitic and library data between extraction tools, timing engines, and signal‑integrity analyzers using SPEF.
• Supporting automation in library development (PDK/IP vendors) and compiled model deployment in ASIC/SoC flows.

Who should use this standard

• EDA tool developers implementing timing/power engines or library interfaces.
• Library/IP vendors and PDK authors creating DCL-based models and compiled libraries.
• Timing, power and signal-integrity engineers working on characterization, signoff, and interoperability across toolchains.
• Systems architects and verification teams requiring consistent delay and power data exchange.

Related standards

• IEEE Std 1481 (integrated as dual‑logo)
• Other parts of the IEC 61523 series addressing complementary aspects of delay and power calculation and tool flows.

IEC 61523-1:2023 provides a practical foundation for consistent, interoperable delay and power modeling in modern IC design flows, improving accuracy and portability across EDA toolchains.

Standards Content (Sample)

IEC 61523-1 ®
Edition 3.0 2023-10
™
IEEE Std 1481
INTERNATIONAL
STANDARD
colour
inside
Delay and power calculation standards –
Part 1: Integrated Circuit (IC) Open Library Architecture (OLA)
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IEC 61523-1 ®
Edition 3.0 2023-10
IEEE Std 1481™
INTERNATIONAL
STANDARD
colour
inside
Delay and power calculation standards –
Part 1: Integrated Circuit (IC) Open Library Architecture (OLA)
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 25.040.01, 35.060 ISBN 978-2-8322-7539-9
– i – IEEE Std 1481™-2019
Contents
1. Overview . 30
1.1 Scope . 30
1.2 Purpose . 30
1.3 Introduction . 30
1.4 Word usage . 31
2. Normative references . 32
3. Definitions . 32
4. Acronyms and abbreviations . 40
5. Typographical conventions . 41
5.1 Syntactic elements . 41
5.2 Conventions . 42
6. DPCS flow . 42
6.1 Overview . 42
6.1.1 Procedural interface . 44
6.1.2 Global policies and conventions . 44
6.2 Flow of control . 44
6.3 DPCM—application relationships . 44
6.3.1 Technology library . 45
6.3.2 Subrule . 45
6.4 Interoperability . 45
7. Delay calculation language (DCL) . 45
7.1 Character set . 45
7.2 Lexical elements . 45
7.2.1 Whitespace . 46
7.2.2 Comments . 46
7.2.3 Tokens . 46
7.2.4 Header names . 56
7.2.5 Preprocessing directives . 56

7.3 Context. 56
7.3.1 Space . 56
7.3.2 Plane . 56
7.3.3 Context operation . 56
7.3.4 Library parallelism . 56
7.3.5 Application parallelism . 57
7.4 Data types . 57
7.4.1 Base types . 57
7.4.2 Native data types . 57
7.4.3 Mathematical calculation data types . 57
7.4.4 Pointer data types . 58
7.4.5 Aggregate data types . 58
7.5 Identifiers . 64
7.5.1 Name spaces of identifiers . 64
7.5.2 Storage durations of objects . 64
7.5.3 Scope of identifiers . 65
7.5.4 Linkages of identifiers . 66
This is a copyrighted IEEE Standard. For personal or standards development use only.
Published by IEC under licence from IEEE. © 2019 IEEE. All rights reserved.

IEEE Std 1481™-2019 – ii –
7.6 Operator descriptions . 66
7.6.1 String prefix operator . 66
7.6.2 Explicit string prefix operator . 66
7.6.3 Embedded string prefix operator . 67
7.6.4 String prefix semantics . 67
7.6.5 Assignment operator . 67
7.6.6 New operator . 67
7.6.7 SCOPE operator(s) . 68
7.6.8 Launch operator . 69
7.6.9 Purity operator . 69
7.6.10 Force operator . 70
7.7 Timing propagation . 70
7.7.1 Timing checks . 71
7.7.2 Test mode operators . 71
7.8 Expressions . 73
7.8.1 Array subscripting . 74
7.8.2 Statement calls . 74
7.8.3 General syntax . 74
7.8.4 Method statement calls . 74
7.8.5 Assign variable reference . 75
7.8.6 Store variable reference . 75
7.8.7 Mathematical expressions . 75
7.8.8 Mathematical operators . 76
7.8.9 Discrete math expression . 77
7.8.10 INT discrete . 78
7.8.11 PINLIST discrete . 78
7.8.12 Logical expressions and operators . 78
7.8.13 MODE expressions . 78
7.8.14 Embedded C code expressions . 80
7.8.15 Computation order . 81
7.9 DCL mathematical statements . 83
7.9.1 Statement names . 83
7.9.2 Modifiers . 87
7.9.3 Prototypes . 89
7.9.4 Statement failure . 92
7.9.5 Type definition statements . 92
7.9.6 Interfacing statements . 93
7.9.7 DCL to C communication . 95
7.9.8 Constant statement . 95
7.9.9 Calculation statements . 96
7.9.10 METHOD statement . 98
7.10 Predefined types . 99
7.10.1 ACTIVITY_HISTORY_TYPE . 99
7.10.2 HISTORY_TYPE .100
7.10.3 LOAD_HISTORY_TYPE .101
7.10.4 CELL_LIST_TYPE .102
7.10.5 TECH_TYPE .102
7.10.6 DELAY_REC_TYPE .102
7.10.7 SLEW_REC_TYPE .103
7.10.8 CHECK_REC_TYPE .103
7.10.9 CCDB_TYPE .103
7.10.10 CELL_DATA_TYPE .103
7.10.11 PCDB_TYPE .103
7.10.12 PIN_ASSOCIATION .104
7.10.13 PATH_DATA_TYPE .104
7.10.14 STD STRUCT .104
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Published by IEC under licence from IEEE. © 2019 IEEE. All rights reserved.

– iii – IEEE Std 1481™-2019
7.11 Predefined variables .105
7.11.1 ARGV .105
7.11.2 CONTROL_PARM .105
7.12 Built-in function calls .105
7.12.1 ABS .106
7.12.2 Complex number components .106
7.12.3 EXPAND .106
7.12.4 Array functions .106
7.12.5 Messaging functions .107
7.13 Tables .109
7.13.1 TABLEDEF statement .109
7.13.2 Table visibility rules . 111
7.13.3 TABLE statement . 112
7.13.4 LOAD_TABLE statement . 115
7.13.5 UNLOAD_TABLE statement . 117
7.13.6 WRITE_TABLE statement . 118
7.13.7 ADD_ROW statement . 118
7.13.8 DELETE_ROW statement . 119
7.14 Built-in library functions .120
7.14.1 Numeric conversion functions .120
7.14.2 Tech_family functions .122
7.14.3 Trigonometric functions .123
7.14.4 Context manipulation functions .124
7.14.5 Debug controls .126
7.14.6 Utility functions .126
7.14.7 Table functions .127
7.14.8 Subrule controls .128
7.15 Library control statements .129
7.15.1 Meta-variables .129
7.15.2 TECH_FAMILY .129
7.15.3 RULENAME .129
7.15.4 CONTROL_PARM .129
7.15.5 SUBRULE statement .129
7.15.6 Path list expansion rules .130
7.15.7 SUBRULES statement .131
7.15.8 Control file .131
7.15.9 TECH_FAMILY statement.133
7.15.10 SUBRULE and SUBRULES statements .134
7.16 Modeling .134
7.16.1 Types of modeling .134
7.16.2 Model organization .135
7.16.3 MODELPROC statement .136
7.16.4 SUBMODEL statement .137
7.16.5 Modeling statements .139
7.16.6 TEST_BUS statement .148
7.16.7 INPUT statement .149
7.16.8 OUTPUT statement .152
7.16.9 DO statement .153
7.16.10 PROPERTIES statement .174
7.16.11 SETVAR statement .175
7.17 Embedded C code .176
7.18 Definition of a subrule .176
7.19 Pragma .177
7.19.1 IMPORT_EXPORT_TAG .177
This is a copyrighted IEEE Standard. For personal or standards development use only.
Published by IEC under licence from IEEE. © 2019 IEEE. All rights reserved.

IEEE Std 1481™-2019 – iv –
8. Power modeling and calculation .177
8.1 Power overview .177
8.2 Caching state information .178
8.2.1 Initializing the state cache .178
8.2.2 State cache lifetime .178
8.3 Caching load and slew information .178
8.3.1 Loading the load and slew cache .179
8.3.2 Load and slew cache lifetime .179
8.4 Simulation switching events .180
8.5 Partial swing events .180
8.6 Power calculation .180
8.7 Accumulation of power consumption by the design .182
8.8 Group Pin List syntax and semantics .182
8.8.1 Syntax .182
8.8.2 Semantics .183
8.8.3 Example .183
8.9 Group Condition List syntax and semantics .183
8.9.1 Syntax .184
8.9.2 Semantics .184
8.9.3 Example .184
8.10 Sensitivity list syntax and semantics .184
8.10.1 Syntax .185
8.10.2 Semantics .185
8.10.3 Example .185
8.11 Group condition language .185
8.11.1 Syntax .186
8.11.2 Semantics .186
8.11.3 Condition expression operator precedence .188
8.11.4 Condition expressions referencing pin states and transitions .188
8.11.5 Semantics of nonexistent pins .189
9. Application and library interaction .189
9.1 behavior model domain .189
9.2 vectorTiming and vectorPower model domains .190
9.2.1 Power unit conversion .190
9.2.2 Vector power calculation .190
10. Procedural interface (PI) .191
10.1 Overview .191
10.1.1 DPCM .191
10.1.2 Application .192
10.1.3 libdcmlr .192
10.2 Control and data flow .192
10.3 Architectural requirements .192
10.4 Data ownership technique .193
10.4.1 Persistence of data passed across the PI .193
10.4.2 Data cache guidelines for the DPCM .193
10.4.3 Application/DPCM interaction .194
10.4.4 Application initializes message/memory handling .194
10.4.5 Application loads and initializes the DPCM .194
10.4.6 Application requests timing models for cell instances .194
10.5 Model domain issues .194
10.5.1 Model domain selection .194
10.5.2 Model domain determination .195
10.5.3 DPCM invokes application modeling callback functions .195
10.5.4 Application requests propagation delay .195
10.5.5 DPCM calls application EXTERNAL functions .196
10.6 Reentry requirements .196
This is a copyrighted IEEE Standard. For personal or standards development use only.
Published by IEC under licence from IEEE. © 2019 IEEE. All rights reserved.

– v – IEEE Std 1481™-2019
10.7 Application responsibilities when using a DPCM .196
10.7.1 Standard Structure rules .196
10.7.2 User object registration .197
10.7.3 Selection of early and late slew values .197
10.7.4 Semantics of slew values .198
10.7.5 Slew calculations .198
10.8 Application use of the DPCM .198
10.8.1 Initialization of the DPCM .198
10.8.2 Context creation .199
10.8.3 Dynamic linking .199
10.8.4 Subrule initialization .200
10.8.5 Use of the DPCM .201
10.8.6 Application control .201
10.8.7 Application execution .201
10.8.8 Termination of DPCM .201
10.9 DPCM library organization .202
10.9.1 Multiple technologies .202
10.9.2 Model names .202
10.9.3 DPCM error handling .202
10.10 C level language for EXPOSE and EXTERNAL functions .203
10.10.1 Integer return code .203
10.10.2 The Standard Structure pointer .203
10.10.3 Result structure pointer .203
10.10.4 Passed arguments .203
10.10.5 DCL array indexing .204
10.10.6 Conversion to C data types .204
10.10.7 include files .204
10.11 PIN and BLOCK data structure requirements.205
10.12 DCM_STD_STRUCT Standard Structure .206
10.12.1 Alternate semantics for Standard Structure fields .208
10.12.2 Reserved fields .209
10.12.3 Standard Structure value restriction .209
10.13 DCMTransmittedInfo structure .209
10.14 Environment or user variables .209
10.15 Procedural interface (PI) functions summary .209
10.15.1 Expose functions .209
10.15.2 External functions .217
10.15.3 Deprecated functions .220
10.16 Implicit functions .222
10.16.1 libdcmlr .222
10.16.2 Run-time library utility functions .223
10.16.3 Memory control functions .223
10.16.4 Message and error control functions .224
10.16.5 Calculation functions .225
10.16.6 Modeling functions .225
10.17 PI function table description .225
10.17.1 Arguments .226
10.17.2 DCL syntax .227
10.17.3 C syntax .227
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Published by IEC under licence from IEEE. © 2019 IEEE. All rights reserved.

IEEE Std 1481™-2019 – vi –
10.18 PI function descriptions .227
10.18.1 Interconnect loading related functions .227
10.18.2 Interconnect delay related functions .234
10.18.3 Functions accessing netlist information .237
10.18.4 Functions exporting limit information .246
10.18.5 Functions getting/setting model information .247
10.18.6 Functions importing instance name information .260
10.18.7 Process information functions .263
10.18.8 Miscellaneous standard interface functions .265
10.18.9 Power-related functions .274
10.19 Application context .282
10.19.1 pathData association .282
10.20 Application and library interaction .282
10.20.1 behavior model domain .283
10.20.2 vectorTiming and vectorPower model domains .283
10.20.3 Power unit conversion .284
10.20.4 Vector power calculation .284
10.21 Parasitic analysis .
...