IEC 62014-4:2015

IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within Tool Flows

IEC 62014-4:2015(E) describes an eXtensible Markup Language (XML) schema for meta-data documenting intellectual property (IP) used in the development, implementation, and verification of electronic systems and an application programming interface (API) to provide tool access to the meta-data. This schema provides a standard method to document IP that is compatible with automated integration techniques. The API provides a standard method for linking tools into a system development framework, enabling a more flexible, optimized development environment.

General Information

• Status: Published
• Publication Date: 10-Mar-2015
• ICS: 01 - GENERALITIES. TERMINOLOGY. STANDARDIZATION. DOCUMENTATION
• ICS: 25.040.01 - Industrial automation systems in general
• ICS: 35.240.50 - IT applications in industry
• Technical Committee: TC 91 - Electronics assembly technology
• Current Stage: PPUB - Publication issued
• Start Date: 30-Apr-2015
• Completion Date: 11-Mar-2015

Standards Content (Sample)

IEC 62014-4 ®
Edition 1.0 2015-03
™
IEEE Std 1685 -2009
INTERNATIONAL
STANDARD
IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within
Tool Flows
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IEC 62014-4 ®
Edition 1.0 2015-03
IEEE Std 1685™-2009
INTERNATIONAL
STANDARD
IP-XACT, Standard Structure for Packaging, Integrating, and Reusing IP within

Tool Flows
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 25.040 ISBN 978-2-8322-2265-2

IEC 62014-4
i IEEE Std 1685-2009
Contents
1. Overview. 1
1.1 Scope. 1
1.2 Purpose. 2
1.3 Design environment. 2
1.4 IP-XACT Enabled implementations. 6
1.5 Conventions used. 7
1.6 Use of color in this standard . 12
1.7 Contents of this standard. 12
2. Normative references. 13
3. Definitions, acronyms, and abbreviations. 15
3.1 Definitions . 15
3.2 Acronyms and abbreviations . 21
4. Interoperability use model . 23
4.1 Roles and responsibilities . 23
4.2 IP-XACT IP exchange flows . 24
5. Interface definition descriptions . 27
5.1 Definition descriptions. 27
5.2 Bus definition. 27
5.3 Abstraction definition . 30
5.4 Ports . 31
5.5 Wire ports . 32
5.6 Qualifiers . 34
5.7 Wire port group. 36
5.8 Wire port mode constraints. 38
5.9 Wire port mirrored-mode constraints . 39
5.10 Transactional ports. 41
5.11 Transactional port group. 43
5.12 Extending bus and abstraction definitions . 44
5.13 Clock and reset handling. 47
6. Component descriptions . 49
6.1 Component. 49
6.2 Interfaces. 52
6.3 Interface interconnections. 52
6.4 Complex interface interconnections . 54
6.5 Bus interfaces. 56
6.6 Component channels. 67
6.7 Address spaces. 69
6.8 Memory maps . 81
6.9 Remapping . 97
6.10 Registers. 102
6.11 Models . 120
6.12 Component generators . 151
6.13 File sets . 153
6.14 Choices. 165
Published by IEC under license from IEEE. © 2009 IEEE. All rights reserved.
IEC 62014-4
IEEE Std 1685-2009 ii
6.15 White box elements . 167
6.16 White box element reference . 168
6.17 CPUs . 170
7. Design descriptions. 171
7.1 Design . 171
7.2 Design component instances. 173
7.3 Design interconnections. 175
7.4 Active, monitored, and monitor interfaces . 176
7.5 Design ad hoc connections . 178
7.6 Design hierarchical connections .180
8. Abstractor descriptions . 183
8.1 Abstractor. 183
8.2 Abstractor interfaces . 185
8.3 Abstractor models . 187
8.4 Abstractor views . 189
8.5 Abstractor ports. 191
8.6 Abstractor wire ports . 193
8.7 Abstractor generators. 195
9. Generator chain descriptions . 199
9.1 generatorChain. 199
9.2 generatorChainSelector. 201
9.3 generatorChain component selector. 202
9.4 generatorChain generator. 203
10. Design configuration descriptions . 207
10.1 Design configuration. 207
10.2 designConfiguration. 207
10.3 generatorChainConfiguration . 209
10.4 interconnectionConfiguration . 211
11. Addressing and data visibility. 213
11.1 Calculating the bit address of a bit in a memory map . 213
11.2 Calculating the bus address at the slave bus interface . 214
11.3 Address modifications of an interconnection .
...