Semiconductor devices - Reliability test method for silicon carbide discrete metal-oxide semiconductor field effect transistors - Part 1: Test method for bias temperature instability

IEC 63275-1:2022 gives a test method to evaluate gate threshold voltage shift of silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) using room temperature readout after applying continuous positive gate-source voltage stress at elevated temperature. The proposed method accepts a certain amount of recovery by allowing large delay times between stress and measurement (up to 10 h).

Dispositifs à semiconducteurs - Méthode d’essai de fiabilité pour les transistors à effet de champ métal-oxyde-semiconducteurs discrets en carbure de silicium - Partie 1: Méthode d’essai pour la mesure de la dérive de la tension de seuil après polarisation électrique en température

L’IEC 63275-1:2022 donne une méthode d’essai pour évaluer le décalage de la tension de seuil de grille des transistors à effet de champ métal-oxyde-semiconducteurs (MOSFET) de puissance en carbure de silicium (SiC) en utilisant un relevé à température ambiante après avoir appliqué une contrainte de tension grille-source positive continue à température élevée. La méthode proposée accepte une certaine quantité de recouvrement en autorisant des décalages importants entre la contrainte et la mesure (jusqu’à 10 h).

General Information

Status
Published
Publication Date
20-Apr-2022
Technical Committee
Current Stage
PPUB - Publication issued
Completion Date
21-Apr-2022
Ref Project

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IEC 63275-1
Edition 1.0 2022-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor devices – Reliability test method for silicon carbide discrete
metal‑oxide semiconductor field effect transistors –
Part 1: Test method for bias temperature instability

Dispositifs à semiconducteurs – Méthode d’essai de fiabilité pour les transistors

à effet de champ métal-oxyde-semiconducteurs discrets en carbure de
silicium –
Partie 1: Méthode d’essai pour la mesure de la dérive de la tension de seuil
après polarisation électrique en température
IEC 63275-1:2022-04(en-fr)
---------------------- Page: 1 ----------------------
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---------------------- Page: 2 ----------------------
IEC 63275-1
Edition 1.0 2022-04
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Semiconductor devices – Reliability test method for silicon carbide discrete
metal‑oxide semiconductor field effect transistors –
Part 1: Test method for bias temperature instability
Dispositifs à semiconducteurs – Méthode d’essai de fiabilité pour
les transistors à effet de champ métal-oxyde-semiconducteurs discrets en
carbure de
silicium –
Partie 1: Méthode d’essai pour la mesure de la dérive de la tension de seuil
après polarisation électrique en température
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.080.30 ISBN 978-2-8322-1101-5

Warning! Make sure that you obtained this publication from an authorized distributor.

Attention! Veuillez vous assurer que vous avez obtenu cette publication via un distributeur agréé.

® Registered trademark of the International Electrotechnical Commission
Marque déposée de la Commission Electrotechnique Internationale
---------------------- Page: 3 ----------------------
– 2 – IEC 63275-1:2022 © IEC 2022
CONTENTS

FOREWORD ........................................................................................................................... 3

INTRODUCTION ..................................................................................................................... 5

1 Scope .............................................................................................................................. 6

2 Normative references ...................................................................................................... 6

3 Terms and definitions ...................................................................................................... 6

4 Requirements .................................................................................................................. 6

4.1 Sample ................................................................................................................... 6

4.2 Test temperature .................................................................................................... 6

4.3 Test voltage ............................................................................................................ 6

4.4 Test time ................................................................................................................. 7

4.5 Measurement temperature ...................................................................................... 7

4.6 Failure criteria ......................................................................................................... 7

4.7 Test circuit .............................................................................................................. 7

5 Procedures ...................................................................................................................... 7

5.1 Sequence of procedure ........................................................................................... 7

5.2 Select sample ......................................................................................................... 8

5.3 V measurement methods .............................................................................. 8

GS(th)

5.4 How to provide a reproducible measurement of V ....................................... 11

GS(th)

5.5 Initial measurement .............................................................................................. 11

5.6 Apply voltage and temperature stress ................................................................... 12

5.7 Remove voltage and temperature stress ............................................................... 12

5.8 Intermediate measurement.................................................................................... 12

6 Test report ..................................................................................................................... 12

Bibliography .......................................................................................................................... 13

Figure 1 – Circuit diagram for bias temperature instability test ................................................ 7

Figure 2 – Test flow chart ....................................................................................................... 8

Figure 3 – Schematic of test pattern for Example 1 ................................................................. 9

Figure 4 – I versus V curve for Example 1 ..................................................................... 9

DS GS

Figure 5 – Schematic of test pattern for Example 2 and Example 3 ....................................... 10

Figure 6 – I versus V curve for Example 2 ................................................................... 10

DS GS

Figure 7 – I – V curve for Example 3 ........................................................................... 10

DS GS

Figure 8 – Schematic of test pattern for Example 4 ............................................................... 11

---------------------- Page: 4 ----------------------
IEC 63275-1:2022 © IEC 2022 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
SEMICONDUCTOR DEVICES –
RELIABILITY TEST METHOD FOR SILICON CARBIDE DISCRETE
METAL‑OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS –
Part 1: Test method for bias temperature instability
FOREWORD

1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising

all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international

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indispensable for the correct application of this publication.

9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent

rights. IEC shall not be held responsible for identifying any or all such patent rights.

IEC 63275-1 has been prepared by IEC technical committee 47: Semiconductor devices. It is

an International Standard.
The text of this International Standard is based on the following documents:
Draft Report on voting
47/2755/FDIS 47/2764/RVD

Full information on the voting for its approval can be found in the report on voting indicated in

the above table.
The language used for the development of this International Standard is English.
---------------------- Page: 5 ----------------------
– 4 – IEC 63275-1:2022 © IEC 2022

This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in

accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available

at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are

described in greater detail at www.iec.ch/standardsdev/publications.

A list of all parts in the IEC 63275 series, published under the general title Semiconductor

devices – Reliability test method for silicon carbide discrete metal‑oxide semiconductor field

effect transistors, can be found on the IEC website.

The committee has decided that the contents of this document will remain unchanged until the

stability date indicated on the IEC website under webstore.iec.ch in the data related to the

specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
---------------------- Page: 6 ----------------------
IEC 63275-1:2022 © IEC 2022 – 5 –
INTRODUCTION

One reliability issue for silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors

(MOSFETs) is gate-source threshold voltage shift under gate-source voltage stress.

Gate-source threshold voltage is a key parameter to represent switching characteristics of

MOSFETs. Since the shift value tends to be larger than that of conventional Si based devices,

it is indispensable to establish an International Standard with regard to evaluation of

gate-source threshold voltage shift as a reliability issue.

This document defines the evaluation method of gate-source threshold voltage shift under

continuous temperature and gate-source voltage stress on SiC MOSFETs.
---------------------- Page: 7 ----------------------
– 6 – IEC 63275-1:2022 © IEC 2022
SEMICONDUCTOR DEVICES –
RELIABILITY TEST METHOD FOR SILICON CARBIDE DISCRETE
METAL‑OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS –
Part 1: Test method for bias temperature instability
1 Scope

This part of IEC 63275 gives a test method to evaluate gate threshold voltage shift of silicon

carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) using room

temperature readout after applying continuous positive gate-source voltage stress at elevated

temperature. The proposed method accepts a certain amount of recovery by allowing large

delay times between stress and measurement (up to 10 h).
2 Normative references

The following documents are referred to in the text in such a way that some or all of their content

constitutes requirements of this document. For dated references, only the edition cited applies.

For undated references, the latest edition of the referenced document (including any

amendments) applies.

IEC 60747-8, Semiconductor devices – Discrete devices – Part 8: Field-effect transistors

3 Terms and definitions

For the purposes of this document, the terms and definitions given in IEC 60747-8 apply.

ISO and IEC maintain terminological databases for use in standardization at the following

addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
4 Requirements
4.1 Sample

Unless otherwise specified, a minimum of four samples is recommended for each test condition

to evaluate representative behaviour of V drift. When the test method is applied to qualify

GS(th)

reliability of product, the sample size should be defined by taking into consideration

device-to-device deviation of shift value of V and target application of the product.

GS(th)
4.2 Test temperature

The test is performed at the temperature within the maximum rating of the sample.

4.3 Test voltage

The test is performed at the V within the maximum rating of the sample. The tests in this

document treat only positive V stress.
---------------------- Page: 8 ----------------------
IEC 63275-1:2022 © IEC 2022 – 7 –
4.4 Test time

Test time is set individually to reach failure criteria of V or to collect data required to

GS(th)

extrapolate the log time dependence to reach failure criteria V . The time for temperature

GS(th)
ramping and measuring V shall not be added to the stress time.
GS(th)
4.5 Measurement temperature

Measurement is performed at room temperature with a tolerance, e.g. 23 °C ± 2 °C. The

measurement temperature shall be consistent across the evaluation.
4.6 Failure criteria

It is recommended to link the failure criteria to a maximum allowed V drift level that does

GS(th)
not cause the violation of any data sheet specification limit.
4.7 Test circuit

Figure 1 shows the test circuit. VGS, voltage source for the V is the voltage source to apply

V on a sample. VDS, voltage source for the V is the voltage source to apply V on a

GS DS DS
sample for V measurement.
GS(th)
Key
A ammeter to measure drain source current of DUT
DUT device under test sample
VGS voltage source for the V
VDS voltage source for the V
Figure 1 – Circuit diagram for bias temperature instability test
5 Procedures
5.1 Sequence of procedure
The test method evaluates the shift value of V by alternately conducting V
GS(th) GS(th)

measurement and applying temperature and voltage stress on the gate terminal of the sample.

Figure 2 shows the test flow chart.
---------------------- Page: 9 ----------------------
– 8 – IEC 63275-1:2022 © IEC 2022
Figure 2 – Test flow chart
5.2 Select sample
Select and set the sample to the test apparatus.
5.3 V measurement methods
GS(th)
V can be defined by several measurement methods. Examples of V measurement
GS(th) GS(th)
methods are listed below:
a) Example 1: Constant current method 1 (V is measured with constant V .)
GS(th) DS

Figure 3 and Figure 4 show schematics of the sequence of positive bias temperature

instability (PBTI) test and I versus V curve for Example 1, respectively. The procedure

DS GS

of V measurement is that the drain to source current (I ) is measured while sweeping

GS(th) DS

gate to source voltage (V ). The drain to source voltage (V ) is kept constant to flow the

GS DS
I . A threshold current (I ) shall be defined to measure V . V is the V when
DS DS(th) GS(th) GS(th) GS

the I crosses the threshold current during the V sweeping operation. A conditioning

DS GS

pulse is applied prior to measuring the V , as shown in Figure 3. The conditioning

GS(th)
procedure is described in 5.4.
---------------------- Page: 10 ----------------------
IEC 63275-1:2022 © IEC 2022 – 9 –
Figure 3 – Schematic of test pattern for Example 1
Figure 4 – I versus V curve for Example 1
DS GS
b) Example 2: Constant current method 2 (V is measured with V = V .)
GS(th) GS DS

Figure 5 and Figure 6 show schematics of the sequence of PBTI test and I versus V

DS GS

curve for Example 2, respectively. The procedure of V measurement is that the I is

GS(th) DS

measured while sweeping V . The V is kept the same as the V to allow the I to flow.

GS DS GS DS
A threshold current I shall be defined to measure V . V is the V when the
DS(th) GS(th) GS(th) GS

I crosses the I during the V sweeping operation. The I current limit shall be set

DS DS(th) GS DS

to a rated-current value corresponding to a standard scale, such as 250 µA/A (e.g. for a

20 A device, I limit is 5 mA).
---------------------- Page: 11 ----------------------
– 10 – IEC 63275-1:2022 © IEC 2022
Figure 5 – Schematic of test pattern for Example 2 and Example 3
Figure 6 – I versus V curve for Example 2
DS GS
c) Example 3: Extrapolation method
versus V curve for Example 3. I is measured at
Figure 7 shows a schematic of the I
DS GS DS

condition of V = V . V is the X-intercept of the interpolated line of square root of

DS GS GS(th)
I .
Figure 7 – I – V curve for Example 3
DS GS
---------------------- Page: 12 ----------------------
IEC 63275-1:2022 © IEC 2022 – 11 –
d) Example 4: Spot measurement method

Figure 8 shows schematics of sequence of PBTI test for Example 4. The procedure of V

GS(th)

measurement is that the I is measured while applying pulsed V without sweeping V .

DS GS GS
The V is kept either constant or the same as the V to flow the I . A I shall be
DS GS DS DS(th)
defined to measure V . The V is V at the I .
GS(th) GS(th) GS DS(th)
Figure 8 – Schematic of test pattern for Example 4
The V measurement method can be selected by users of this document. The V
GS(th) GS(th)
measurement condition shall be consistent across the evaluation.
5.4 How to provide a reproducible measurement of V
GS(th)

Conditioning is recommended before initial and intermediate V measurement. A positive

GS(th)

V pulse should be applied before measurement as conditioning to evaluate the shift value of

V while avoiding the hysteresis effect that is generated by carrier trapping and de-trapping

GS(th)

into interfacial traps. The conditioning bias of the V should be equal to the soaking/stressing

voltage or less and within the maximum rating of the sample. The voltage level of V pulse

width should be 100 ms [1] . It is recommended to check the conditioning parameters by

ensuring they provide measurement values of V stably. The conditioning bias and the time

GS(th)

delay between conditioning and V measurement shall be consistent across the evaluation.

GS(th)

For more details on how to perform the conditioning prior to measuring the V , refer to [2].

GS(th)
5.5 Initial measurement

Measure the initial value of V of the sample after conditioning. The time delay between

GS(th)
conditioning and initial measurement should be within 10 ms.
____________
Numbers in square brackets refer to the Bibliography.
---------------------- Page: 13 ----------------------
– 12 – IEC 63275-1:2022 © IEC 2022
5.6 Apply voltage and temperature stress

Apply the gate-source voltage and temperature stress on the sample. The voltage of V

voltage source should be reduced to zero before gate stress voltage is applied. Heating up with

or without bias applied should be optional. Whatever the method used, the bias condition during

heating shall be specified in the test report and the time to reach the stress temperature shall

be minimized. If the voltage is applied before, part of the stress is at an undefined temperature.

5.7 Remove voltage and temperature stress

Remove the gate-source voltage and temperature stress on the sample for the intermediate

measurement. Cooling down with or without bias applied should be optional. Whatever the

method used, the bias condition during cooling shall be specified in the test report and the time

to reach the stress temperature shall be minimized. If the voltage is applied with cooling down,

it does avoid recovery to a certain degree, but it also adds some additional stress at an

undefined temperature.
5.8 Intermediate measurement

Intermediate measurements should be performed within 10 h after terminating voltage stress.

During intermediate measurement, measure the intermediate value of V of the sample

GS(th)

after conditioning and evaluate the shift value of V by taking the difference to initial value.

GS(th)

The time delay between conditioning and intermediate measurement is recommended within

10 ms.

Intermediate measurements should be arranged in logarithmic time intervals to evaluate the

drift of V . Characteristics other than V (e.g., R , I , etc.) can be measured during

GS(th) GS(th) on DS
intermediate measurement but it is recommended to measure V always at first.
GS(th)
6 Test report
A test report shall be provided, that includes:
– sample identification;
– test bias condition during heating;
– test temperature;
– test voltage;
– test time;
– test bias condition during cooling;

– pulse condition (width, voltage and negative bias of conditioning if negative bias is applied)

of conditioning pulse before V measurement;
GS(th)
– V measurement method;
GS(th)
– shift value of gate-source threshold voltage;
– other characteristics (R , I , ...).
on DS
---------------------- Page: 14 ----------------------
IEC 63275-1:2022 © IEC 2022 – 13 –
Bibliography

[1] Thomas Aichinger, Gerald Rescher, Gregor Pobegen, "Threshold voltage peculiarities

and bias temperature instabilities of SiC MOSFETs", Microelectron. Reliab. 80 (2018)

68–78

[2] JEDEC JEP183, "Guidelines for measuring the threshold voltage (VT) of SiC MOSFETs",

Version 1.03, (2021)
___________
---------------------- Page: 15 ----------------------
– 14 – IEC 63275-1:2022 © IEC 2022
SOMMAIRE

AVANT-PROPOS .................................................................................................................. 15

INTRODUCTION ................................................................................................................... 17

1 Domaine d’application ................................................................................................... 18

2 Références normatives .................................................................................................. 18

3 Termes et définitions ..................................................................................................... 18

4 Exigences ...................................................................................................................... 18

4.1 Echantillon ............................................................................................................ 18

4.2 Température d’essai ............................................................................................. 18

4.3 Tension d'essai ..................................................................................................... 19

4.4 Durée d’essai ........................................................................................................ 19

4.5 Température de mesure ........................................................................................ 19

4.6 Critères de défaillance .......................................................................................... 19

4.7 Circuit d'essai ....................................................................................................... 19

5 Procédures .................................................................................................................... 20

5.1 Ordre de la procédure ........................................................................................... 20

5.2 Choix de l’échantillon ............................................................................................ 20

5.3 Méthodes de mesure de la tension V .......................................................... 20

GS(th)

5.4 Comment fournir une mesure reproductible de V ......................................... 23

GS(th)

5.5 Mesure initiale ...................................................................................................... 24

5.6 Appliquer la contrainte de tension et de température ............................................ 24

5.7 Retirer la contrainte de tension et de température ................................................. 24

5.8 Mesure intermédiaire .................
...

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