IEC PAS 62085:1998

Implementation of ball grid array and other high density technology

Establishes the requirements and interactions necessary for Printed Board Assembly processes for interconnecting high performance/high pin count I/C packages. Included is information on design principles, material selection, board fabrication, assembly technology, testing strategy, and reliability expectations based on end-use environments.

General Information

• Status: Withdrawn
• Publication Date: 02-Dec-1998
• Withdrawal Date: 28-Oct-2004
• ICS: 33.200 - Telecontrol. Telemetering
• Technical Committee: TC 91 - Electronics assembly technology
• Current Stage: WPUB - Publication withdrawn
• Start Date: 31-Oct-2004
• Completion Date: 29-Oct-2004

Standards Content (Sample)

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Edition 1.0
1998-12
Implementation of Ball Grid Array
and other High Density Technology

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IN TER N A TION AL Reference number
E L E C T R OT E CHNI CA L
IEC/PAS 62085
C O MMI S S I O N
Copyright © 1996, IPC; 1998, IEC

J-STD-013
JULY 1996
JOINT INDUSTRY STANDARD
COORDINATED BY THE SURFACE MOUNT COUNCIL

Copyright © 1996, IPC; 1998, IEC

INTERNATIONAL ELECTROTECHNICAL COMMISSION

____________
IMPLEMENTATION OF BALL GRID ARRAY

AND OTHER HIGH DENSITY TECHNOLOGY

FOREWORD
A PAS is a technical specification not fulfilling the requirements for a standard, but made available to the

public and established in an organization operating under given procedures.

IEC-PAS 62085 was submitted by the IPC (The Institute for Interconnecting and Packaging Electronic Circuits) and
has been processed by IEC technical committee 91: Surface mounting technology.
The text of this PAS is based on the This PAS was approved for
following document: publication by the P-members of the
committee concerned as indicated in
the following document:
Draft PAS Report on voting
91/140/PAS 91/154/RVD
Following publication of this PAS, the technical committee or subcommittee concerned will investigate the
possibility of transforming the PAS into an International Standard.
The following statement has been made by IPC (The Institute for Interconnecting and Packaging Electronic
Circuits):
The IPC has the leadership position on this publication, as suggested by the Surface Mount Council. Any
input or suggestion from other persons or organizations, not a part of the IPC membership, has been
coordinated by the IPC during the development process.
The IEC and its members are authorized to exploit the following document:
J-STD-013 Implementation of ball grid array and other high density technology
under the PAS procedures for the purpose of international standardization.
1) The IEC (International Electrotechnical Commission) is a worldwide organization for standardization comprising all
national electrotechnical committees (IEC National Committees). The object of the IEC is to promote international co-
operation on all questions concerning standardization in the electrical and electronic fields. To this end and in addition
to other activities, the IEC publishes International Standards. Their preparation is entrusted to technical committees;
any IEC National Committee interested in the subject dealt with may participate in this preparatory work. International,
governmental and non-governmental organizations liaising with the IEC also participate in this preparation. The IEC
collaborates closely with the International Organization for Standardization (ISO) in accordance with conditions
determined by agreement between the two organizations.

2) The formal decisions or agreements of the IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all interested
National Committees.
3) The documents produced have the form of recommendations for international use and are published in the form of
standards, technical reports or guides and they are accepted by the National Committees in that sense.
4) In order to promote international unification, IEC National Committees undertake to apply IEC International Standards
transparently to the maximum extent possible in their national and regional standards. Any divergence between the
IEC Standard and the corresponding national or regional standard shall be clearly indicated in the latter.
5) The IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with one of its standards.
6) Attention is drawn to the possibility that some of the elements of this PAS may be the subject of patent rights. The
IEC shall not be held responsible for identifying any or all such patent rights.

Copyright © 1996, IPC; 1998, IEC
July 1996 J-STD-013
Material in this standard was voluntarily coordinated by the Surface Mount Coun-

cil (SMC), and established by Technical Committees of IPC and EIA. Committee
members of the two organizations contributed their time, knowledge and expertise
to blend a cohesive report on the topic covered by this document. Proposals were
sent to key individuals in each of the individual organizations for consensus.
Meetings were held to resolve differences or conflicts prior to documenting the
information in the final released version.
The material contained herein is advisory and its use or adaptation is entirely vol-
untary. IPC and EIA disclaim all liability of any kind as to the use, application, or
adaptation of this material. Users are also wholly responsible for protecting them-
selves against all claims or liabilities for patent infringement.
Comments Welcome
The J-STD-013 is intended to serve as a roadmap for ball grid array and other
high-density technology implementation.
In order to keep the document current, the Surface Mount Council welcomes com-
ments from individuals reading the document, or implementing the suggested con-
cepts.
Comments may be sent to the EIA or IPC. All comments will be organized and
sent to representatives of the Ad Hoc Committee responsible for the J-STD-013 for
a yearly review and incorporation into the updating procedures.
Final Ballot Edition
The Surface Mount Council has authorized the special printing of this document in order to make the information available

to industry experts for final ballot approval.
The official publication will be released for full industry circulation after the final editorial revision and completion of the
balloting process by representatives of JEDEC. The results of those processes may initiate some changes. Once concensus
has been reached, the official J-STD-013 will be printed and be supported by the three organizations, EIA, IPC, and JEDEC,
and endorsed by Sematech and MCNC whose representatives participated and contributed to the development of this
document.
Copyright © 1996, IPC; 1998, IEC
July 1996 IPC-J-STD-013
J-STD-013
IMPLEMENTATION OF BALL GRID ARRAY

AND OTHER HIGH-DENSITY TECHNOLOGY

About this Document
This document is intended to report on the work being done by a variety of organizations concerned with surface mount-
ing of area array packages or other high pin count package configurations. The details were developed by companies who
have implemented the processes described herein and have agreed to share their experiences. Readers are encouraged to
communicate to the appropriate trade association any comments or observations regarding details published in this docu-
ment, or provide additional ideas and details that would serve the industry.
Section 8 of this document represents a listing of standards that are being developed, being updated, or need to be created
in order to provide for the orderly implementation of Ball Grid Array, or other High-Density Technology. Members of the
industry are invited to participate in the ongoing standardization process.
For additional information regarding material published herein or inquiries regarding the status of standardization activities,
we urge you to contact the organization listed below.

IPC EIA
The Institute for Interconnecting Electronic Industries Association
and Packaging Electronic Circuits 2500 Wilson Blvd.
2215 Sanders Road Arlington, VA 22201-3834
Northbrook, IL 60062-6135 Telephone: [phone]
Telephone: [phone] Fax: [phone]
Fax: [phone]
i
BGA 225 I/O
Copyright © 1996, IPC; 1998, IEC
IPC-J-STD-013 July 1996
Acknowledgement
Any standard involving a complex technology draws material from a vast number of sources. While the

principle members of the Ad Hoc committee are shown below, it is not possible to include all of those

who assisted in the evolution of this document. To each of them, the members of the IPC and EIA extend

their gratitude.
Ball Grid Array Technology Ad Hoc Committee
Chairman: Ray Prasad, Ray Prasad Consultancy Group
L. Abnagnaro, Pace Inc. Les Hymes, Les Hymes Associates
George Arrigotti, Intel A. Kaliszek, Honeywell Inc.
E.M. Aoki, Hewlett Packard G. W. Kenealey, GWK Enterprises, Inc.
R. Aspandiar, Intel William Kenyon, Global Ctr for Process Change
Ron Boyce, Tektronix J. D. Leibowitz, Shirline Composites Inc.
J.S. Burg, 3 M. Company Nick Lycoudes, Motorola
Chusak Chamkasem, Hyundai Electronics America Paul Magill, MCNC
T. A. Carroll, Hughes Aircraft S. R. Martell, Sonoscan Inc.
Leon Cohen, Formation Jack McMahon, Intel Corp.
J. Cordum, Teledyne Lewisburg G. C. Munie, AT&T Bell Laboratories
T. Dixon Dudderar, AT&T R. Perez, Compaq Computer Corp.
Werner Engelmaier, Engelmaier & Assoc. E. Pope, Intel Corporation
Gerald K. Fehr, IPAC R. J. Prosman, IEEC/Binghamton Univ
J. R. Finnell, National Semicondutor Jeff Robb, Lockeed Martin
Joseph Fjelstad, Tessera Robert Rowland, Fujitsu Computer Products
Martin G. Freedman, AMP Incorporated Craig A. St. Martin, II
A. Funcell, Integrated Device Tech Vern Solberg, Tessera
C. J. Gonzlez, SCI Manufacturing Frank S. Stein, Consultant
Gary W. Green, Cypress Semiconductor G. Theroux, Honeywell Inc.
Greg Igo, Amkor Electronics Inc. Murli Tirumala, Intel Corp.
John Jackson, Sematech K. D. Vance, NCR Corp.
John Hoback, Amoco Chemical H. Waltersdorf, Thomas & Betts Corp.
Albert Holliday, AT&T Bell Labs John Yantis, Texas Instruments

A special note of appreciation goes to the representatives of Intel who provided resources for a
great deal of information regarding the subject of this publication, and to Motorola whose engineer-
ing personnel provided copies of their BGA mounting methodologies.
ii
Copyright © 1996, IPC; 1998, IEC
July 1996 J-STD-013
Table of Contents
4.1.1 Physical Properties. 25
1 SCOPE. 1

4.1.2 Bump/Termination Layout. 26
1.1 Purpose. 1
4.1.3 Standardization. 27

1.2 Categorization . 1
4.2. BGA Types. 27

1.3 Presentation. 1
4.2.1 Plastic BGA . 28

1.4 Producibility Levels. 1
4.2.2 Thermally Enhanced BGA . 29

2 TECHNOLOGY OVERVIEW OF BOARD 4.2.3 Tab BGA . 29
AND ASSEMBLY REQUIREMENTS . 3

4.2.4 Mini BGA . 30
2.1 The Drivers for Component Packaging . 4
4.2.5 Micro BGA . 30
2.1.1 The Thermal Drivers . 4
4.2.6 Ceramic Ball Grid Array (CBGA) . 30
2.1.2 The Electric Drivers . 5
4.3 Material Decisions . 31
2.1.3 The Real Estate Drivers . 5
4.3.1 Thin Film Redistribution . 32
2.1.4 Specific Package Drivers. 6
4.3.2 Coplanarity. 32
2.2 Issues in Component Packaging. 7
4.3.3 ‘‘Popcorning Effect’’ Failure . 32
2.2.1
Future Considerations. 7
4.4 Area Array Selection Process. 32
2.3 Impact on Interconnecting (Printed Board)
4.4.1 Device Outlines. 32
Technology. 8
4.4.2 Array Population. 33
2.4
Impact on Assembly . 9
4.5 Peripheral Lead Package Descriptions. 33
2.5 Future Implementation Strategies. 11
4.5.1 Lead Pitch Parameters . 34
2.5.1
Complexity Matrix. 12
4.5.2 Standard SMT. 35
3 COMPONENT PACKAGES. 13
4.5.3 Fine Pitch Packages. 35
3.1 Component Identification . 13
4.5.4 Ultra Fine Pitch Packages . 35
3.1.1 Area Array Component Types. 13
4.6 Sockets . 35
3.1.2 Peripheral Leaded Devices Packages. 13
4.6.1 ZIF Sockets. 36
3.1.3 Component Marking. 14 4.6.2 LIF Sockets. 36
3.2 Component Materials. 14
5 INTERCONNECTING STRUCTURES . 36
3.2.1 Ball/Column Termination . 15
5.1 Interconnecting Structure Descriptions . 36
3.2.2 Terminations Leads. 15
5.1.1 Rigid Printed Boards . 37
3.2.3
Plating and Coating Technologies. 15
5.1.2 Flexible Printed Wiring Boards. 38
3.2.4 Process Comparisons . 16
5.1.3 Encapsulated Discrete Wire Interconnection
Boards . 40
3.2.5
Plastic Packages. 16
5.1.4 Nonorganic (Ceramic) Structures. 40
3.2.6 Ceramic Packages . 17

5.2 Material Selection . 42
3.2.7
Die Attach . 17
5.2.1 Reinforcement Material Properties. 42
3.3 Heat Dissipation Techniques . 17
5.2.2 Resin Types. 43
...