IEC 60191-6-12:2002

Mechanical standardization of semiconductor devices - Part 6-12: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine-pitch land grid array (FLGA) - Rectangular type

Provides common outline drawings and dimensions for all types of structures and composed materials of fine-pitch land grid array whose terminal pitch is less than, or equal to, 0,80 mm and whose package body outline is rectangular.

General Information

• Status: Published
• Publication Date: 13-Jun-2002
• ICS: 31.080.01 - Semiconductor devices in general
• Technical Committee: SC 47D - Semiconductor devices packaging
• Drafting Committee: WG 2 - TC 47/SC 47D/WG 2
• Current Stage: DELPUB - Deleted Publication
• Completion Date: 08-Jun-2011

Relations

• Revised: IEC 60191-6-12:2011 - Mechanical standardization of semiconductor devices - Part 6-12: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guidelines for fine-pitch land grid array (FLGA)
• Effective Date: 05-Sep-2023

Standards Content (Sample)

INTERNATIONAL IEC
STANDARD
60191-6-12
First edition
2002-06
Mechanical standardization of semiconductor devices –
Part 6-12:
General rules for the preparation of outline drawings
of surface mounted semiconductor device packages –
Design guide for fine-pitch land grid array (FLGA) –
Rectangular type
Normalisation mécanique des dispositifs à semiconducteurs –
Partie 6-12:
Règles générales pour la préparation des dessins
d'encombrement des dispositifs à semiconducteurs
pour montage en surface –
Guide de conception pour les boîtiers FLGA
de type rectangulaire
Reference number
Publication numbering
As from 1 January 1997 all IEC publications are issued with a designation in the
60000 series. For example, IEC 34-1 is now referred to as IEC 60034-1.
Consolidated editions
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edition numbers 1.0, 1.1 and 1.2 refer, respectively, to the base publication, the
base publication incorporating amendment 1 and the base publication incorporating
amendments 1 and 2.
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INTERNATIONAL IEC
STANDARD
60191-6-12
First edition
2002-06
Mechanical standardization of semiconductor devices –
Part 6-12:
General rules for the preparation of outline drawings
of surface mounted semiconductor device packages –
Design guide for fine-pitch land grid array (FLGA) –
Rectangular type
Normalisation mécanique des dispositifs à semiconducteurs –
Partie 6-12:
Règles générales pour la préparation des dessins
d'encombrement des dispositifs à semiconducteurs
pour montage en surface –
Guide de conception pour les boîtiers FLGA
de type rectangulaire
 IEC 2002  Copyright - all rights reserved
No part of this publication may be reproduced or utilized in any form or by any means, electronic or
mechanical, including photocopying and microfilm, without permission in writing from the publisher.
International Electrotechnical Commission, 3, rue de Varembé, PO Box 131, CH-1211 Geneva 20, Switzerland
Telephone: [phone] Telefax: [phone] E-mail: [e-mail]  Web: www.iec.ch
PRICE CODE
Commission Electrotechnique Internationale
R
International Electrotechnical Commission
Международная Электротехническая Комиссия
For price, see current catalogue

– 2 – 60191-6-12 © IEC:2002(E)
CONTENTS
FOREWORD.3
INTRODUCTION.4
1 Scope.5
2 Normative references .5
3 Definitions .5
Figure 1 – Rectangular FLGA packages.6
Figure 2 – Terminal zones .7
Table 1 – Group 1: Dimensions appropriate to mounting and interchangeability.8
Table 2 – Group 2: Dimensions appropriate to mounting and gauging.11
Table 3 – Package dimensions .12
e
Table 4 – D/E, nD/nE, n max. variation –   = 0,80 mm pitch FLGA flanged type.13
Table 5 – D/E, nD/nE, n max. variation –  e  = 0,65 mm pitch FLGA flanged type.14
e
Table 6 – D/E, nD/nE, n max. variation –   = 0,50 mm pitch FLGA flanged type.15
Table 7 – D/E, nD/nE, n max. variation –  e  = 0,40 mm pitch FLGA flanged type.16
e
Table 8 – D/E, nD/nE, n max. variation –   = 0,80 mm pitch FLGA real chip size type .17
Table 9 – D/E, nD/nE, n max. variation –  e  = 0,65 mm pitch FLGA real chip size type .18
e
Table 10 – D/E, nD/nE, n max. variation –   = 0,50 mm pitch FLGA real chip size type .19
e
Table 11 – D/E, nD/nE, n max. variation –   = 0,40 mm pitch FLGA real chip size type .20

60191-6-12 © IEC:2002(E) – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
___________
MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES –
Part 6-12: General rules for the preparation of outline drawings
of surface mounted semiconductor device packages –
Design guide for fine-pitch land grid array (FLGA) –
Rectangular type
FOREWORD
1) The IEC (International Electrotechnical Commission) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of the IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, the IEC publishes International Standards. Their preparation is
entrusted to technical committees; any IEC National Committee interested in the subject dealt with may
participate in this preparatory work. International, governmental and non-governmental organizations liaising
with the IEC also participate in this preparation. The IEC collaborates closely with the International
Organization for Standardization (ISO) in accordance with conditions determined by agreement between the
two organizations.
2) The formal decisions or agreements of the IEC on technical matters express, as nearly as possible, an
international consensus of opinion on the relevant subjects since each technical committee has representation
from all interested National Committees.
3) The documents produced have the form of recommendations for international use and are published in the form
of standards, technical specifications, technical reports or guides and they are accepted by the National
Committees in that sense.
4) In order to promote international unification, IEC National Committees undertake to apply IEC International
Standards transparently to the maximum extent possible in their national and regional standards. Any
divergence between the IEC Standard and the corresponding national or regional standard shall be clearly
indicated in the latter.
5) The IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with one of its standards.
6) Attention is drawn to the possibility that some of the elements of this International Standard may be the subject
of patent rights. The IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 60191-6-12 has been prepared by subcommittee 47D: Mechanical
standardization of semiconductor devices, of IEC technical committee 47: Semiconductor
devices.
The text of this standard is based on the following documents:
FDIS Report on voting
47D/493/FDIS 47D/507/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
This publication has been drafted in accordance with the ISO/IEC Directives, Part 3.
A bilingual version of this publication may be issued at a later date.
The committee has decided that the contents of this publication will remain unchanged
until 2004. At this date, the publication will be
• reconfirmed;
• withdrawn;
• replaced by a revised edition, or
• amended.
– 4 – 60191-6-12 © IEC:2002(E)
INTRODUCTION
The demand for area array style packages exists because of the multi-functions and high
performance of electrical equipment. The objective of this design guide is to standardize
outlines and to get interchangeability of FLGA rectangular type packages. The terminal pitch
and package outlines of these fine-pitch array packages are smaller than those of LGA
packages.
60191-6-12 © IEC:2002(E) – 5 –
MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES –
Part 6-12: General rules for the preparation of outline drawings
of surface mounted semiconductor device packages –
Design guide for fine-pitch land grid array (FLGA) –
Rectangular type
1 Scope
This part of IEC 60191 provides common outline drawings and dimensions for all types of
structures and composed materials of fine-pitch land grid array (hereinafter called FLGA)
whose terminal pitch is less than, or equal to, 0,80 mm and whose package body outline is
rectangular.
2 Normative references
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document (including any amendments) applies.
IEC 60191 (all parts), Mechanical standardization of semiconductor devices
3 Definitions
For the purposes of this part of IEC 60191, the following definitions, as well as those given in
the other parts of this series, apply.
3.1
flanged type
type whose package body size (body length and width) consists of its own flange composed
around the encapsulation or lid
3.2
type of real chip size
type whose package body size (body length and width) consists of an encapsulation around
the real chip only
3.3
FLGA
packages with metal lands or metal bumps of which the terminal height is less than, or equal
to, 100 μm, and whose terminal pitch is less than, or equal to, 0,80 mm, positioned in an array
on the base plane of the package as external terminals
This package structure makes it possible to surface-mount the packages to the printed circuit board.
3.4
material designation
FLGA packages are classified according to the following two material designations:
3.4.1
plastic type (P-FLGA)
plastic-type classification is assigned to packages which consist of resin substrate as
interposer material (for example, glass-epoxy, poly-imid)
3.4.2
ceramic type (C-FLGA)
ceramic-type classification is assigned to packages which consist of ceramic substrate as
interposer material
– 6 – 60191-6-12 © IEC:2002(E)
E
w
SB
NOTE 2
NOTE 3
4 ×
v
NOTE 1
y
1 SSS
S
NOTE 7 y
S
eE
B
ZE
A A
1 2
NOTE 7
Even type
nD
B
A A
1 2
NOTE 7
A B
B B
1 3
NOTE 6
Odd type
B B
2 4
A A
1 2
B
B
12 3
nE NOTE 4
A A
3 4
∅b
∅X MSAB
SE
NOTE 5 IEC  1240/02
Figure 1 – Rectangular FLGA packages
SD
A
A BC
ZD
A
1 w SA
D
eD
A
60191-6-12 © IEC:2002(E) – 7 –
NOTE 1 Indicates seating plane. Seating plane is defined by the plane that the carrier contacts to the mount
surface.
NOTE 2 Indicates positional tolerance of the index mark.
NOTE 3 Bilateral tolerance zone is applied to four sides of the package body.
NOTE 4 The positional tolerances are applied to all terminals.
NOTE 5 Terminal diameter is the maximum terminal profile when the package is projected vertically from the
seating plane.
NOTE 6      and     SD SE are stipulated the position of closest terminal with respect to datum lines    and    .A B
NOTE 7 Datum     and     are tA B he axes defined by the centres of the opposite package sides of the ball. The
definition of the centre applies to “Odd type” and “Even type”.
e
SE
IEC  1241/02
NOTE As foot circuit pattern design reference, the zone in which the terminals can be positioned is shown in this
figure.
Figure 2 – Terminal zones
e
SD
∅b
– 8 – 60191-6-12 © IEC:2002(E)
Table 1 – Group 1: Dimensions appropriate to mounting and interchangeability
Dimensions in millimetres
Reference Recommended
Name Stipulations Supplement
symbol value
Nominal Flanged type –E < D
E × D
dimension is not defined
The combination of one digit below decimal
point of package width E and package length D
is considered as the nominal dimension
Type of real chip size
The combination of two digits below decimal
point of package width E and package length D
is considered as the nominal dimension
Package D 1) Flanged type –
length
Package length: Dnom
D = 1,5, 2,0, 2,5, 3,0, 3,5, 4,0, 4,5, 5,0, 5,5,
6,0, 6,5, 7,0, 7,5, 8,0, 8,5, 9,0, 9,5, 10,0,
10,5, 11,0, 11,5, 12,0, 12,5, 13,0, 13,5,
14,0, 14,5, 15,0, 15,5, 16,0, 16,5, 17,0,
17,5, 18,0, 18,5, 19,0, 19,5, 20,0, 20,5,
21,0
2) Type of real chip size Dimension
range shows
Package length: Dnom
nominal
value
D = From 1,5 to 21,0
Package E 1) Flanged type –
width
Package width: Enom
E = 1,5, 2,0, 2,5, 3,0, 3,5, 4,0, 4,5, 5,0, 5,5,
6,0, 6,5, 7,0, 7,5, 8,0, 8,5, 9,0, 9,5, 10,0,
10,5, 11,0, 11,5, 12,0, 12,5, 13,0, 13,5,
14,0, 14,5, 15,0, 15,5, 16,0, 16,5, 17,0,
17,5, 18,0, 18,5, 19,0, 19,5, 20,0, 20,5,
21,0
2) Type of real chip size Dimension
range shows
Package width: Enom
nominal
value
E = From 1,5 to 21,0
60191-6-12 © IEC:2002(E) – 9 –
Table 1 – (continued)
Reference Recommended
Name Stipulations Supplement
symbol value
Tolerance of v v = 0,15 – Include burrs
package lateral
profile
Packagew––
centre offset
e W
0,80 0,20
0,65 0,20
0,50 0,20
0,40 0,15
Mounting A – Include heat slug
height
Include package
A max.
warpage and tilt
V
...