Mechanical standardization of semiconductor devices - Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine-pitch ball grid array (FBGA)

Provides common outline drawings and dimensions for all types of structures and composed materials of fine-pitch ball grid array the terminal pitch of which is less than or equal to 0,80 mm.

General Information

Status
Published
Publication Date
26-Aug-2001
Current Stage
PPUB - Publication issued
Start Date
30-Sep-2001
Completion Date
27-Aug-2001
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IEC 60191-6-5:2001 - Mechanical standardization of semiconductor devices - Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine-pitch ball grid array (FBGA)
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INTERNATIONAL IEC
STANDARD
60191-6-5
First edition
2001-08
Mechanical standardization
of semiconductor devices –
Part 6-5:
General rules for the preparation of outline
drawings of surface mounted semiconductor
device packages –
Design guide for fine-pitch ball grid array (FBGA)
Normalisation mécanique des dispositifs à semiconducteurs
Partie 6-5:
Règles générales pour la préparation des dessins
d'encombrement des dispositifs à semiconducteurs
à montage en surface –
Guide de conception pour les boîtiers matriciels à billes
et à pas fins (FBGA)
Reference number
IEC 60191-6-5:2001(E)

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Publication numbering
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INTERNATIONAL IEC
STANDARD
60191-6-5
First edition
2001-08
Mechanical standardization
of semiconductor devices –
Part 6-5:
General rules for the preparation of outline
drawings of surface mounted semiconductor
device packages –
Design guide for fine-pitch ball grid array (FBGA)
Normalisation mécanique des dispositifs à semiconducteurs
Partie 6-5:
Règles générales pour la préparation des dessins
d'encombrement des dispositifs à semiconducteurs
à montage en surface –
Guide de conception pour les boîtiers matriciels à billes
et à pas fins (FBGA)
 IEC 2001  Copyright - all rights reserved
No part of this publication may be reproduced or utilized in any form or by any means, electronic or
mechanical, including photocopying and microfilm, without permission in writing from the publisher.
International Electrotechnical Commission 3, rue de Varembé Geneva, Switzerland
Telefax: +41 22 919 0300 e-mail: inmail@iec.ch IEC web site http://www.iec.ch
Commission Electrotechnique Internationale
PRICE CODE
K
International Electrotechnical Commission
For price, see current catalogue

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– 2 – 60191-6-5 © IEC:2001(E)
INTERNATIONAL ELECTROTECHNICAL COMMISSION
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MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES –
Part 6-5: General rules for the preparation of outline drawings
of surface mounted semiconductor device packages –
Design guide for fine-pitch ball grid array (FBGA)
FOREWORD
1) The IEC (International Electrotechnical Commission) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of the IEC is to promote
international co-operation on all questions concerning standardization in the electrical and electronic fields. To
this end and in addition to other activities, the IEC publishes International Standards. Their preparation is
entrusted to technical committees; any IEC National Committee interested in the subject dealt with may
participate in this preparatory work. International, governmental and non-governmental organizations liaising
with the IEC also participate in this preparation. The IEC collaborates closely with the International
Organization for Standardization (ISO) in accordance with conditions determined by agreement between the
two organizations.
2) The formal decisions or agreements of the IEC on technical matters express, as nearly as possible, an
i
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