Information technology — Microprocessor systems — Control and Status Registers (CSR) Architecture for microcomputer buses

Defines the address-space maps, the bus transaction sets, and the node's CSRs. Includes the format and content of the configuration ROM on the node providing the parameters necessary to autoconfigure systems with nonprocessor nodes provided by multiple vendors. The annexes provide background for understanding the usage of this CSR Archtecture specification.

Technologies de l'information — Systèmes à microprocesseurs — Architecture des registres de commande et d'état pour bus de micro-ordinateur

General Information

Status
Published
Publication Date
12-Dec-1994
Current Stage
9093 - International Standard confirmed
Completion Date
13-Jul-2018
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ISO/IEC 13213:1994 - Information technology -- Microprocessor systems -- Control and Status Registers (CSR) Architecture for microcomputer buses
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ISO/IEC 13213 : 1994
ANSVIEEE Std 1212,1994 EDITION
6. Unit architectures
6.1 Unit architecture overview
The node ’s CSRs provide Standard mechanisms for addressing, identifying, and testing hardware resources.
After the System has been initialized, most of these registers are not accessed by the I/O driver Software.
Other register sets are provided to access processor, memory, or I/O device functions; these register sets
define one or more unit architectures on the node.
The node provides address spaces that tan be mapped to a unit architecture. Most of the unit ’s registers are
expected to be mapped to a contiguous range of addresses within one of these (initial units, indirect, or
extended units) spaces. In normal Operation, each unit has its own register set, and register sets of different
units tan be accessed concurrently by their VO driver Software.
In addition, a small number of CSRs on the node may be shared by its units. A few of the CSRs are used to
route broadcast transactions (interrupts and messages) to the units through standardized CSR addresses on
the node. One of the other CSRs, STATE-CLEAR, provides unit-dependent Status bits, so the state of the
node and its attached units tan be quickly checked with one Status register read.
To facilitate understanding these shared CSR resources, the interrupt and message-passing mechanisms are
described in 6.2 and 6.3. Two of the partially standardized unit architectures (global clock and memory con-
troller) are described in 6.4 and 6.5. Subclause 6.6 illustrates how other vendor-dependent unit architecturcs
could be designed.
6.2 Interrupts
6.2.1 Interrupt-target registers
A Standard CSR address offset, INTERRUPT-TARGET, is provided to support broadcast interrupts. A write
to this address offset with the broadcast node address (node #63) is broadcast to all units on the local bus. A
write to this address offset with a directed node address is nodecast to all units on the selected node. Other
(unit-dependent) interrupt addresses may be provided for interrupts that are directed to a specific unit.
To improve efficiency and ensure forward progress, the standardized INTERRUPT~TARGET register sup-
ports the immediate acceptance of an arbitrary number of interrupt-write transactions. Although all broad-
cast interrupt events are immediately queued, the processing of the queued interrupts may be delayed (based
on vendor-dependent interrupt-processing protocols).
The INTERRUPT-TARGET register provides one bit of storage for each of 32 interrupt groups; an interrupt
is queued by setting the corresponding interrupt-group bit. Although this ensures that interrupt events tan
always be queued, there is no mechanism for determining the number of interrupt events that may have set a
shared interrupt-group bit. When interrupt-group bits are shared, other polling mechanisms are needed to
determine the Source of the broadcast interrupt or to provide interrupt-service-routine Parameters.
To ensure interoperability among processors and I/O controllers provided by different vendors, the CSR
Architecture also restricts the functionality of directed interrupt registers. Directed interrupts are constrained
to be write4 transactions, whose address is a register within the vendor-defined processor unit architecture
(note that a 64-bit address may sometimes be needed to address this register).
As with all CSRs, congested processors may assert a busy Status to delay the acceptance of directed inter-
rupts until storage space is available. However, to avoid the generation of System deadlocks, the processor is
not expected to additionally delay the acceptance of the interrupt until other bus transactions are completed.
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ISO/IEC 13213 : 1994
CONTROLAND STATUS REGISTERS (CSR)
ANSVIEEE Std 1212, 1994 EDITION
6.2.2 Interrupt-po11 registers
When multiple nodes share an interrupt-group bit, polling is required to identify the interrupt Source. Note
that polling may never be required for processors whose vendor-dependent directed-interrupt definitions
provide a sufficient number of interrupt-group bits.
To support such polling, a simple (non-DMA) node is expected to set a “Service-request” bit within its
STATE-CLEAR register before interrupting the processor. Alternatively, the processor may be programmed
to periodically po11 the STATECLEAR register of active I/O nodes.
To simplify and enhance the Performance of the interrupt dispatch routine, 16 bits within the node ’s
STATE CLEAR register are reserved for units and expected to be used for this purpose. Note that other
-
node-Status bits are included in the same register, to minimize the overhead of simultaneously checking for
other node-error conditions.
For shared interrupt-group bits, previously initialized memory tables or lists are expected to identify these
interrupting nodes. In addition to a pointer to the node ’s STATE-CLEAR register, these data structures are
expected to provide an interrupt mask value and interrupt-dispatch Parameters, as illustrated in figure 24.
(inte, rrupting devices)
.
~.‘.:.:.:.:.:.:.:.~:.:.:.:.:.:.:.~:.:.:.:.:.:.:,~:.:.:.~:.:.:.:.:.:
. .‘. .,.,.~.~.,.,.,.,.,.,.,.,.,.,.,.,.,.,.~.,.,.,.~.,.,.,.,.,.,.,.,.,
. .~~ii.,.,.*. .’ .,.,.,.,.,.,.,.,.,.,.,.,.,.~.,.,.,.,.,.,.,.,.~.,.,.,.,.,.~.,.,.,.,.,.
. .’ .,.,.,.,.,._.,.,.,.,.,.,.~.~.~.~.,.,.,.,.,.,.,.,.,.,.,.,.~.,.,.,.,.,.
. .’ .~.~.~~~~,.,.~.,.~.~~~.~.~.,.,.~~,.~~,~,.~.,.~.,.,.,~,~,~~~~~~~~.~.
....’ .,.,.,.,.,.,.,.,.,.,.,.,.,...~.,.,.,.,.,.,.,.,.,.,.,.,.,,,.,.,.,.~.,.
i>: .,.,.,.,.,.,.,.,.,.,.,.~.~.~.,.,.,,,.,.,.,.,.~.,.,.,.,.~.,.,.,.~.,. + STATi CLiAR -
. . . ,. ,. .,.,.,.,.,.~.,.,.,.,.,.,.,.,.,.,.~.~.~., ,.,.,.,.,. -
‘X .,.,.,.~.,.,.,.,.,.,.,.,.~.,.,.,.,.,,~.,.~.~.~.~.,.,.,.,.~.~.,.,.,.
node[A]
---i) STATE CLEAR
-
node[B]
., .,.,. .,.,.,.,.,.,.~.,.,.,.~.,.~.,.~.,.~.,. _. ,. ,. .,.,.,.,.,.
..:.:.:.: .,.,._.,...,.,.,.,.,. *.*._.* .,.,.I.,.,...,...,.,.,...,.,.,.,.,.,.
.:_~:.:.:.:.:.:_:.~.~.~.~.~.~.~.~.~.~.:.~~.~.~.~.~.~,~.~~.~.~.~.~.~,~.~
w STATE CLEAR
-
node[C]
next
node
mask
dispatch
information
Figure 24-Polled-CSR interrupt dispatch model
An interrupting node produces a nonzero value when its STATE-CLEAR register is ANDed with its speci-
fied mask value. After the interrupting node has been identified, the selected Status bits tan be cleared by
writing this nonzero value to the STATE-CLEAR register. The location, format, and functionality of the
STATE-CLEAR register is standardized, to improve the Performance of the latency-sensitive interrupt-poll-
ing softwar-e.
40

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ISO/IEC 13213 : 1994
ARCHITECTURE FOR MICROCOMPUTER BUSES ANSVIEEE Std 1212, 1994 EDITION
For higher-Performance nodes with processor or DMA-like capabilities, the interrupting node tan return
completion-Status reports to arrays or queues in memory. Nodes sharing one interrupt-group bit could share
one completion-Status list; each interrupt-group bit and its corresponding completion-Status list could corre-
spond to a different interrupt priority level. However, the details of these DMA-related data structures are
beyond the scope of the CSR Architecture.
6.3 Message passing
Two Standard CSR address offsets are provided to support broadcast message passing. A write to either of
these address offsets with the broadcast node address (node [63]) is broadcast to all units on the local bus. A
write to either of these address offsets within a directed node address is nodecast to all units on the selected
no&. Other unit-dependent message-passing addresses may be provided for messages that are directed to a
specific unit.
Properly sized and aligned write transactions to these target addresses shall return a done correct (if mes-
-
sage queue space is available) or a codicterror Status (if no message queue space is available). All mes-
sage-passing nodes are required to support 64-byte messages. Nodes may optionally support other message
sizes (such as 16 or 256 bytes) as well, but larger message sizes are not transported indivisibly across all
Standard buses.
Separate target addresses are provided for request and response messages, to avoid message-queue dead-
locks. A request message is defined as a message that could generate one or more response messages when
processed. A response message never generates additional messages when being processed. Request and
response messages may be directed to the MESSAGEREQUEST address. Only response messages shall be
directed to the MESSAGE RESPONSE address.
-
Hardware is expected to provide a minimum of one queue entry for each message-passing address. The
queue entry is updated and inserted into one of two message-received queues by writing to the correspond-
ing message-passing address. The queues are emptied by processor firmware or Software, which processes
the queued messages. The protocols used by the processors to empty and interpret the contents of these mes-
sages are beyond the scope of the CSR Architecture.
Several techniques tan be used to transfer larger messages using the 64-byte message-transfer primitives:
Concatenated messages. The larger message is Split into smaller 64-byte messages. Messages con-
a>
tain identifiers that distinguish among the parts of the large message and smaller messages that may
be concurrently accepted.
b) Indirect messages. The small message provides the address of a larger message, which tan be
DMA ’d from memory-mapped data structures.
The format and meaning of 64-byte messages, as well as the techniques used to transmit large messages, are
beyond the scope of the CSR Architecture.
6.4 Globally synchronized clocks
6.4.1 Glock overview
A bus Standard may provide support for physically distributed yet globally synchronized clocks. Since the
synchronization process involves a broadcast address and the clock values have a uniform format across bus
Standards, the register interface for the clock-unit architecture is partially standardized.
Real time Systems often require a sense of the current physical time. The current time may be needed to
record the time that events occur in the external world, to measure the elapsed time between events, to con-
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ISO/IEC 13213 : 1994
ANSVIEEE Std 1212, 1994 EDITION CONTROLAND STATUS REGISTERS (CSR)
trol the sequence in which event processing takes place, or to schedule the initiation
of new events in the
external world.
When only one processor requires physical time, this Service is easily provided by a real time clock directly
accessible to the processor. Although a central clock may be highly accurate internally, its accuracy is sub-
ject to loss in transit through the bus (due to variable arbitration and transmission latencies). A central clock
also constitutes a Single Point of possible failure. Thus there is a need to provide distributed clocks for each
node, and in Order for the decentralized clocks to provide a common sense of time, the respective clocks
must be synchronized.
A clock is expected to consist of a clockvalue register and an oscillator. The clockvalue register is updated
by adding a cZock_tick value to it at the completion of each cycle of the oscillator. The clock-value register
may be initialized by Software to any value within its range. To provide a common interface, all clock values
are presented to the System scaled to the same dock-value format. The clock-vahe is represented as a 64-bit
unsigned fixed-Point number. The binary radix Point divides the 64-bit integer into two 32-bit portions. The
32-bit most-significant Portion represents seconds. The 32-bit least-significant Portion represents a binary
fraction of one second. The least-significant bit represents approximately 233 picoseconds. The 64-bit
unsigned number overflows approximately once every 136 years.
The number of oscillations per second is called the frequency or rate of the clock. The completion of one
oscillator cycle is called a tick. The tick period represents the time interval between two ticks and determines
the resolution or granularity of the clock.
6.4.2 Glock synchronization
Glock synchronization is expected to involve the following Steps:
CZock sampling. The values of all clocks are sampled at the same (or nearly the Same) time, by dis-
a>
tributing a clock-strobe Signal to all nodes on the same bus. The sampled values are saved in the
CLOCK ARRIVED registers.
-
b) Reference update. A reference clock value (which corresponds to the time of the previous
clock-strobe Signal) is calculated. The reference clock may be derived in one of two ways:
1) Master reference. The master ’s CLOCK ARRIVED register is used as the value of the refer-
-
ence time.
2) Averaged reference. The values of the CLOCK-ARFUVED registers from two or more nodes
are averaged to provide the reference time.
Glock adjustnzent. The frequencies of clocks are changed to compensate for the errors between their
C>
sampled values and the reference time. The frequency adjustments may be performed in the follow-
mg ways:
1) Master update. The Slave nodes provide external access to their clock-adjustment and clock-
calibration registers. The clock master computes the clock Slave clock errors and compensates
for these errors through writes to their clock-adjustment registers.
2) LocaZ updates. The clock master distributes the reference time (as sampled on the last
clock-strobe Signal) to the clock slaves, using directed or broadcast writes to bus-dependent
memory-mapped control registers. The clock slaves locally compensate for their own errors
based on the differentes between their internal clock value register and the reference value
-
received from the clock master.
On a traditional physically bussed bus Standard, the clock-strobe is a well-defined Phase of a write to a spe-
cific control register address. This event is nearly simultaneously observed by local nodes, which latch their
impression of the current clock value in the CLOCK-ARRIVED register, as illustrated in figure 25.
On other bus Standards based on Point-to-Point physical links, such as SCI, the clock-strobe
Signal m ust be
forwarded through multiple nodes on the ringlet. Since the time delay through each node is
variable, sepa-
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ISO/IEC 13213 : 1994
ARCHITECTURE FOR MICROCOMPUTER BUSES
ANSVIEEE Std 1212, 1994 EDITION
clock clock clock clock
arrive arrive arrive arrive
dock-strobe
Figure 25-Synchronized node clocks (broadcast backplane mode)
rate registers are required to latch the time the clock-strobe Signal arrives and the accumulated time between
its arrival and departure (delta). Only the nodes with local clocks are required to have an arrival-time regis-
ter, but (to accurately synchronize clocks) all nodes are required to provide the delta register. These registers
are illustrated in figure 26.
clock clock clock clock
delta arrive delta arrive delta arrive delta arrive
dock-strobe
Figure 26-Synchronized clocks (pipelined backplane model)
The delta register capability may also be used on bridges between buses, to calibrate the time taken by the
clock-strobe Signal when passing through the bridge. However, the detailed functionality and format of the
delta registers are beyond the scope of the CSR Architecture.
6.4.3 Glock update models
Several of the (optional) clock registers are needed to support a master update clock adjustment model. Six
of the clock-related registers have Standard formats and meanings; four of the clock-related registers are
reserved for bus-dependent uses. The optionality of these ten clock-related registers, as well as additional
definitional details, are bus-dependent.
The CLOCK VALUE registers are used to initialize and monitor the current clock value, the
-
CLOCK TICK PERIOD registers are used to adjust the current clock value, and the
- -
CLOCK~STROBEJARRIVED registers are used to calibrate the current clock value. The definition of these
registers is based on the clock design model illustrated in figure 27.
The upper 64 bits of the clock-value register are externally visible as the CLOCK VALUE register pair. In
-
figure 27, these registers are not shaded, to illustrate that register storage is not required to provide access to
the internal clock-value register value. The clock-value register is expected to have additional less-signifi-
cant bits, which cannot be accessed directly through CSR registers.
Although 32 least-significant bits of clock-value register are architecturally supported, an implementation
may omit unnecessary least-significant bits in the adder and clock-value registers; the shading of these com-
ponents is intended to illustrate this optionality. However, the resolution in the register and adder shall be
sufficient to meet the node ’s clock-adjustment accuracy specification.
The adder is used to compute the next clock-value register value, which is updated at each tick of the oscil-
lator. The differente between new and old values of the clock-value register is determined by the pair of
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ISO/IEC 13213 : 1994
CONTROLAND STATUS REGISTERS (CSR)
ANSVIEEE Std 1212, 1994 EDITION
hi 1 midl
CLOCKVALUE-Hl
CLOCK-VALUE-LO
Figure 27-Synchronized clock registers
CLOCK TICK-PERIOD CSRs, which supply the middle-significant and least-significant quadlets of the
-
added value, respectively (the most-significant quadlet of the added value is Zero). Software is expected to
control the rate of the clock-value increase by setting the values in the CLOCK-TICK-PERIOD registers.
The CLOCK STROBE ARRIVED registers record the value of CLOCKJALUE during the time that a
- -
strobe Signal is observed on the bus. The CLOCK-STROBE-ARRIVED-MID register is sufficient to detect
synchronization error differentes up to half of a second; the CLOCK-STROBE-ARRIVED-HI register is
needed to detect synchronization error differentes that may be larger than half a second.
A bus Standard may also support a local-update clock-adjustment model. Although a similar implementation
model is expected, a local-update node is not required to provide CSR access to these resources; the details
of their implementation are beyond the scope of the CSR Architecture.
6.4.4 Updating clock registers
Software is expected to use sequences of 32-bit accesses to access the larger 64-bit clock-register values.
Although this complicates some of the register-access protocols, supporting the larger 64-bit read and write
transactions would complicate the hardware designs.
Reading the CLOCK VALUE register is expected to involve three reads of two quadlet registers. Software
-
reads the CLOCKJALUE-HI register and the CLOCKJALUE-MID register before re-reading the
CLOCK_vALuE_HI register. If the first and second values read from CLOCKJALUE~HI are different (a
carry condition), the second CLOCKJALUE-HI time is used and the previously read value of
CLOCK VALUEMID is cleared. The resultant 64-bit time value reflects a valid time between the first and
-
second read of the CLOCKJALUE-HI register.
Writing the CLOCK-VALUE register is expected to involve two quadlet register writes. Software is
expected to set the time by writing zero to the CLOCKJALUE-MID register and time value to the
VALUE-HI register when the time is an integer multiple of seconds. Since the CLOCK VALUE
CLOCK -
-
register need only be updated when the System is initialized, these difficulties in accurately setting the initial
time value do not complicate the on-line use of these registers.
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ISO/IEC 13213 : 1994
ARCHITECTURE FOR MICROCOMPUTER BUSES ANSVIEEE Std 1212, 1994 EDITION
Writing the CLOCK TICK PERIODMID register is expected to involve two quadlet register writes. Soft-
-
-
ware is expected to write to the GLOCKTICK-PERIOD-MID register before writing to the
CLOCK TICK PERIOD LO register. The second write simultaneously
updates the
- - -
CLOCK~TICK~PERIOD~LO register and transfers the value of the CLOCK-TICK-PERIOD
MID regis-
-
ter to the internal tick-mid register.
6.4.5 Glock accuracy requirements
The clock-calibration and clock-adjustment protocols shall minimally meet the following functional require-
ments (tighter restrictions on accuracy and drift may be specified by the bus Standard):
CZock tick period. The internal clock-value register shall be updated at a nominal frequency of no
a>
slower than once per microsecond.
b) CZuck tick resolution. The effective resolution of the clock-adjustment protocol shall be sufficient to
adjust the clock drift rate to within 10 Parts per million.
Oscillator accuracy. The frequency accuracy of the clock shall be 100 Parts per million or less in the
C)
product ’s operating environment.
6.5 Memory unit architectures
The CSR Architecture provides the framework for the definition of memory unit architectures and constrains
or supports its definition in the following ways:
Read and write transaction set. The CSR Architecture defines Standard transactions that shall be
a>
implemented within the extended memory address space (see 3.2). The memory unit architecture
may optionally support locks (see 3.3) or other bus-dependent transactions as well.
b) RAM addressing. The node provides MEMORY-BASE and MEMORY BOUND registers that
-
define the base and bound of the node ’s extended memory space. Addresses within this space are
mapped through the node and processed by the memory unit.
Address-space constraints. The node ’s ROM provides Standard mechanisms for specifying the align-
4
ment and size requirements for the node ’s extended memory space (see 8.4.14).
A memory Controller with error-detection circuitry (EDC) tan detect errors; a memory Controller with error-
correction circuitry (ECC) tan also correct errors. A memory unit is expected to log detected and corrected
errors in a unit-dependent error log and to set its allocated unit-dependent bit in the STATECLEAR register
when the error is logged. The location of the memory-error bit and the details of the memory controller ’s
error log are dependent on the memory-Controller architecture.
A memory unit is expected to provide a set of registers for accessing the memory-Controller functions. These
registers could be used to initialize and test the contents of RAM and to select altemate memory banks.
However, the detailed definition of these memory-unit registers is beyond the scope of the CSR Architec-
ture.
6.6 Unit architecture environment
Unit architectures may be standardized or may have vendor-dependent definitions. A unit corresponds to a
piece of I/O driver Software and (in normal Operation) the accesses to one unit do not affect the node or other
units. A unit tan be (optionally) reset without affecting the other units or the node to which it is attached.
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ISO/IEC 13213 : 1994
ANSMEEE Std 1212, 1994 EDITION CONTROLAND STATUS REGISTERS (CSR)
The node architecture provides a framework for the definition of unit architectures; this framework is sum-
marized below:
Address space. A unit (other than a memory unit) is located in a contiguous range of addresses
a>
within one of the initial units, extended units, or indirect address spaces. To support autoconfigura-
tion of the units, the offset and size of the unit ’s address space is specified by an entry in the node ’s
ROM.
Initialized states. The node command-reset and powerreset events also initialize the registers of
b)
their attached units. The initial state of the unit ’s registers is defined when the node enters the run-
ning state. Although their initial values are beyond the scope of this Standard, one of the following
conventions is expected:
1) Running. The unit architecture is minimally initialized and left in the running state. I/O driver
Software is expected to invoke a unit-specific initialization or extended test.
2) hitializing. The unit is in the initializing state and remains in this state until the initialization
test has completed. I/O driver Software is expected to po11 periodically until the initialization
test has completed.
Messages. Two Standard message-passing target addresses are defined on the node. These addresses
C)
may be used to direct a message to all units on one node or to broadcast a message to all units on the
bus.
Interrupt target. A Standard INTERRUPT-TARGET address is defined on the node. This address
4
may be used to broadcast an interrupt to all units on the bus or to send an interrupt to all units on one
node.
Znterrupt ~022. Sixteen (16) bits of a Standard interrupt-po11 register (STATE-CLEAR) may be used
e>
by unit architectures on the node. This provides one register that tan be efficiently polled to check
the unit and node states.
No-access spaces. If the optional STATE-CLEAR.Zost bit is implemented, accesses to registers in
fl
the initial units and extended units space are blocked when the node enters the initializing or dead
states. This blocks access to the unit registers after a loss of power or after fatal errors.
Power-fail warning. On Standard buses that provide centralized power, a (minimum) 4 ms power-fail
g)
warning should be provided. The warning is expected to be sufficient for most nodes to save their
critical primary state (such as processor registers) in node-local secondary state (such as battery-
backed RAM).
Nodes with requester capabilities are expected to pass the error Status of bus transactions to the units that
initiated them. Simple unit architectures (such as DMA or non-monarch-capable processors) are expected to
log the bus transaction errors and set one of their allocated bits in the STATE CLEAR register before halt-
ing. A processor is expected to periodically po11 the STATE CLEAR register to detect these halted-DMA
-
error conditions.
Polling of the STATECLEAR register tan be avoided if the unit provides a DMA heartbeat capability,
which periodically returns its Status to memory. The definition and use of such heartbeat capabilities are
unit-dependent and beyond the scope of the CSR Architecture.
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ISO/IEC 13213: 1994
ARCHITECTURE FOR MICROCOMPUTER BUSES ANSVIEEE Std 1212, 1994 EDITION
7. CSR definitions
7.1 Register names and offsets
This clause defines the format and meaning of the control and Status registers (CSRs) that provide a frame-
work for the design of vendor-dependent unit architectures (such as memory, UO, or processors).
The CSR Architecture is not intended to provide a complete register definition for all node types-the ven-
dor is expected to define additional unit-specific register Sets. The intent is to standardize the registers that
are accessed by generic Software for initializing, configuring, and testing the node. Also, the intent is to spec-
ify broadcast addresses, to avoid incorrect interpretations of broadcast transactions directed to inconsistently
defined addresses.
Many of the CSRs are optional and need not be implemented. However, other uses for a register address
shall not be defined (the behavior of an unimplemented register is exactly defined). Thus, the tost of the
implementation depends on the functionality provided by the node.
The location of a node-control register is defined by its byte-offset from the beginning of the initial register
space. The CSRs needed to support the basic and optional capabilities are listed in table 10.
Note that some of the registers are affiliated with Standard unit architectures; they provide extended address
spaces for the units (UNIT-BASE through MEMORY-BOUND), a target address for broadcastinodecast
interrupts (INTERRUPT-TMGET), target addresses for broadcastinodecast messages
(MESSAGE REQUEST or MESSAGERESPONSE), or they define a Standard unit with special broadcast
capabilities (CLOCKJALUE through CLOCK-INFO).
The ROM WINDOW specifies a range of register addresses that are mapped to the first 1 kbytes of the
-
node ’s internal address space. The first Portion of the internal address space shall contain ROM data (a min-
imum of 4 ROM bytes is required, see clause 8 for details).
A rather large space is allocated for bus-dependent registers; the bus Standard expected to define some of
these to be vendor-dependent.
The read4 transactions are supported at all CSR addresses. The write4 transactions are supported to most
CSR addresses, and the write64 transaction is supported to the message-target registers. For each of the
CSRs, table 11 lists the expected Software uses of the register (RO for read-only, WO for write-only, and RW
for read/write) and the transaction types that are supported (read4, write4, etc.).
Access to the previously listed registers is supported when the node is in the running state. When a node is in
the initializing, testing, or dead states, only limited access to the registers is supported, as described in
table 12.
Only the first quadlet address of the ROMWINDOW location always returns a defined result. A node ’s
ROM is not required to be accessible while in the initializing state; if not accessible, a read of the first
ROM WINDOW address shall return a zero value. Once the ROM WINDOW becomes accessible (a read
-
-
of the first ROMJVINDOW address returns a nonzero value), the entire 1-kbyte ROM WINDOW shall be
-
accessible while the node is in the initializing state. -
Accesses to the node ’s init
...

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