Space systems — Semiconductor integrated circuits for space applications — Design requirements

ISO 18257:2016 specifies the basic design requirements for semiconductor ICs for space applications, including its design process, as well as required tasks and requirements of each stage. Requirements of specific circuit design are not included.

Systèmes spatiaux — Circuits intégrés semi-conducteurs d'applications spatiales — Exigences de conception

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Status
Published
Publication Date
16-Nov-2016
Current Stage
9093 - International Standard confirmed
Completion Date
20-Sep-2022
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INTERNATIONAL ISO
STANDARD 18257
First edition
2016-11-15
Space systems — Semiconductor
integrated circuits for space
applications — Design requirements
Systèmes spatiaux — Circuits intégrés semi-conducteurs
d’applications spatiales — Exigences de conception
Reference number
ISO 18257:2016(E)
©
ISO 2016

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ISO 18257:2016(E)

COPYRIGHT PROTECTED DOCUMENT
© ISO 2016, Published in Switzerland
All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized otherwise in any form
or by any means, electronic or mechanical, including photocopying, or posting on the internet or an intranet, without prior
written permission. Permission can be requested from either ISO at the address below or ISO’s member body in the country of
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ISO 18257:2016(E)

Contents Page
Foreword .iv
Introduction .v
1 Scope . 1
2 Normative references . 1
3 Terms and definitions . 1
4 Abbreviated terms . 2
5 General requirements . 2
6 Design process . 3
6.1 Overview . 3
6.2 Design input . 5
6.3 Design phases and tasks . 6
6.3.1 Architecture design . 6
6.3.2 Logic design and circuit design . 7
6.3.3 Layout design . 8
6.4 Mask making, package and testing .10
7 Detailed requirements .10
7.1 Architectural design requirements .10
7.2 Logic design and circuit design requirements .10
7.3 Layout design requirements .11
7.4 Package design requirements .11
7.4.1 Package structure design requirements .11
7.4.2 Packaging technology design requirements .12
7.4.3 Packaging electrical simulation analysis requirements .12
7.4.4 Packaging thermal simulation analysis .12
7.5 Reliability design requirements .12
7.5.1 Overview .12
7.5.2 Reliability design requirements .13
7.5.3 Antistatic design requirements .13
7.5.4 Low-power design requirements .13
7.5.5 Parameter modification and design margin optimization requirements .14
7.5.6 Electromagnetic compatibility design requirements .14
7.5.7 Radiation-hardened design requirements .14
7.6 Testability design requirements .15
Annex A (normative) Datasheet .16
Annex B (informative) Guidance .17
Bibliography .24
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ISO 18257:2016(E)

Foreword
ISO (the International Organization for Standardization) is a worldwide federation of national standards
bodies (ISO member bodies). The work of preparing International Standards is normally carried out
through ISO technical committees. Each member body interested in a subject for which a technical
committee has been established has the right to be represented on that committee. International
organizations, governmental and non-governmental, in liaison with ISO, also take part in the work.
ISO collaborates closely with the International Electrotechnical Commission (IEC) on all matters of
electrotechnical standardization.
The procedures used to develop this document and those intended for its further maintenance are
described in the ISO/IEC Directives, Part 1. In particular, the different approval criteria needed for the
different types of ISO documents should be noted. This document was drafted in accordance with the
editorial rules of the ISO/IEC Directives, Part 2 (see www.iso.org/directives).
Attention is drawn to the possibility that some of the elements of this document may be the subject of
patent rights. ISO shall not be held responsible for identifying any or all such patent rights. Details of
any patent rights identified during the development of the document will be in the Introduction and/or
on the ISO list of patent declarations received (see www.iso.org/patents).
Any trade name used in this document is information given for the convenience of users and does not
constitute an endorsement.
For an explanation on the meaning of ISO specific terms and expressions related to conformity assessment,
as well as information about ISO’s adherence to the World Trade Organization (WTO) principles in the
Technical Barriers to Trade (TBT) see the following URL: www.iso.org/iso/foreword.html.
The committee responsible for this document is ISO/TC 20, Aircraft and space vehicles, Subcommittee
SC 14, Space systems and operations.
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ISO 18257:2016(E)

Introduction
Normative design requirements of semiconductor integrated circuits for space applications largely
determine the reliability of an integrated circuit (IC) and its adaptability to space environment, thereby
affecting the reliability of space systems. IC tests and experiments based on product specification
only can provide a comprehensive evaluation of its reliability. Once applied to space systems, the
design flaws will directly affect the implementation of aerospace engineering. The development of
design requirements for semiconductor ICs for space applications can ensure its reliability and space
suitability from its very source to meet the space application requirements.
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INTERNATIONAL STANDARD ISO 18257:2016(E)
Space systems — Semiconductor integrated circuits for
space applications — Design requirements
1 Scope
This document specifies the basic design requirements for semiconductor ICs for space applications,
including its design process, as well as required tasks and requirements of each stage. Requirements of
specific circuit design are not included.
2 Normative references
The following documents are referred to in text in such a way that some or all of their content
constitutes requirements of this document. For dated references, only the edition cited applies. For
undated references, the latest edition of the referenced document (including any amendments) applies.
IEC 61967-2, Integrated circuits — Measurement of electromagnetic emissions
IEC 62132, Integrated circuits — Measurement of electromagnetic immunity
IEC 62215-3:2013, Integrated circuits — Measurement of impulse immunity — Part 3: Non-synchronous
transient injection method
IEEE 1149.1, IEEE standard for test access port and boundary — Scan architecture
3 Terms and definitions
For the purposes of this document, the terms defined in ISO 10795 and the following apply.
ISO and IEC maintain terminological databases for use in standardization at the following addresses:
— IEC Electropedia: available at http://www.electropedia.org/
— ISO Online browsing platform: available at http://www.iso.org/obp
3.1
programmable logic device
PLD
hardware-programmable device
EXAMPLE FPGA, CPLD, etc.
3.2
suitability
degree to which a product meets its requirements
3.3
environment adaptability
ability to achieve the entire product’s intended functions, performance and (or) capacity for protecting
itself under various environments within its life cycle
3.4
testability
ability to perform function and performance testing of the circuit, position the failure of the circuit and
select qualified circuit chip as soon as possible
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ISO 18257:2016(E)

4 Abbreviated terms
ASIC application specific integrated circuit
BIST built-in self test
CMOS complementary metal oxide semiconductor
DFT design for test
DRC design rule checking
EMC electro-magnetic compatibility
ERC electrical rule checking
ESD electrostatic discharge
FPGA field programmable gate array
IC integrated circuit
I/O input/output
IP intellectual property
JFET junction field effect transistor
MOSFET metallic oxide semiconductor field effect transistor
NMOS N-channel metal oxide semiconductor
RAM random access memory
RC resistance capacitance
ROM read only memory
RTL register transfer level
SAR ADC successive approximation register analogue digital converter
SCR silicon controlled rectifier
SEL single event latch-up
SET single event transient
SEU single event upset
SOI silicon on insulator
SOS silicon on sapphire
5 General requirements
General requirements in designing semiconductor ICs for space applications include:
a) process conducted under a fault-tolerant system with design requirements;
NOTE 1 Special implements are allowed for different types of ICs for space applications.
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b) adherence to existing standards and regulations during the design process;
c) feasibility and risk analysis of requirements from aerospace customer to validate the rationality of
its functional and performance requirements;
d) conversion of users’ requirements into design input, which may involve the following steps:
1) derating the design criteria;
NOTE 2 Derate on the basis of nominal stress according to the stress of the circuit. The key is the level and
effects. Derating can improve reliability, but takes into consideration issues such as reliability, size, weight
and cost.
2) applying fault-tolerant design and adopting rational use of redundant technology;
3) ensuring the characteristics of the orbit thermal environment for reliable thermal design;
4) considering radiation hardness to ensure grade requirements, if necessary;
5) taking note of the life of customer’s requirements (mean time to failure);
e) decomposition of the design input requirements to each design stage according to its tasks.
NOTE 3 Implement and validate each step until all objectives and requirements of a semiconductor IC for
space applications are achieved.
6 Design process
6.1 Overview
IC designs generally include architecture design, logic design, circuit design and layout design. In order
to ensure the validity of the design, computer simulation and verification of its results at each stage are
necessary. Figure 1 illustrates the IC design flow.
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Figure 1 — Integrated circuit design flow diagram
In designing semiconductor ICs for space applications, designers have to follow a general IC design
process to convert users’ general and special requirements (i.e. user-oriented features, performance
and reliability requirements, etc.) into design input, thereby accomplishing the design goals of each
stage to meet the overall requirements. Figure 2 illustrates the decomposition of tasks in the design
process of semiconductor IC for space applications.
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ISO 18257:2016(E)



Figure 2 — Decomposition of tasks in designing semiconductor IC for space applications
6.2 Design input
A design input document will be formed after completing the requirements definition. Design input
generally includes (modifications are allowed according to specific circuit requirements) the following:
a) system division, system configuration and operating mode;
b) system interface, external device communication protocols, including memory-mapped register;
c) operating frequency range;
d) constraints of electrical parameter;
e) functional requirements;
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f) application algorithm;
g) reset and power dissipation requirements;
h) error handling;
i) testing mode;
j) fault coverage requirements of digital circuit testing;
k) key signal timing;
l) constraints of the normal working environment;
m) constraints of the special space working environment, which includes
1) space radiation,
2) heat dissipation in vacuum, and
3) in-space charging effects (i.e. ESD, latch-up);
n) power dissipation budget;
o) physical and mechanical constraints include: pin distribution, size, packaging;
p) reusability and additional features of the product;
q) new technologies;
r) intellectual property of design;
s) IP cores that are necessary and with verification.
6.3 Design phases and tasks
6.3.1 Architecture design
6.3.1.1 Overview
Finding an architecture design that offers efficient functionality at minimal cost, while meeting users’
objectives and constraints, is important.
6.3.1.2 Design content
The following is the architecture design process.
a) Define the chip architecture, verify and record the completion of functions of the basic module, as
well as interfaces and interactions.
b) Select and validate the chip architecture.
c) Ensure that all definitions and selections are in accordance with the documents made in the
definition phase.
d) Ensure that the output includes:
1) a simulation model,
2) the results verification, and
3) a preliminary datasheet.
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The datasheet shall conform to the requirements of Annex A.
Verification: For example, complex digital circuit research and development will be realized through
FPGA sample or tested by simulation; digital circuit code coverage requirements; requirements for
hardware and software interaction; applications of the code rules.
6.3.1.3 Design verification
The following is the architectural design verification process.
a) Verify whether the defined architecture meets demands through appropriate simulation and
analysis techniques.
b) Complete independent verification.
c) Finish the primary placement and routing after the hardware unit is connected, making sure each
unit is placed effectively under the given constraints.
NOTE Does not apply to PLD design.
d) Put in place a back-up plan, in case conflicts occur (i.e. power dissipation and speed, performance,
pin number and package size, complexity and area).
e) Establish a final system design.
f) Complete the initial datasheet.
6.3.2 Logic design and circuit design
6.3.2.1 Overview
In this stage, the high-level system design is transmitted and transformed to unit-level architecture
description with the chosen technology library, and the input information of the next phase, such as
layout constraints, placement and routing, and product testing and detailed pin description, etc. are
generated. Logic design and circuit design are included. For digital circuits, verified gate-level netlist is
generated; while for analogue circuit, verified transistor-level netlist is generated.
6.3.2.2 Design content
The following is the logic design and circuit design process.
a) Provide complete details of the circuit architecture.
b) Identify testability description and product testing methods, including extent of fault coverage.
c) Identify circuit and layout, which are considered together for simulation design.
d) Test concept of definition during design input and synthesis stage (i.e. scan path, testability logic,
test points, test bus and boundary scan).
e) Identify radiation-hardened concept through design and synthesis stage, when applicable.
f) Implement step-by-step verification plans and verify the results obtained.
g) Validate pin leads and connection plans, paying special attention to technical constraints (i.e. power
dissipation supply and pin definition).
h) Select buffers according to I/O requirements.
i) Ensure that output includes
1) updated datasheet (including output pin), and
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2) updated design database (including netlist, layout constraints, product testing and testing
vectors).
6.3.2.3 Design verification
The following is the logic design and circuit design verification process.
a) Verify parasitic data and delay data of the assessment layout.
b) Use the testing method from system design to complete the gate-level simulation, such as formal
verification and static timing analysis.
NOTE 1 Does not apply to pure analogue circuits, but applies to digital parts of a hybrid circuit, such as
A/D converter and D/A converter.
c) Verify critical parameters such as bias voltage, operating point, frequency, dynamic, linear range,
and modify the timing.
d) Complete functional verification, including verification of interface.
NOTE 2 It applies to analogue circuit design and analogue part of a hybrid circuit.
e) If the simulation of the whole mode cannot be completed at the top level (such as operating time
limit), simulation of typical mode is allowed.
f) From the results of simulation of a typical model, verification and analysis can be applied to
other models.
g) Verify the realized testing concepts, such as scan path design, testability design DFT logic,
measurement points and test bus.
h) Verify the radiation-hardened concept at the netlist level.
i) Verify defined typical power dissipation.
j) Upload the parameters of the preliminary datasheet according to results obtained.
k) Generate test vectors and verify the fault coverage requirements.
l) Complete parameter sensitivity analysis.
NOTE 3 It applies to analogue circuit design and analogue part of a hybrid circuit.
6.3.3 Layout design
6.3.3.1 Overview
Transforming a circuit design into a layout design, as well as its verification, are important parts in the
physical realization of an IC design, serving as the transition from the design phase to its manufacture.
6.3.3.2 Design content
The following is the layout design process.
a) Determine chip placement.
NOTE 1 This does not apply to PLDs.
b) Complete the placement and routing, ensuring that all constraints are considered.
c) Complete netlist optimization according to timing and design rules.
NOTE 2 Only applies to digital ASIC design.
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d) Generate power dissipation distribution.
e) Generate clock distribution.
NOTE 3 Does not apply to analogue ASIC design.
f) Insert core and pad power, as well as other testing pins.
g) Determine the size of die.
NOTE 4 Does not apply to PLD design.
h) Generate a bonding diagram, ensuring that constraints of package wire are considered.
NOTE 5 Does not apply to PLD design.
i) Ensure that the output contains
1) an updated datasheet,
2) an updated design database (including layout imitation netlist of the target requirements and
related parasitic information), and
3) a draft detail specification.
6.3.3.3 Design verification
The following is the layout verification process.
a) Perform a design rule checking (DRC).
b) Perform an electrical rule checking (ERC) if user requests and crosstalk sensitivity shall be checked
as well.
c) Extract the netlist from the layout.
d) Verify the consistency between the gate-level netlist and the layout by comparing the layout and
the circuit schematic.
e) Verify the functional consistency between the pre-layout netlist and the post-layout netlist through
simulation and formal methods.
f) Extract parasitic information.
g) Complete the comprehensive layout verification through anti-standard simulation and timing
analysis.
h) Check clock jitter and delay.
NOTE 1 Does not apply to PLD design.
i) Check I/O-related timing.
j) Check chip power dissipation.
NOTE 2 Does not apply to PLD design.
k) Describe timing performance of the circuit (i.e. maximum clock frequency, clock duty factor, input
set-up and its holding time, output propagation delay).
l) Update the data table.
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6.4 Mask making, package and testing
Once the design is complete, prototype manufacturing begins. It involves mask making, package and
testing. The following is the prototype manufacturing process.
a) Transform correct layout data into data format that is acceptable to the mask system.
b) Submit basic device electrical parameters and process parameter documents according to design
requirements for manufacturers to produce and package.
c) Test circuit function and its performance parameters by conducting irradiation tests and reliability
tests according to requirements of the detail specification to ensure that the product meets the
requirements.
7 Detailed requirements
7.1 Architectural design requirements
The detailed architectural design requirements are provided in the list below, while the design guidance
is provided in Annex B.
Architectural design requirements include:
a) semiconductor chips subdivided into basic functions or modules, with each interface, function and
interaction identified and recorded;
b) architecture definition divided into process definition, transistor-level or gate-level mapping;
c) algorithm and schematics, including realization of functional parameters;
d) independent chip modules at different positions with each sub-function identified;
NOTE Sub-functions can be compiled as core against other designs.
e) clock reset program to ensure correct data transmission of clock domains and asynchronous
clock part;
f) generated model as input for subsequent detailed design.
7.2 Logic design and circuit design requirements
Code design shall meet the following specifications when designing digital circuits.
a) Initial ports state shall be stable and informed.
b) Comprehensive design principles shall
1) avoid level-sensitive transparent latches and combination of feedback loops when describing
combinational logic,
2) have individual temporal logic blocks that can only be triggered by one clock transition within
each timing logic block, and
3) employ synchronous design when describing the design.
c) Asynchronous logic shall be avoided when designing register transfer level (RTL) code. If
asynchronous logic has to be employed, synchronizer among asynchronous interfaces is needed to
ensure reliability of the design.
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d) An internal logic unit clock generated by employing independent clock management unit, which
supports independent reset unit to synchronize the reset input signal in generating the required
reset signal of the internal logic unit.
e) Internal logic unit shall prohibit the use of tri-state bus and combined ring to ensure higher testing
coverage of DFT design and circuit reliability.
7.3 Layout design requirements
Layout design requirements include:
a) a reliable circuit with the smallest footprint;
b) layout design that meets process design regulations from technology vendors;
c) die corner design, die seal ring design, wide metal slotting and other design criteria with the
following specifications:
1) die corner with a 45° metal wiring in chip corner;
NOTE 1 The size of the die corner is determined by chip size.
2) die seal ring (from substrate to pdiff, contact, metal1, via1 until the highest level of metal) to
protect the chip against the blade when cutting;
3) wide metal slotting with 45° corner to alleviate the pressure caused by current density in the
metal (slotted placement shall be consistent with current direction);
d) placement and routing that addresses signal harassment;
NOTE 2 Follow the principle of reducing parasitic parameters.
e) overall chip power design that employs vertical and horizontal grid wiring to ensure that every
memory bit could obtain V and V from the power grid;
DD SS
NOTE 3 Design the power cord width of the word line direction according to the array stored number to
achieve the supply capacity when all units operating line are open at the same time.
f) trace width spacing, through-hole diameter and hole line spacing that minimize trace lengths and
number of through-holes.
7.4 Package design requirements
7.4.1 Package structure design requirements
Package structure design requirements include:
a) an adhesive or bonding surface on the package, the size of which is determined according to the
chip size;
NOTE 1 Ensure that there is enough space so that the bonding process does not affect the chip’s electrical
performance.
b) bonding wires configured according to pad size, pitch and pin orientation;
NOTE 2 Ensure that functional pads can be smoothly extracted and step width between bonding wires
meet bonding requirements.
c) melt seal ring that matches the size of the case and meets requirements;
d) case thickness that ensures mechanical strength.
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