ISO/IEC 15205:2000

SBus — Chip and module interconnect bus

SBus is a high performance computer I/O interface for connecting integrated circuits and SBus Cards to a computer system motherboard. This standard defines the mechanical, electrical, environmental, and protocol requirements for the design of SBus Cards and the computer system motherboard that supports those cards. Every SBus Card shall implement appropriate self-descriptive and initialization firmware using FCode, which is similar to the Forth programming language. The details of this firmware standard are beyond the scope of this standard.1) In addition, other software interfaces may be used for communication with SBus Cards. SBus is intended to provide a high performance I/O bus interface with a small mechanical form factor. The small size, high levels of integration, and low power usage of SBus Cards enable them to be used in laptop computers, compact desktop computers, and other applications requiring similar characteristics. SBus Cards are mounted in a plane parallel to the motherboard of the computer system, allowing the computer system to have a low profile. SBus is not designed as a general purpose backplane bus. SBus allows transfers to be in units of 8, 16, 32, or 64 bits. Burst transfers are allowed to further improve performance. SBus allows a number of SBus Master devices to arbitrate for access to the bus. The chosen SBus Master provides a 32-bit virtual address which the SBus Controller maps to the selection of the proper SBus Slave and the development of the 28-bit physical address for that Slave. The selected SBus Slave then performs the data transfers requested by the SBus Master. Simple SBus Cards may be designed to operate solely as Slaves on the SBus. 1.2 Normative references The following normative documents contain provisions which, through reference in this text, constitute provisions of this International Standard. For dated references, subsequent amendments to, or revisions of, any of these publications do not apply. However, parties to agreements based on this International Standard are encouraged to investigate the possibility of applying the most recent editions of the normative documents indicated below. For undated references, the latest edition of the normative document referred to applies. Members of IEC and ISO maintain registers of currently valid International Standards. IEEE Std 1275:1994, IEEE Standard for Boot (Initialization Configuration) Firmware: Core Requirements and Practices2) 1) A firmware interface standard is under consideration. 2) IEEE publications are available from the Institute of Electrical and Electronics Engineers, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 08855-1331, USA (standards.ieee.org/).

SBus — Norme pour bus d'interconnexion de jeton et module

General Information

• Status: Published
• Publication Date: 05-Jul-2000
• ICS: 35.160 - Microprocessor systems
• Technical Committee: ISO/IEC JTC 1/SC 25 - Interconnection of information technology equipment
• Drafting Committee: ISO/IEC JTC 1/SC 25 - Interconnection of information technology equipment
• Current Stage: 9093 - International Standard confirmed
• Completion Date: 13-Jul-2018

Standards Content (Sample)

INTERNATIONAL ISO/IEC
STANDARD
15205
IEEE
Std 1496
First edition
2000-06
SBus – Chip and module interconnect bus
Reference number
ISO/IEC 15205:2000(E)
IEEE
Std 1496, 1993 Edition

---------------------- Page: 1 ----------------------
Abstract: An input/output expansion bus with a 32- or 64-bit width is described in this standard.
The SBus is designed for systems requiring a small number expansion ports. SBus Cards
may be connected to a standard Sbus Connector mounted on the motherboard. SBus Devices
may also be attached to the SBus directly on the system's motherboard. The dimensions of
the SBus Card are 83,8 mm by 146,7 mm, making the cards appropriate for small computer
systems that make extensive use of highly integrated circuits. The SBus Cards are designed
to be installed in a plane parallel to the system's motherboard as mezzanine cards. They are
designed to provide connections for devices external to the computer system through an
exposed back panel. The form factor is useful in Futurebus+, VMEbus, desktop computers,
and similar applications. The SBus has the capability of transferring data at rates up to
168 Mbytes/s, depending on the implementation options selected.
SBus Cards may either serve as Masters on the bus, providing all virtual address information
as well as the data to be transferred, or they may serve as Slaves on the bus, providing data
transfer according to the requirements of some other SBus Master. The SBus Master for a
data transfer is selected by an arbitration process managed by the single SBus Controller on
the SBus. The SBus Controller provides a virtual to physical address translation service.
Keywords: I/O bus, SBus, SBus Card, Standard for Boot Firmware.

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The Institute of Electrical and Electronics Engineers, Inc.
345 East 47th Street, New York, NY 10017-2394, USA
Copyright © 1993 by the Institute of Electrical and Electronics Engineers, Inc.
All rights reserved. First published in 1993.
ISBN 2-8318-5165-3
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the prior written permission of the publisher.

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INTERNATIONAL ISO/IEC
STANDARD
15205
IEEE
Std 1496
First edition
2000-06
SBus – Chip and module interconnect bus
Sponsor
Bus Architecture Standards Committee
of the IEEE Computer Society
PRICE CODE
XA
For price, see current catalogue

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– 2 – ISO/IEC 15205:2000(E)
IEEE Std 1496, 1993 Edition
CONTENTS
Page
FOREWORD . 4
INTRODUCTION .5
Clause
1 General. 8
1.1 Scope and object . 8
1.2 Normative references. 8
2 Definitions, usage of special terms, acronyms, and editorial conventions . 9
2.1 Definitions . 9
2.2 Usage of special terms . 13
2.3 Acronyms. 13
2.4 Editorial conventions. 13
3 Overview. 14
3.1 System overview. 14
3.2 Overview of configurations. 16
3.3 General design information . 19
3.4 Performance . 21
4 Signal definitions . 23
4.1 CLK signal . 23
4.2 RST* signal . 24
4.3 PA[27:0] signals. 25
4.4 SEL* signal. 25
4.5 AS* signal. 26
4.6 BR* signal. 26
4.7 BG* signal . 26
4.8 D[31:0], D[63:0], and DP signals . 27
4.9 SIZ[2:0] signals. 28
4.10 RD signal. 28
4.11 ACK[2:0]* signals. 29
4.12 LERR* signal . 31
4.13 INT[7:1]* signals . 32
5 SBus cycle definitions . 33
5.1 Arbitration Phase . 33
5.2 Translation Phase. 34
5.3 Extended Transfer Information Phase . 36
5.4 Transfer Phase . 40
5.5 Dual function SBus Devices . 58
5.6 Exception conditions. 59
5.7 Extended Transfer locking protocol . 60
Copyright © 1993 IEEE. All rights reserved.

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ISO/IEC 15205:2000(E) – 3 –
IEEE Std 1496, 1993 Edition
Clause Page
6 SBus electrical requirements. 62
6.1 Power . 62
6.2 Electronic characteristics . 63
6.3 Electronic timing requirements . 66
6.4 Compliance requirements . 69
7 Environmental requirements. 69
7.1 Operating range. 69
8 Mechanical requirements . 70
8.1 SBus Slot Connector. 70
8.2 SBus Card . 74
8.3 Panel installation . 88
9 SBus program interface . 89
9.1 Introduction. 89
9.2 Program format and interpretation . 89
9.3 Required FCode attributes . 90
9.4 FCode language . 90
9.5 Special functions of Word 0 . 90
Annex A (informative) Compliance checklist . 92
Annex B (informative) Known implementation variations. 97
Bibliography . 101
Index . 102
Copyright © 1993 IEEE. All rights reserved.

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– 4 – ISO/IEC 15205:2000(E)
IEEE Std 1496, 1993 Edition
SBus – CHIP AND MODULE INTERCONNECT BUS
FOREWORD
1) ISO (the International Organization for Standardization) and IEC (the International Electrotechnical
Commission) form the specialized system for worldwide standardization. National bodies that are members of
ISO or IEC participate in the development of International Standards through technical committees established
by the respective organization to deal with particular fields of technical activity. ISO and IEC technical
committees collaborate in fields of mutual interest.Other international organizations, governmental and non-
governmental, in liaison with ISO and IEC, also take part in the work.
2) In the field of information technology, ISO and IEC have established a joint technical committee, ISO/IEC
JTC 1. Draft International Standards adopted by the joint technical committee are circulated to national bodies
for voting. Publication as an International Standard requires approval by at least 75 % of the national bodies
casting a vote.
3) Attention is drawn to the possibility that some of the elements of this International Standard may be the
subject of patent rights. ISO and IEC shall not be held responsible for identifying any or all such patent rights.
International Standard ISO/IEC 15205 was prepared by subcommittee 26: Microprocessor
systems, of ISO/IEC joint technical committee 1: Information technology.
International Standards are drafted in accordance with ISO/IEC Directives, Part 3.
Annexes A and B are for information only.
This standard must be used in conjunction with the latest edition of the following standard:
IEEE Std 1275.
International Electrotechnical Commission • 3, rue de Varembé, PO Box 131,
CH-1211-Geneva 20, Switzerland • Telephone: [phone] •
Telefax: [phone] • e-mail: [e-mail] •
URL: http://www.iec.ch
Copyright © 1993 IEEE. All rights reserved.

---------------------- Page: 6 ----------------------
ISO/IEC 15205:2000(E) – 5 –
IEEE Std 1496, 1993 Edition
INTRODUCTION
(This introduction is not a normative part of ISO/IEC 15205:2000, but is included for
information only.)
This IEEE standard documents the implementation of the popular SBus interface. The SBus,
originally developed and documented by Sun Microsystems as an I/O expansion bus, uses a
standard form factor SBus Card that is a suitable size for the use of VLSI circuits in small
computers. It has a high bandwidth and is capable of data transfer 8, 16, 32, or 64 bits in
width. This standard includes the set of functionality originally documented by the SBus
Specification B.0 (Sun Microsystems Part #800.5922-10, Revision A, December 1990) and
clarifies, corrects, and extends that functionality as required. The IEEE P1275 Working Group
is developing a standard for boot firmware, which will define and document the initialization
and boot interface for SBus Cards.
Special thanks are due to Bob Snively (P1496 Working Group draft technical editor) for the
many hours spent in converting this document from the original SBus Specification B.0 and
editing it into its final form. Also deserving of thanks are Jim Lyle (P1496 Working Group vice
Chair), Barbara Vance (P1496 Working Group former Secretary), Bob Gianni (P1496 Working
Group Secretary), and Steve Hix (P1496 draft document editor) for their support in the
Committee work and the generation of this document.
The following people were members of the P1496 Working Group that approved the draft for
submission to IEEE for sponsor ballot:
Wayne Fischer, Chair
James Lyle, Co-Chair
Robert Gianni, Secretary
Robert Snively, Draft Technical Editor
Sanjay Adkar Steve Golson Elwood Parsons
Steven W. Aiken Anthony A. Goodloe Heinz Piorunneck
Ray S. Alderman James N. Hardage, Jr. Jack Regula
Ravi Anantharaman Hans Heilborn Eayne Rickard
James Antonellis Kai Holz Michael Saari
Tom Armbruster Timothy Hu Siamak Salimpour
Jon K. Bennett Mohammad Issa Gary Sloane
C.J. Beynon Shinkyo Kaku Martin Sodos
Paul Borrill Kuljeet Kalkat Richard Spratt
Mike Chastain Thomas Kappler Mike Strang
Gary Croak Bill Keshlear Lars Themsjö
Scott Eichmann Gary Kidwell David Therrien
Robert Elliott Erik Kristenson Istvan Vadasz
Jurgen Fey Ernst H. Kristiansen Barbara Vance*
Larry Fiedler Joel Libove Naor Wallach
William A. Fox James Ludemann Eike Waltz
Paul Fulton Susan Mason Leo Yuan
Brad Giffel Shrenik Mehta Janusz Zalewski
Donald J. Murphy
* Former Secretary
Copyright © 1993 IEEE. All rights reserved.

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– 6 – ISO/IEC 15205:2000(E)
IEEE Std 1496, 1993 Edition
The following persons were on the balloting committee:
Amir Abouelnaga Larry E. Gerald Richard Mueller
Edward W. Aichinger Robert R. Gianni Michael Orlovsky
Ray S. Alderman Steve Golson Mira Pauker
Richard P. Ames Julio Gonzalez-Sanz Philip K. Piele
Keith D. Anthony John Griffith Rochit Rajsuman
Behrooz Bandall Hans H. Heilborn Brian Ramelson
Chris Bezirtzoglou Zoltan R. Hunor Gary Sloane
Michael L. Bradley Edgar Jacques Bob Snively
Scott M. Buck David V. James Michael Teener
Steven Cobb Horace Jones Joseph P. Trainor
Robert Crowde W. Frederick Ki Robert Tripi
Doug Degroot Ernst H. Kristiansen Rudolf Usselmann
Dante Del Corso Lak Ming Lam Clarence M. Weaver
Samuel Duncan Gerry Laws Michael Wenzel
Wilhelm P. Evertz Boon Lum Lim Andrew Wilson
Wayne Fischer Marlyn Miner Robert J. Wood
Chee K. Fong William E. Molyneaux David L. Wright
Joseph D. George Oren Yuen
When the IEEE Standards Board approved this standard on June 17, 1993, it had the
following membership:
Wallace S. Read, Chair Donald C. Loughry, Vice Chair
Andrew G. Salem, Secretary
Gilles A. Baril Ben C. Johnson T. Don Michael*
Clyde R. Camp Walter J. Karplus Marco Migliaro
Donald C. Fleckenstein Lorraine C. Kevra L. John Rankine
Jay Forster* E. G. Al Kiener Arthur K. Reilly
David F. Franklin Ivor N. Knight Ronald H. Reimer
Ramiro Garcia Joseph L. Koepfinger* Gary S. Robinson
Donald N. Heirman D. N. Jim Logothetis Leonard L. Tripp
Jim Isaak Donald W. Zipse
* Member Emeritus
Also included are the following nonvoting IEEE Standards Board liaisons:
Satish K. Aggarwal
James Beall
Richard B. Engelman
David E. Soffrin
Stanley Warshaw
Paula M. Kelty
IEEE Standards Project Editor
Copyright © 1993 IEEE. All rights reserved.

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ISO/IEC 15205:2000(E) – 7 –
IEEE Std 1496, 1993 Edition
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Societies and the Standards Coordinating Committees of the IEEE Standards Board.
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Copyright © 1993 IEEE. All rights reserved.

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– 8 – ISO/IEC 15205:2000(E)
IEEE Std 1496, 1993 Edition
SBus – CHIP AND MODULE INTERCONNECT BUS
1 General
1.1 Scope and object
SBus is a high performance computer I/O interface for connecting integrated circuits and
SBus Cards to a computer system motherboard. This standard defines the mechanical,
electrical, environmental, and protocol requirements for the design of SBus Cards and the
computer system motherboard that supports those cards.
Every SBus Card shall implement appropriate self-descriptive and initialization firmware using
FCode, which is similar to the Forth programming language. The details of this firmware
1)
standard are beyond the scope of this standard. In addition, other software interfaces may
be used for communication with SBus Cards.
SBus is intended to provide a high performance I/O bus interface with a small mechanical
form factor. The small size, high levels of integration, and low power usage of SBus Cards
enable them to be used in laptop computers, compact desktop computers, and other
applications requiring similar characteristics. SBus Cards are mounted in a plane parallel to
the motherboard of the computer system, allowing the computer system to have a low profile.
SBus is not designed as a general purpose backplane bus.
SBus allows transfers to be in units of 8, 16, 32, or 64 bits. Burst transfers are allowed to
further improve performance. SBus allows a number of SBus Master devices to arbitrate for
access to the bus. The chosen SBus Master provides a 32-bit virtual address which the SBus
Controller maps to the selection of the proper SBus Slave and the development of the 28-bit
physical address for that Slave. The selected SBus Slave then performs the data transfers
requested by the SBus Master. Simple SBus Cards may be designed to operate solely as
Slaves on the SBus.
1.2 Normative references
The following normative documents contain provisions which, through reference in this text,
constitute provisions of this International Standard. For dated references, subsequent
amendments to, or revisions of, any of these publications do not apply. However, parties to
agreements based on this International Standard are encouraged to investigate the possibility
of applying the most recent editions of the normative documents indicated below. For undated
references, the latest edition of the normative document referred to applies. Members of IEC
and ISO maintain registers of currently valid International Standards.
IEEE Std 1275:1994, IEEE Standard for Boot (Initialization Configuration) Firmware: Core
2)
Requirements and Practices
__________
1)
A firmware interface standard is under consideration.
2)
IEEE publications are available from the Institute of Electrical and Electronics Engineers, 445 Hoes Lane,
P.O. Box 1331, Piscataway, NJ 08855-1331, USA (standards.ieee.org/).
Copyright © 1993 IEEE. All rights reserved.

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ISO/IEC 15205:2000(E) – 9 –
IEEE Std 1496, 1993 Edition
2 Definitions, usage of special terms, acronyms, and editorial conventions
2.1 Definitions
For the purposes of this standard the following definitions apply.
2.1.1
assert
a) for a single signal: to drive a signal to the one (1), or asserted, logic state.
b) for a set of parallel signals of the same function: to place the desired logic state pattern on
the bus, which may include both one and zero values
2.1.2
byte
set of eight bit-parallel signals corresponding to binary digits operated on as a unit
The most significant bit carries index value 7 and the least significant bit carries index value
0.
2.1.3
byte Slave
SBus Slave having a data path only through bits D[31:24] of the data bus
2.1.4
Bus Sizing
the dynamic modification of the data transfer width to meet the SBus Slave's bus width
requirements [see 5.4.6]
2.1.5
CLK
a fixed-frequency clock signal; the main SBus timing signal
2.1.6
clock cycle
one period of the CLK signal, beginning with the rising edge of the signal and ending on the
following rising edge of the signal
2.1.7
Controller
see SBus Controller
2.1.8
central processing unit (CPU)
describes that part of a computer that does the primary computational functions; loosely
describes the computer system other than connected input and output devices
2.1.9
double-word
eight bytes or 64 bits operated on as a unit.
The most significant byte carries index value 0 and the least significant byte carries index
value 7.
2.1.10
half-word
two bytes or 16 bits operated on as a unit
The most significant byte carries index value 0 and the least significant byte carries index
value 1.
Copyright © 1993 IEEE. All rights reserved.

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– 10 – ISO/IEC 15205:2000(E)
IEEE Std 1496, 1993 Edition
2.1.11
half-word Slave
an SBus Slave having a data path only through bits D[31:16] of the data bus
2.1.12
high (H) level
a signal voltage within the more positive (less negative) of the two ranges of logic levels
chosen to represent the logic states
2.1.13
holding amplifier
receiver circuit incorporating feedback that maintains the present input logic level in the
absence of any other drive signals on the signal line
2.1.14
logic state
one of two possible abstract states that may be taken on by a binary logic variable
See one, zero, assert, negate, signal state.
2.1.15
logic level
any level within one of two non-overlapping ranges of values of voltage used to represent the
logic states
See high, low.
2.1.16
low (L) level
a signal voltage within the more negative (less positive) of the two ranges of logic levels
chosen to represent the logic states
2.1.17
mandatory
The referenced item is required to claim compliance with this standard.
2.1.18
Master
See SBus Master.
2.1.19
motherboard
the printed circuit board on which an SBus Card is mounted through the connectors specified
by this standard
2.1.20
negate
to drive a signal or a parallel set of signals to the zero logic state
2.1.21
odd parity
within a field or set of fields, an odd number of bits having the logical state of one; the
exclusive-OR of all the bits being checked has the value of 1
2.1.22
one ("1")
a true logic state or a true condition of a variable
Copyright © 1993 IEEE. All rights reserved.

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ISO/IEC 15205:2000(E) – 11 –
IEEE Std 1496, 1993 Edition
2.1.23
optional
The referenced item is not required to claim compliance with this standard. Implementation of
an optional item should be as defined in this standard.
2.1.24
reserved
the term used for signals, bits, fields, and code values that are set aside for future
standardization
2.1.25
SBus
a) the correct spelling of the noun describing the bus defined by this standard
b) the name for the Chip and Module Interconnect Bus described by this standard
2.1.26
SBus Card
a physical printed circuit assembly that conforms to the single-width or double-width
mechanical specifications; meets the connector, power, and signal assignment requirements
of this standard and contains one or more SBus Devices
2.1.27
SBus Controller
the SBus Device that performs all the centralized services for the SBus, including bias
circuitry, arbitration, and address translation for SBus Masters, and selection of and time-outs
for SBus Slaves
2.1.28
SBus cycle
one complete operation on the SBus, consisting of a set of phases beginning with an optional
Arbitration Phase and progressing through the optional Translation Phase, the optional
Extended Transfer Information Phase, and the Transfer Phase
2.1.29
SBus Device
a set of circuitry complying with the electrical and protocol requirements of the SBus and
properly implementing all the signals of the SBus
An SBus Device may reside on the computer motherboard or it may be on an SBus Card.
See SBus Controller, SBus Master, SBus Slave.
2.1.30
SBus Master
the SBus Device that requests data transfers to be performed by an SBus Slave
2.1.31
SBus Master port
in an SBus Device that combines both an SBus Master and an SBus Slave, the circuitry that
is associated with the SBus Master
2.1.32
SBus Slave
the SBus Device providing the function of performing the data transfers requested by an SBus
Master; the address space for the data transfers may contain data, control registers, or sense
registers
Copyright © 1993 IEEE. All rights reserved.

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– 12 – ISO/IEC 15205:2000(E)
IEEE Std 1496, 1993 Edition
2.1.33
SBus Slave port
in an SBus Device that combines both an SBus Master and an SBus Slave, the circuitry that
is associated with the SBus Slave
2.1.34
SBus Slot
the location on a computer motherboard in which an SBus Card may be installed
The SBus Slot has the connector, the electrical characteristics, and the physical volumes and
dimensions that are required by this standard.
2.1.35
SBus Specification
1)
SBus Specification B.0 [B1] , an earlier specification of SBus, now superseded by
IEEE Std 1496
2.1.36
SBus standard
IEEE Std 1496, IEEE Standard for a Chip and Module Interconnect Bus: SBus
2.1.37
SBus System
a computer system containing a motherboard with at least an SBus Controller and some
combination of zero or more SBus Slots which may be populated with SBus Cards
The SBus System may additionally have SBus Devices integrated on the motherboard. The
SBus System includes the electronic, powering, cooling, and mechanical support functions
required by the installed SBus Devices and SBus Slots.
2.1.38
signal assertion
a) the act of driving a signal to the true state
b) the act of driving a bus of signals to the correct pattern of ones and zeros
2.1.39
signal negation
the act of driving a signal to the false state
2.1.40
signal release
the act of removing electronic drive to a signal thereby placing the driver in a high-impedance
condition
Release of an SBus signal
...