Electrostatic discharge (ESD) sensitivity testing human body model (HBM)

Establishes a standard procedure for testing and classifying microcircuits according to their susceptibility to damage or degradation by exposure to a defined electrostatic Human Body Model (HBM) discharge (ESD). The objective is to provide reliable, repeatable HBM ESD test results so that accurate classifications can be performed.

General Information

Status
Replaced
Publication Date
21-Aug-2000
Technical Committee
Drafting Committee
Current Stage
DELPUB - Deleted Publication
Completion Date
22-Oct-2003
Ref Project

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Technical specification
IEC PAS 62179:2000 - Electrostatic discharge (ESD) sensitivity testing human body model (HBM) Released:8/22/2000 Isbn:2831853524
English language
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Standards Content (Sample)


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Edition 1.0
2000-08
Electrostatic discharge (ESD) sensitivity
testing human body model (HBM)

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IN TER N A TION AL Reference number
E L E C T R OT E CHNI CA L
IEC/PAS 62179
C O MMI S S I O N
Copyright © 1997, JEDEC; 2000, IEC

INTERNATIONAL ELECTROTECHNICAL COMMISSION

____________
ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY

TESTING HUMAN BODY MODEL (HBM)

FOREWORD
A PAS is a technical specification not fulfilling the requirements for a standard, but made available to the
public and established in an organization operating under given procedures.
IEC-PAS 62179 was submitted by JEDEC and has been processed by IEC technical committee 47: Semiconductor
devices.
The text of this PAS is based on the This PAS was approved for
following document: publication by the P-members of the
committee concerned as indicated in
the following document:
Draft PAS Report on voting
47/1452/PAS 47/1485/RVD
Following publication of this PAS, the technical committee or subcommittee concerned will investigate the
possibility of transforming the PAS into an International Standard.
An IEC-PAS licence of copyright and assignment of copyright has been signed by the IEC and JEDEC and is
recorded at the Central Office.
1) The IEC (International Electrotechnical Commission) is a worldwide organization for standardization comprising all
national electrotechnical committees (IEC National Committees). The object of the IEC is to promote international co-
operation on all questions concerning standardization in the electrical and electronic fields. To this end and in addition
to other activities, the IEC publishes International Standards. Their preparation is entrusted to technical committees;
any IEC National Committee interested in the subject dealt with may participate in this preparatory work. International,
governmental and non-governmental organizations liaising with the IEC also participate in this preparation. The IEC
collaborates closely with the International Organization for Standardization (ISO) in accordance with conditions
determined by agreement between the two organizations.
2) The formal decisions or agreements of the IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all interested
National Committees.
3) The documents produced have the form of recommendations for international use and are published in the form of
standards, technical specifications, technical reports or guides and they are accepted by the National Committees in
that sense.
4) In order to promote international unification, IEC National Committees undertake to apply IEC International Standards
transparently to the maximum extent possible in their national and regional standards. Any divergence between the
IEC Standard and the corresponding national or regional standard shall be clearly indicated in the latter.
5) The IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with one of its standards.
6) Attention is drawn to the possibility that some of the elements of this PAS may be the subject of patent rights. The
IEC shall not be held responsible for identifying any or all such patent rights.
Page i
Copyright © 1997, JEDEC; 2000, IEC

JESD22-A114-A
Page 1
TEST METHOD A114A
ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING

HUMAN BODY MODEL (HBM)
(From JEDEC Council Ballot JCB-97-11, formulated under the cognizance of JC-14.1 Committee on

Reliability Test Methods for Packaged Devices.)

1 Purpose
This method establishes a standard procedure for testing and classifying microcircuits according to their
susceptibility to damage or degradation by exposure to a defined electrostatic Human Body Model
(HBM) discharge (ESD). The objective is to provide reliable, repeatable HBM ESD test results so that
accurate classifications can be performed.
2 Apparatus
This test method requires the following equipment.
2.1 An ESD pulse simulator and a Device Under Test (DUT) socket equivalent to the circuit of figure 1.
The simulator must be capable of supplying pulses with the characteristics required by figure 2 and
figure 3.
2.2 Oscilloscope
The oscilloscope and amplifier combination shall have a 350 MHz minimum single-shot bandwidth and a
visual writing speed of 4 cm/ns minimum.
2.3 Current probe
The current probe shall have a minimum pulse-current bandwidth of 350 MHz. A current probe
(transformer and cable with a nominal length of 1 meter) with a 1 GHz bandwidth and a current rating of
12 amperes maximum pulse-current is recommended.

2.4 Evaluation loads
An 18 AWG tinned copper wire is recommended for the short waveform verification test. The lead
length should be as short as practicable to span the distance between the two farthest pins in the socket
while passing through the current probe. The ends of the 18 AWG wire may be ground to a point where
clearance is needed to make contact on fine-pitch socket pins.
A 500 ohm +/-1%, 4000 volt, low-inductance resistor shall be used for initial system checkout and
periodic system recalibration.
Test Method Al14-A
(Revision of Test Method Al14)

Copyright © 1997, JEDEC; 2000, IEC

Copyright © 1997, JEDEC; 2000, IEC

Copyright © 1997, JEDEC; 2000, IEC

Copyright © 1997, JEDEC; 2000, IEC
JESD22-A114-A
Page 5
3 Qualification, calibration, and waveform verification

3.1 Equipment qualification
Equipment calibration must be performed during initial acceptance testing. Recalibration is required

whenever equipment repairs are made that may affect the waveform and a minimum of every 12 months.

The tester must meet the requirements of table 1 and figure 2 at all voltage levels using the shorting wire
and at the 4000 volt level with the 500 ohm resistor (see figure 3). The waveform measurements during
calibration shall be made using the worst-case pin on the highest pin count board with a positive
mechanical clamp socket. (Machine repeatability should be verified during initial equipment acceptance
by performing a minimum of 5 consecutive positive and a minimum of 5 consecutive negative waveforms
at a voltage level in table 2.) The high-voltage relays and associated high-voltage circuitry shall be tested
by the user of computer-controlled systems per the equipment manufacturer’s instructions (system
diagnostics). This test will check for any open or short relays.
Table 1 — Waveform Specification
Rise Time Decay Decay Ringing
Level Short, 500 Ohm* for Short, for 500 Time for Time for Current
(V) 1/Ips Ipr Ohm* Short, 500 Ohm*
(A) (A)
(ns)
(ns) (ns)
(ns)
500 0.30-0.37 N/A 2.0-10 N/A 130-170 N/A 15% of Ips
1000 0.60-0.74 N/A 2.0-10 N/A 130-170 N/A 15% of Ips
1.20-1.48
2000 N/A 2.0-10 N/A 130-170 N/A 15% of Ips

4000 2.40-2.96
1.5-2.2 2.0-10 15% of Ips
and Ipr
* The 500 ohm load is used only during equipment qualification as specified in 3.1.
1/ Ipeak is the current through Rl, that is, approximately V/1500 ohms.
Test Method Al14-A
(Revision of Test Method Al14)

Copyright © 1997, JEDEC; 2000, IEC

JESD22-A114-A
Page 6
3 Qualification, calibration, and waveform verification (cont’d)

3.2 Worst-case pin
The worst-case pin combination for each socket and DUT board shall be identified and documented. It is
recommended that the manufacturers supply the worst-case pin data with each DUT board. The pin
combination with the waveform closest to the limits (see table 1) shall be designated for waveform
verification.
3.2.1 The worst-case pin combination shall be identified by the following procedure.
3.2.1.1 For each test socket, identify the socket pin with the shortest wiring path from
...

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