IEC PAS 62177:2000

Highly-accelerated temperature and humidity stress test (HAST)

The highly-accelerated temperature and humidity stress test is performed for the purpose of evaluating the reliability of non-hermetic packaged solid-state devices in humid environments. It employs severe conditions of temperature, humidity, and bias which accelerate the penetration of moisture through the external protective material or along the interface between the external protective material and the metallic conductors which pass through it.

General Information

• Status: Replaced
• Publication Date: 23-Aug-2000
• ICS: 31.080.01 - Semiconductor devices in general
• Technical Committee: TC 47 - Semiconductor devices
• Drafting Committee: WG 2 - TC 47/WG 2
• Current Stage: WPUB - Publication withdrawn
• Start Date: 30-Jun-2002
• Completion Date: 01-Jul-2002

Relations

• Replaced By: IEC 60749-4:2002 - Semiconductor devices - Mechanical and climatic test methods - Part 4: Damp heat, steady state, highly accelerated stress test (HAST)
• Effective Date: 05-Sep-2023

Standards Content (Sample)

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2000-08
Highly-accelerated temperature and
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IN TER N A TION AL Reference number
E L E C T R OT E CHNI CA L
IEC/PAS 62177
C O MMI S S I O N
EIA/JEDEC
STANDARD
Test Method A110-B
Highly-Accelerated Temperature and
Humidity Stress Test (HAST)
JESD22-A110-B
(Revision of Test Method A110-A)
FEBRUARY 1999
ELECTRONIC INDUSTRIES ALLIANCE
JEDEC Solid State Technology Association

Copyright © 1999, JEDEC; 2000, IEC

INTERNATIONAL ELECTROTECHNICAL COMMISSION

____________
HIGHLY-ACCELERATED TEMPERATURE

AND HUMIDITY STRESS TEST (HAST)

FOREWORD
A PAS is a technical specification not fulfilling the requirements for a standard, but made available to the
public and established in an organization operating under given procedures.
IEC-PAS 62177 was submitted by JEDEC and has been processed by IEC technical committee 47: Semiconductor
devices.
The text of this PAS is based on the This PAS was approved for
following document: publication by the P-members of the
committee concerned as indicated in
the following document:
Draft PAS Report on voting
47/1450/PAS 47/1483/RVD
Following publication of this PAS, the technical committee or subcommittee concerned will investigate the
possibility of transforming the PAS into an International Standard.
An IEC-PAS licence of copyright and assignment of copyright has been signed by the IEC and JEDEC and is
recorded at the Central Office.
1) The IEC (International Electrotechnical Commission) is a worldwide organization for standardization comprising all
national electrotechnical committees (IEC National Committees). The object of the IEC is to promote international co-
operation on all questions concerning standardization in the electrical and electronic fields. To this end and in addition
to other activities, the IEC publishes International Standards. Their preparation is entrusted to technical committees;
any IEC National Committee interested in the subject dealt with may participate in this preparatory work. International,
governmental and non-governmental organizations liaising with the IEC also participate in this preparation. The IEC
collaborates closely with the International Organization for Standardization (ISO) in accordance with conditions
determined by agreement between the two organizations.
2) The formal decisions or agreements of the IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all interested
National Committees.
3) The documents produced have the form of recommendations for international use and are published in the form of
standards, technical specifications, technical reports or guides and they are accepted by the National Committees in
that sense.
4) In order to promote international unification, IEC National Committees undertake to apply IEC International Standards
transparently to the maximum extent possible in their national and regional standards. Any divergence between the
IEC Standard and the corresponding national or regional standard shall be clearly indicated in the latter.
5) The IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with one of its standards.
6) Attention is drawn to the possibility that some of the elements of this PAS may be the subject of patent rights. The
IEC shall not be held responsible for identifying any or all such patent rights.
Page i
Copyright © 1999, JEDEC; 2000, IEC

NOTICE
EIA/JEDEC standards and publications contain material that has been prepared, reviewed, and

approved through the JEDEC Board of Directors level and subsequently reviewed and approved

EIA/JEDEC standards and publications are designed to serve the public interest through

eliminating misunderstandings between manufacturers and purchasers, facilitating
interchangeability and improvement of products, and assisting the purchaser in selecting and
obtaining with minimum delay the proper product for use by those other than JEDEC members,
EIA/JEDEC standards and publications are adopted without regard to whether or not their
adoption may involve patents or articles, materials, or processes. By such action JEDEC does not
assume any liability to any patent owner, nor does it assume any obligation whatever to parties
The information included in EIA/JEDEC standards and publications represents a sound approach
to product specification and application, principally from the solid state device manufacturer
viewpoint. Within the JEDEC organization there are procedures whereby an EIA/JEDEC
No claims to be in conformance with this standard may be made unless all requirements stated in
the standard are met.
Inquiries, comments, and suggestions relative to the content of this EIA/JEDEC standard or
publication should be addressed to JEDEC Solid State Technology Association, 2500 Wilson
Boulevard, Arlington, VA 22201-3834, [phone]/7559 or www.jedec.org
©
Engineering Department
Arlington, VA 22201-3834
JEDEC Publication 21 "Manual of Organization and Procedure".
free to duplicate this document in accordance with the latest revision of
"Copyright" does not apply to JEDEC member companies as they are
2500 Wilson Boulevard
ELECTRONIC INDUSTRIES ALLIANCE 1999
Published by
standard or publication may be further processed and ultimately become an ANSI/EIA standard.
adopting the EIA/JEDEC standards or publications.
whether the standard is to be used either domestically or internationally.
by the EIA General Counsel.
Copyright © 1999, JEDEC; 2000, IEC

TEST METHOD A110-B
HIGHLY-ACCELERATED TEMPERATURE

AND HUMIDITY STRESS TEST (HAST)

(From JEDEC Council Ballot JCB-98-86, formulated under the cognizance of JC-14.1 Committee on

1 Purpose
Highly-Accelerated Temperature and Humidity Stress Test is performed for the purpose of
evaluating the reliability of non-hermetic packaged solid-state devices in humid environments. It employs
bias which accelerate the penetration of moisture through
material and the metallic conductors which pass through it. The stress usually activates the same failure
2 Apparatus
continuously, while providing electrical connections to the devices under test in a specified biasing
2.1 Controlled conditions
The chamber must be capable of providing controlled conditions of pressure, temperature and relative
humidity during ramp-up to, and ramp-down from the specified test conditions. Calibration records shall
verify that the equipment avoids condensation on devices under test (DUTs) hotter than 50 ºC during
ramp-up and ramp-down for conditions of maximum thermal mass loading and minimum (zero) DUT
power dissipation. Calibration records shall verify that, for steady state conditions and maximum thermal
2.2 Temperature profile
A permanent record of the temperature profile for each test cycle is recommended, so that the validity of
2.3 Devices under stress
Devices under stress must be physically located to minimize temperature gradients. Devices under stress
shall be no closer than 3 cm from internal chamber surfaces, and must not be subjected to direct radiant
(Revision of A110-A)
Test Method A110-B
vapor circulation.
heat from heaters. Boards on which devices are mounted should be oriented to minimize interference with
the stress can be verified.
mass loading, test conditions are maintained within the tolerances specified in 3.1.
configuration.
The test requires a pressure chamber capable of maintaining a specified temperature and relative humidity
mechanisms as the “85/85” Steady-State Humidity Life Test (JEDEC Standard No. 22-A101).
the external protective material (encapsulant or seal) or along the interface between the external protective
severe conditions of temperature, humidity, and
The
Reliability Test Methods for Packaged Devices.)
Page
JESD22-A110-B
Copyright © 1999, JEDEC; 2000, IEC

2 Apparatus (cont’d)
2.4 Minimize release of contamination

Care must be exercised in the choice of board and socket materials, to minimize release of contamination

2.5 Ionic contamination
Ionic contamination of the test apparatus (card cage, test boards, sockets, wiring storage containers, etc.)
2.6 De-ionized water
3 Test conditions
Test conditions consist of a temperature, relative humidity, and duration in conjunction with an electrical
3.1 Temper
...