IEC 62137:2004

Environmental and endurance testing - Test methods for surface-mount boards of area array type packages FBGA, BGA, FLGA, LGA, SON and QFN

This International Standard specifies the test method and guidelines for evaluating the quality and reliability of boards, solder lands, solder process and solder joints of reflow solder mounted area array type packages and peripheral terminal type packages. This standard tests for durability against mechanical and thermal stress received during or after the mounting process of discrete semiconductor devices and of integrated circuits (hereinafter both referred to as semiconductor devices) used mainly for industrial and consumer use equipment.

Essais d'environnement et d'endurance - Méthodes d'essai pour les cartes à montage en surface de boîtiers de type matriciel FBGA, BGA, FLGA, LGA, SON et QFN

Cette norme internationale spécifie les méthodes d'essai et les principes pour évaluer la qualité et la fiabilité des cartes, des zones de report, du processus de brasage, et des joints de soudure du procédé de refusion des boîtiers de type matriciel et des boîtiers de type à bornes périphériques (QFN et SON). La présente norme fournit des essais d'endurance aux contraintes thermiques et mécaniques subies pendant ou après le processus d'assemblage des dispositifs à semi-conducteurs discrets et des circuits intégrés (tous deux appelés ci-après "dispositifs à semi-conducteurs") utilisés principalement pour l'équipement d'utilisation industrielle et grand public.

General Information

• Status: Replaced
• Publication Date: 05-Jul-2004
• ICS: 31.190 - Electronic component assemblies
• Technical Committee: TC 91 - Electronics assembly technology
• Drafting Committee: WG 3 - TC 91/WG 3
• Current Stage: DELPUB - Deleted Publication
• Completion Date: 09-Oct-2014

Relations

• Replaced By: IEC 62137-4:2014 - Electronics assembly technology - Part 4: Endurance test methods for solder joint of area array type package surface mount devices
• Effective Date: 05-Sep-2023
• Corrected By: IEC 62137:2004/COR1:2005 - Corrigendum 1 - Environmental and endurance testing - Test methods for surface-mount boards of area array type packages FBGA, BGA, FLGA, LGA, SON and QFN
• Effective Date: 05-Sep-2023

Standards Content (Sample)

INTERNATIONAL IEC
STANDARD 62137
First edition
2004-07
Environmental and endurance testing –
Test methods for surface-mount boards
of area array type packages FBGA, BGA,
FLGA, LGA, SON and QFN
Reference number
Publication numbering
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60000 series. For example, IEC 34-1 is now referred to as IEC 60034-1.
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INTERNATIONAL IEC
STANDARD 62137
First edition
2004-07
Environmental and endurance testing –
Test methods for surface-mount boards
of area array type packages FBGA, BGA,
FLGA, LGA, SON and QFN
© IEC 2004 ⎯ Copyright - all rights reserved
No part of this publication may be reproduced or utilized in any form or by any means, electronic or
mechanical, including photocopying and microfilm, without permission in writing from the publisher.
International Electrotechnical Commission, 3, rue de Varembé, PO Box 131, CH-1211 Geneva 20, Switzerland
Telephone: [phone] Telefax: [phone] E-mail: [e-mail] Web: www.iec.ch
PRICE CODE
Commission Electrotechnique Internationale U
International Electrotechnical Commission
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For price, see current catalogue

– 2 – 62137 © IEC:2004(E)
CONTENTS
FOREWORD.3
1 Scope.5
2 Normative references .5
3 Terms and definitions .6
4 Abbreviations .6
5 Solder joint quality test methods.6
5.1 Reflow solderability test for solder joint .6
5.2 Reserved for future use.9
6 Mechanical test methods .9
6.1 Bending test for solder joint.9
6.2 Drop test for solder joint .9
7 Environment test methods .9
7.1 Temperature cycling test for solder joint .9
7.2 Reserved for future use.12
Annex A (informative) Informative test methods for test board – Guidance.13
Annex B (informative) Standard mounting process for area array type packages and
peripheral terminal type packages (QFN and SON).23
Bibliography.26
Figure 1 – Temperature measurement of the specimen using thermocouples.8
Figure 2 – Moistening/reflow process cycle proposed .8
Figure 3 – Reflow profile.8
Figure 4 – Configuration of one cycle period .11
Figure A.1 – Temperature measurement of the specimen using thermocouples .14
Figure A.2 – Temperature measurement of the specimen using thermocouples .16
Figure A.3 – Measuring method for peel strength.18
Figure A.4 – Standard land shape of the mount reliability test board .21
Figure A.5 – Design standard for land shape of packages of peripheral terminal type
SON and QFN.22
Table 1 – Temperature cycling test conditions .11
Table A.1 – Types of mount reliability test board.20
Table A.2 – Standard mount reliability test board layer configuration .21
Table A.3 – Design guideline for land size of packages of area array ball/land type
BGA, FBGA, LGA, and FLGA.21
Table B.1 – Stencil design standard for area array terminal type packages.24
Table B.2 – Stencil design standard for peripheral terminal type packages .24

62137 © IEC:2004(E) – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
ENVIRONMENTAL AND ENDURANCE TESTING –
TEST METHODS FOR SURFACE-MOUNT BOARDS OF AREA ARRAY
TYPE PACKAGES FBGA, BGA, FLGA, LGA, SON AND QFN
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
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9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of
patent rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 62137 has been prepared by IEC technical committee 91:
Electronics assembly technology.
The text of this standard is based on the following documents:
FDIS Report on voting
91/444/FDIS 91/451/RVD
Full information on the voting for the approval of this standard can be found in the report on
voting indicated in the above table.
___________
FBGA fine-pitch ball grid array
BGA ball grid array
FLGA fine-pitch land grid array
LGA land grid array
SON small outline non-leaded package
QFN quad flat-pack non-leaded package

– 4 – 62137 © IEC:2004(E)
This publication has been drafted in accordance with the ISO/IEC Directives, Part 2.
The committee has decided that the contents of this publication will remain unchanged until
the maintenance result date indicated on the IEC web site under "http://webstore.iec.ch" in
the data related to the specific publication. At this date, the publication will be
 reconfirmed;
 withdrawn;
 replaced by a revised edition, or
 amended.
A bilingual version may be issued at a later date.

62137 © IEC:2004(E) – 5 –
ENVIRONMENTAL AND ENDURANCE TESTING –
TEST METHODS FOR SURFACE-MOUNT BOARDS OF AREA ARRAY
TYPE PACKAGES FBGA, BGA, FLGA, LGA, SON AND QFN
1 Scope
This International Standard specifies the test method and guidelines for evaluating the quality
and reliability of boards, solder lands, solder process and solder joints of reflow solder
mounted area array type packages and peripheral terminal type packages.
This standard tests for durability against mechanical and thermal stress received during or
after the mounting process of discrete semiconductor devices and of integrated circuits
(hereinafter both referred to as semiconductor devices) used mainly for industrial and
consumer use equipment.
The test method specified in this standard is an integrated one by including the evaluation
method of mounting methods, mounting conditions, printed circuit boards, soldering materials,
and so on. It does not specify the evaluation method of the individual semiconductor devices.
Mounting conditions, printed wiring boards, soldering materials, and so on significantly affect
the result of the test specified in this standard. Therefore, the test specified in this standard
shall not be regarded as the one to be used to guarantee the mounting reliability of the
semiconductor devices.
The test method is not necessary if there is no stress (mechanical or others) from any of the
tests covered in this standard.
2 Normative references
The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document (including any amendments) applies.
IEC 60068-1:1988, Environmental testing – Part 1: General and guidance
IEC 60191-6-2:2001, Mechanical standardization of semiconductor devices – Part 6-2:
General rules for the preparation of outline drawings of surface mounted semiconductor
device packages – Design guide for 1,50 mm, 1,27 mm and 1,00 mm pitch ball and column
terminal packages
IEC 60191-6-5:2001, Mechanical standardization of semiconductor devices – Part 6-5:
General rules for the preparation of outline drawings of surface mounted semiconductor
device packages – Design guide for fine-pitch ball grid array (FBGA)
IEC 61190-1-1, Attachment materials for electronic assemblies – Part 1-1: Requirements for
soldering fluxes for high-quality interconnections in electronics assembly
IEC 61190-1-2, Attachment materials for electronic assemblies – Part 1-2: Requirements for
solder pastes for high-quality interconnections in electronics assembly
IEC 61190-1-3, Attachment materials for electronic assemblies – Part 1-3: Requirements for
electronic grade solder alloys and fluxed and non-fluxed solid solders for electronic soldering
applications
JEITA ETR-7001:1998, Terms and definitions for surface mount technology
___________
Japan Electronics and Information Technology Industries Association.

– 6 – 62137 © IEC:2004(E)
3 Terms and definitions
For the purposes of this document, the terms and definitions for BG
...

IEC 62137
Edition 1.0 2004-07
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Environmental and endurance testing – Test methods for surface-mount boards
or area array type packages FBGA, BGA, FLGA, LGA, SON and QFN

Essais d’environnement et d’endurance – Méthodes d’essai pour les cartes à
montage en surface de boîtiers de type matriciel FBGA, BGA, FLGA, LGA, SON
et QFN
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IEC 62137
Edition 1.0 2004-07
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Environmental and endurance testing – Test methods for surface-mount boards
or area array type packages FBGA, BGA, FLGA, LGA, SON and QFN

Essais d’environnement et d’endurance – Méthodes d’essai pour les cartes à
montage en surface de boîtiers de type matriciel FBGA, BGA, FLGA, LGA, SON
et QFN
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
PRICE CODE
INTERNATIONALE
U
CODE PRIX
ICS 31.190 ISBN 2-8318-7806-3
– 2 – 62137 © CEI:2004
SOMMAIRE
AVANT-PROPOS.6

1 Domaine d'application .10
2 Références normatives.10
3 Termes et définitions .12
4 Abréviations .12
5 Méthodes d’essai de la qualité des joints de soudure .12
5.1 Essai de brasabilité avec fusion pour les joints de soudure .12
5.2 Réservé pour utilisation ultérieure .18
6 Méthodes d’essais mécaniques .18
6.1 Essai de flexion sur les joints de soudure.18
6.2 Essai de chute pour les joints de soudure .18
7 Méthodes d’essais d’environnement .20
7.1 Essai de cycle de température des joints de soudure.20
7.2 Réservé pour utilisation ultérieure .26

Annexe A (informative) Méthodes d’essais informatives pour cartes d’essais – Lignes
directrices.28
Annexe B (informative) Processus de montage normal des boîtiers de type matriciel
et des boîtiers de type à bornes périphériques (QFN et SON) .50

Bibliographie.56

Figure 1 – Mesure de la température des spécimens utilisant des thermocouples .16
Figure 2 – Cycle proposé du processus d’humidification/de fusion .16
Figure 3 – Profil de refusion.18
Figure 4 – Configuration d’une période cyclique.22
Figure A.1 – Mesure de la température du spécimen en utilisant des thermocouples .30
Figure A.2 – Mesure de la température du spécimen en utilisant des thermocouples .34
Figure A.3 – Méthode de mesure de la force d’adhérence des boules de soudure .38
Figure A.4 – Forme d’une plage de connexion normale de la carte d’essai du montage
de fiabilité.44
Figure A.5 – Norme de conception pour la forme des plages de connexion des boîtiers
de type à bornes périphériques SON et QFN .46

62137 © IEC:2004 – 3 –
CONTENTS
FOREWORD.7

1 Scope.11
2 Normative references .11
3 Terms and definitions .13
4 Abbreviations .13
5 Solder joint quality test methods.13
5.1 Reflow solderability test for solder joint .13
5.2 Reserved for future use.19
6 Mechanical test methods .19
6.1 Bending test for solder joint.19
6.2 Drop test for solder joint .19
7 Environment test methods .21
7.1 Temperature cycling test for solder joint .21
7.2 Reserved for future use.27

Annex A (informative) Informative test methods for test board – Guidance.29
Annex B (informative) Standard mounting process for area array type packages and
peripheral terminal type packages (QFN and SON).51

Bibliography.57

Figure 1 – Temperature measurement of the specimen using thermocouples.17
Figure 2 – Moistening/reflow process cycle proposed .17
Figure 3 – Reflow profile.19
Figure 4 – Configuration of one cycle period .23
Figure A.1 – Temperature measurement of the specimen using thermocouples .31
Figure A.2 – Temperature measurement of the specimen using thermocouples .35
Figure A.3 – Measuring methods for peel strength .39
Figure A.4 – Standard land shape of the mount reliability test board .45
Figure A.5 – Design standard for land shape of packages of peripheral terminal type
SON and QFN.47

– 4 – 62137 © CEI:2004
Tableau 1 – Conditions d’essai des cycles de températures.24
Tableau A.1 – Types de cartes d’essais du montage de fiabilité.42
Tableau A.2 – Configuration d’une carte d’essai à couches d’un montage de fiabilité
normalisé.44
Tableau A.3 – Indications de conception pour la taille des plages de connexion des
boîtiers de type matriciel à billes BGA, FBGA, LGA, et FLGA.46
Tableau B.1 – Norme de conception du stencil pour les boîtiers de type matriciel.50
Tableau B.2 – Norme de conception du stencil pour les boîtiers de type à bornes
périphériques.50

62137 © IEC:2004 – 5 –
Table 1 – Temperature cycling test conditions .25
Table A.1 – Types of mount reliability test board.43
Table A.2 – Standard mount reliability test board layer configuration .45
Table A.3 – Design guideline for land size of packages of area array ball/land type
BGA, FBGA, LGA, and FLGA.47
Table B.1 – Stencil design standard for area array type packages .51
Table B.2 – Stencil design standard for peripheral terminal type packages .51

– 6 – 62137 © CEI:2004
COMMISSION ÉLECTROTECHNIQUE INTERNATIONALE
____________
ESSAIS D’ENVIRONNEMENT ET D’ENDURANCE –
MÉTHODES D’ESSAI POUR LES CARTES À MONTAGE EN SURFACE DE
BOÎTIERS DE TYPE MATRICIEL FBGA, BGA, FLGA, LGA, SON ET QFN

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