ISO 11898-2:2024

Road vehicles - Controller area network (CAN) - Part 2: High-speed physical medium attachment (PMA) sublayer

This document specifies physical medium attachment (PMA) sublayers for the controller area network (CAN). This includes the high-speed (HS) PMA without and with low-power mode capability, without and with selective wake-up functionality. Additionally, this document specifies PMAs supporting the signal improvement capability (SIC) mode and the FAST mode in Annex A. The physical medium dependent (PMD) sublayer is not in the scope of this document.

Véhicules routiers — Gestionnaire de réseau de communication (CAN) — Partie 2: Sous-couche de l’unité d'accès au support à haute vitesse (PMA)

General Information

• Status: Published
• Publication Date: 21-Mar-2024
• ICS: 43.040.15 - Car informatics. On board computer systems
• Technical Committee: ISO/TC 22/SC 31 - Data communication
• Drafting Committee: ISO/TC 22/SC 31 - Data communication
• Current Stage: 9092 - International Standard to be revised
• Start Date: 28-Oct-2024
• Completion Date: 13-Dec-2025

Relations

• Revises: ISO 11898-2:2016 - Road vehicles - Controller area network (CAN) - Part 2: High-speed medium access unit
• Effective Date: 06-Jun-2022

Overview

ISO 11898-2:2024 - Road vehicles - Controller area network (CAN) - Part 2: High‑speed physical medium attachment (PMA) sublayer defines the electrical and functional behaviour of the CAN PMA sublayer. The third edition updates static and dynamic PMA parameters, adds support for new PMA parameter sets (including higher bit‑rate operation), and introduces Annex A for Signal Improvement Capability (SIC) and FAST mode operation. The physical medium dependent (PMD) sublayer is explicitly out of scope.

Key topics and technical requirements

• HS‑PMA function and interfaces: Specification of the AUI (TXD, RXD, GND) and the relationship to the PCS (physical coding sublayer) and PMD. Defines CAN_H / CAN_L signalling for dominant (logical 0) and recessive (logical 1) bus states.
• Static and dynamic parameters: Detailed static limits (voltages, leakage, receiver input resistance) and dynamic behaviours (driver symmetry, transmit timeouts, timing behaviour).
• Low‑power and wake‑up: Requirements for HS‑PMA low‑power modes, basic wake‑up, selective wake‑up and wake‑up patterns (WUP/WUF), and bus biasing procedures.
• SIC and FAST modes (Annex A): Normative support for PMAs with signal‑improvement capability to suppress ringing and for FAST RX/TX modes that change how recessive/level states are driven and detected.
• Conformance and testing: References conformance requirements and cross‑references to CAN test plans (e.g., ISO 16845 series).
• Parameter sets for higher bit rates: Revised parameter set tables include support for implementations above 1 Mbit/s and up to several Mbit/s (new parameter set C introduced).

Applications and who uses it

ISO 11898-2:2024 is essential for:

• Transceiver/chip designers implementing CAN HS‑PMA functionality (normal/low‑power, selective wake‑up, SIC/FAST).
• ECU hardware engineers specifying transceiver requirements and EMC/ESD considerations.
• Automotive system architects integrating CAN networks, including high‑speed CAN XL and partial networking (PN) use cases.
• Test labs and certification bodies performing conformance and interoperability testing against PMA requirements.
• Vehicle OEMs and suppliers adopting higher bit‑rate, low‑power, or SIC‑enabled CAN transceivers for next‑generation in‑vehicle networks.

Related standards

• ISO 11898-1 - CAN data link layer and physical signalling (PCS/AUI definitions)
• ISO 16845 series - CAN conformance test plans
• ISO/IEC 7498-1 - OSI basic reference model (terminology and layer mapping)

ISO 11898-2:2024 is a normative reference for designers and integrators focused on robust, interoperable high‑speed CAN transceivers, low‑power operation, and advanced signal‑integrity modes (SIC/FAST) used in modern automotive networks.

Standards Content (Sample)

International
Standard
ISO 11898-2
Third edition
Road vehicles — Controller area
2024-03
network (CAN) —
Part 2:
High-speed physical medium
attachment (PMA) sublayer
Véhicules routiers — Gestionnaire de réseau de
communication (CAN) —
Partie 2: Sous-couche de l’unité d'accès au support à haute
vitesse (PMA)
Reference number
© ISO 2024
All rights reserved. Unless otherwise specified, or required in the context of its implementation, no part of this publication may
be reproduced or utilized otherwise in any form or by any means, electronic or mechanical, including photocopying, or posting on
the internet or an intranet, without prior written permission. Permission can be requested from either ISO at the address below
or ISO’s member body in the country of the requester.
ISO copyright office
CP 401 • Ch. de Blandonnet 8
CH-1214 Vernier, Geneva
Phone: [phone]
Email: [e-mail]
Website: www.iso.org
Published in Switzerland
ii
Contents Page
Foreword .iv
Introduction .v
1 Scope . 1
2 Normative references . 1
3 Terms and definitions . 1
4 Abbreviated terms . 3
5 HS-PMA function . 4
5.1 Base requirements .4
5.2 HS-PMA test circuit .5
5.3 Static parameter .5
5.3.1 Maximum ratings of V , V and V .5
CAN_H CAN_L Diff
5.3.2 Recessive output characteristics, bus biasing active .6
5.3.3 Recessive output characteristics, bus biasing inactive .6
5.3.4 Dominant output characteristics .7
5.3.5 Maximum driver output current .8
5.3.6 PMA static receiver input characteristics, bus biasing active and inactive.9
5.3.7 Receiver input resistance .9
5.3.8 Maximum leakage currents of CAN_H and CAN_L .10
5.4 Dynamic parameter .11
5.4.1 Driver symmetry . .11
5.4.2 Optional transmit dominant timeout .11
5.4.3 Transmitter and receiver timing behaviour .11
5.5 Wake-up from low-power mode . 15
5.5.1 Wake-up procedures . 15
5.5.2 General requirement . . 15
5.5.3 Basic wake-up . 15
5.5.4 Via wake-up pattern . 15
5.5.5 Selective wake-up .18
5.5.6 Bus biasing procedure . 23
6 Conformance .25
Annex A (normative) HS-PMA with SIC mode and FAST mode .26
Annex B (informative) ECU and network design .55
Annex C (informative) PN physical layer modes .63
Bibliography .64

iii
Foreword
ISO (the International Organization for Standardization) is a worldwide federation of national standards
bodies (ISO member bodies). The work of preparing International Standards is normally carried out through
ISO technical committees. Each member body interested in a subject for which a technical committee
has been established has the right to be represented on that committee. International organizations,
governmental and non-governmental, in liaison with ISO, also take part in the work. ISO collaborates closely
with the International Electrotechnical Commission (IEC) on all matters of electrotechnical standardization.
The procedures used to develop this document and those intended for its further maintenance are described
in the ISO/IEC Directives, Part 1. In particular, the different approval criteria needed for the different types
of ISO document should be noted. This document was drafted in accordance with the editorial rules of the
ISO/IEC Directives, Part 2 (see www.iso.org/directives).
ISO draws attention to the possibility that the implementation of this document may involve the use of (a)
patent(s). ISO takes no position concerning the evidence, validity or applicability of any claimed patent
rights in respect thereof. As of the date of publication of this document, ISO had not received notice of (a)
patent(s) which may be required to implement this document. However, implementers are cautioned that
this may not represent the latest information, which may be obtained from the patent database available at
www.iso.org/patents. ISO shall not be held responsible for identifying any or all such patent rights.
Any trade name used in this document is information given for the convenience of users and does not
constitute an endorsement.
For an explanation of the voluntary nature of standards, the meaning of ISO specific terms and expressions
related to conformity assessment, as well as information about ISO's adherence to the World Trade
Organization (WTO) principles in the Technical Barriers to Trade (TBT), see www.iso.org/iso/foreword.html.
This document was prepared by Technical Committee ISO/TC 22, Road vehicles, Subcommittee SC 31, Data
communication.
This third edition cancels and replaces the second edition (ISO 11898-2:2016), which has been technically
revised.
The main changes are as follows:
— Clause 5 is restructured, the parameters are categorized by static parameter and dynamic parameter;
— Table 13 with bit rates above 1 Mbit/s and up to 2 Mbit/s is in this edition Table 15 (parameter set
A). Table 14 with bit rates above 2 Mbit/s and up to 5 Mbit/s is now Table 16 (parameter set B). The
parameter set C (see Table 17 and Table 18) in this edition is newly introduced;
— Annex A in this edition is newly introduced; it specifies HS-PMAs with the SIC mode and the FAST mode.
Annex B and Annex C in this edition are Annex A and Annex B in the previous edition. The content is
unchanged.
A list of all parts in the ISO 11898 series can be found on the ISO website.
Any feedback or questions on this document should be directed to the user’s national standards body. A
complete listing of these bodies can be found at www.iso.org/members.html.

iv
Introduction
The ISO 11898 series provides requirement specifications for the CAN data link layer and physical layer. It
is intended for chip implementers, e.g. ISO 11898-1 for CAN protocol controllers and this document for CAN
transceivers. Related conformance test plans are given in the ISO 16845 series. The CAN data link layer
models the open system interconnect (OSI) data link layer; it is internally subdivided into logic link control
(LLC) and medium access control (MAC). ISO 11898-1 also specifies the CAN physical coding sublayer (PCS)
by means of the attachment unit interface (AUI). Optionally, the PCS also provides the PWM encoding to be
linked to a CAN SIC XL transceiver, which provides the PWM decoding.
The open system interconnect (OSI) layers above the data link layer (e.g. the network layer) are not specified
in the ISO 11898 series.
Figure 1 shows the relation between the OSI layers and the CAN sublayers.
Key
AUI attachment unit interface
MDI medium dependent interface
a
Only supported by CAN XL.
Figure 1 — CAN data link and physical sublayers relation to the OSI model

v
International Standard ISO 11898-2:2024(en)
Road vehicles — Controller area network (CAN) —
Part 2:
High-speed physical medium attachment (PMA) sublayer
1 Scope
This document specifies physical medium attachment (PMA) sublayers for the controller area network
(CAN). This includes the high-speed (HS) PMA without and with low-power mode capability, without and
with selective wake-up functionality. Additionally, this document specifies PMAs supporting the signal
improvement capability (SIC) mode and the FAST mode in Annex A. The physical medium dependent (PMD)
sublayer is not in the scope of this document.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their content constitutes
requirements of this document. For dated references, only the edition cited applies. For undated references,
the latest edition of the referenced document (including any amendments) applies.
ISO/IEC 7498-1, Information technology — Open Systems Interconnection — Basic Reference Model: The Basic Model
1)
ISO 11898-1 , Road vehicles — Controller area network (CAN) — Part 1: Data link layer and physical signalling
3 Terms and definitions
For the purposes of this document, the terms and definitions given in ISO/IEC 7498-1, ISO 11898-1 and the
following apply.
ISO and IEC maintain terminology databases for use in standardization at the following addresses:
— ISO Online browsing platform: available at https:// www .iso .org/ obp
— IEC Electropedia: available at https:// www .electropedia .org/
3.1
active recessive
intermediate high-speed physical medium attachment (HS-PMA) output drive with a dedicated lower than
nominal impedance at transitions from dominant state or level_0 state towards the passive recessive (3.14)
state with a dedicated duration
3.2
attachment unit interface
AUI
interface between the physical coding sublayer (PCS) (3.15) and the physical medium attachment (PMA) (3.16)
sublayer
3.3
bus
shared medium of any topology
1) Third edition under preparation. Stage at the time of publication: ISO/DIS 11898-1:2024.

3.4
bus state
state of the medium dependent interface (MDI) (3.11), which is dominant or recessive if the physical medium
attachment (PMA) (3.16) sublayer is in arbitration mode, or is level_0 or level_1 otherwise
Note 1 to entry: The dominant state represents the logical 0 and the recessive state represents the logical 1. During
simultaneous transmission of dominant and recessive bits, the resulting bus state is dominant. When no transmission
is in progress, the bus (3.3) is idle. During idle time, it is in recessive state.
Note 2 to entry: The level_0 state represents the logical 0, and the level_1 state represents the logical 1.
3.5
CAN_H, CAN_L
pair of ports, where V – V is positive at dominant bus state (3.4) and level_0 bus state
CAN_H CAN_L
3.6
edge
difference in bus states (3.4) between two consecutive time quanta
3.7
FAST RX mode
mode in which the physical medium attachment (PMA) (3.16) sublayer drives the bus state (3.4) recessive and
the receive thresholds are adjusted to distinguish between the bus states level_0 and level_1
3.8
FAST TX mode
mode in which the physical medium attachment (PMA) (3.16) sublayer drives the bus states (3.4) level_0 and
level_1, which are not able to overwrite each other
3.9
legacy implementation
HS-PMA implementation compliant with previous ISO 11898-2 editions
3.10
low-power mode
mode in which the transceiver is not capable of transmitting or receiving frames, except for the purposes of
determining if a WUP or WUF is being received
3.11
MDI
medium dependent interface
electrical interface consisting of CAN_H and CAN_L, that defines the signal transfer between the physical
medium dependent (PMD) sublayer and the physical medium attachment (PMA) (3.16) sublayer
3.12
nominal bit time
duration of one bit in the arbitration phase
3.13
normal-power mode
mode in which the transceiver is capable of transmitting and receiving
3.14
passive recessive
final high-speed physical medium attachment (HS-PMA) output drive with nominal impedance, also known
as recessive
3.15
physical coding sublayer
PCS
sublayer of the open system interconnect (OSI) physical layer that performs bit encoding/decoding and
synchronization
3.16
physical medium attachment
PMA
sublayer of the open system interconnect (OSI) physical layer that converts physical signals into logical
signals and vice versa
3.17
PWM decoding
PWMD
physical medium attachment (PMA) (3.16) sublayer function decoding the pulse-width modulation (PWM) bit
streams into the non-return-to-zero (NRZ) bit streams
3.18
PWM encoding
PWME
physical coding sublayer (PCS) (3.15) function encoding the non-return-to-zero (NRZ) bit streams into the
pulse-width modulation (PWM) bit streams
3.19
receiver
node that, while the bus (3.3) is not idle, is neither a transmitter (3.23) nor is it integrating
3.20
RXD
port of the attachment unit interface (AUI) (3.2) used to transmit the actual state of the physical medium, in
binary format, to the physical coding sublayer (PCS) (3.15)
3.21
signal improvement capability
SIC
capability to suppress the ringing on the MDI
Note 1 to entry: It is as specified in the high-speed physical medium attachment (HS-PMA) implementation parameter
set C in Table 14 and Table 17.
3.22
SIC mode
mode according to the high-speed physical medium attachment (HS-PMA) during the arbitration phase
Note 1 to entry: For PMA implementations, it is according to parameter set C or Annex A.
3.23
transmitter
node sending CAN frames
3.24
TXD
port of the attachment unit interface (AUI) (3.2) driven by the physical coding sublayer (PCS) (3.15) to control
how the physical medium attachment (PMA) (3.16) influences the actual state of the physical medium
4 Abbreviated terms
For the purposes of this document, the symbols and abbreviated terms given in ISO 11898-1 and the
following apply. If the definition of the term in this document is different from the definition in ISO 11898-1,
this definition applies.
CAN controller area network
DLC data length code
ECU electronic control unit
EMC electromagnetic compatibility
ESD electro static discharge
GND ground
HS-PMA high-speed PMA
NRZ non-return-to-zero
OSI open layer system
PMD physical medium dependent
PN partial networking
PWM pulse width modulation
RF radio frequency
WUF wake-up frame
WUP wake-up pattern
5 HS-PMA function
5.1 Base requirements
The HS-PMA comprises one transmitter and one receiving entity. It shall be able to bias the connected
physical medium, an electric two-wire cable, relative to a common ground. The transmitter entity shall
drive a differential voltage between the CAN_H and CAN_L signals to signal a logical 0 (dominant) or shall
not drive a differential voltage to signal a logical 1 (recessive) to be received by other nodes connected to the
very same medium. These two signals are the interface to the PMD sublayer.
The HS-PMA shall provide an AUI to the physical coding sublayer as specified in ISO 11898-1. It comprises the
TXD and RXD signals as well as the GND signal. The TXD signal receives from the physical coding sublayer
the bit stream to be transmitted on the MDI. The RXD signal transmits to the physical coding sublayer the
bit stream received from the MDI.
Implementations that comprise one or more HS-PMAs shall at least support the normal-power mode of
operation. A low-power mode may be implemented.
Some of the items specified in the following depend on the operation mode of the (part of the) implementation,
in which the HS-PMA is included.
Table 1 shows the possible combinations of HS-PMA operating modes and expected behaviour.
Table 1 — HS-PMA operating modes and expected behaviour
Operating mode Bus-biasing behaviour Transmitter behaviour
a
Normal-power mode Bus biasing active Dominant or recessive
Low-power mode Bus biasing active or inactive Recessive
a
Depends on input conditions as described in this document.

Parameters given in Clause 5 shall be fulfilled throughout the operating temperature range and supply
voltage range (if not explicitly specified for unpowered) as specified individually for every HS-PMA
implementation.
5.2 HS-PMA test circuit
The outputs of the HS-PMA implementation to the CAN signals are called CAN_H and CAN_L, TXD is the
transmit data input and RXD is the receive data output. Figure 2 shows the external circuit used to measure
the specified voltage and current parameters. R represents the effective resistive load (bus load) for an
L
HS-PMA implementation, when used in a network, and C represents an optional split-termination capacitor.
The values of R and C vary for different parameters that the HS-PMA implementation needs to meet and
L 1
are given as condition in the tables of related parameters.
Key
1 PMA implementation
V differential voltage between CAN_H and CAN_L wires
Diff
V single-ended voltage on CAN_H wire
CAN_H
V single-ended voltage on CAN_L wire
CAN_L
C capacitive load on RXD
RXD
C optional split-termination capacitor
C differential capacitive load
R differential load resistance
L
a
Power supply for the PMA implementation.
Figure 2 — HS-PMA test circuit
5.3 Static parameter
5.3.1 Maximum ratings of V , V and V
CAN_H CAN_L Diff
Table 2 specifies upper and lower limit static voltages, which can be applied to CAN_H and CAN_L without
causing damage, while V stays within in its own maximum rating range.
Diff
Table 2 — HS-PMA maximum ratings of V , V and V
CAN_H CAN_L Diff
Value
Parameter description Notation
Min. Max.
[V] [V]
a
Maximum rating V −5,0 +10,0
Diff
V ,
CAN_H
General maximum rating −27,0 +40,0
V
CAN_L
V ,
CAN_H
Optional: Extended maximum rating −58,0 +58,0
V
CAN_L
a
This is required regardless whether general or extended maximum rating for V and V is
CAN_H CAN_L
fulfilled.
Applies to HS-PMA implementation powered and unpowered conditions. Applies to transmit data input
de-asserted and transmit data input (TXD) becomes asserted while CAN_H or/and CAN_L connected to
a fixed voltage.
The maximum rating for V excludes that all combinations of V and V are compliant to this
Diff CAN_H CAN_L
document. V = V − V , see Figure 2.
Diff CAN_H CAN_L
5.3.2 Recessive output characteristics, bus biasing active
Table 3 specifies the recessive output characteristics when bus biasing is active.
Table 3 — HS-PMA recessive output characteristics, bus biasing active
Value
Parameter Notation
Min. Nom. Max.
[V] [V] [V]
a
Single-ended output voltage on CAN_H V +2,0 +2,5 +3,0
CAN_H
b
Single-ended output voltage on CAN_H V +2,137 +2,5 +2,887
CAN_H_rec
a
Single-ended output voltage on CAN_L V +2,0 +2,5 +3,0
CAN_L
b
Single-ended output voltage on CAN_L V +2,137 +2,5 +2,887
CAN_L_rec
Differential output voltage V −0,5 0 +0,05
Diff
NOTE  The requirements in this table apply concurrently. Therefore, not all combinations of V and V are compliant
CAN_H CAN_L
with the defined differential output voltage.
a
Measurement setup according to Figure 2 (including implementations with selective wake-up function):
R > 10 Ω (not present)
L
C = 0 pF (not present)
C = 0 pF (not present)
C = 0 pF (not present)
RXD
b
Measurement setup according to Figure 2:
R = 60 Ω (tolerance ≤ ± 1 %)
L
C = 0 pF (not present)
C = 0 pF (not present)
C = 0 pF (not present)
RXD
5.3.3 Recessive output characteristics, bus biasing inactive
Table 4 specifies the recessive output characteristics when bus biasing is inactive.

Table 4 — HS-PMA recessive output characteristics, bus biasing inactive
a
Value
Parameter Notation
Min. Nom. Max.
[V] [V] [V]
Single-ended output voltage on CAN_H V −0,1 0 +0,1
CAN_H
Single-ended output voltage on CAN_L V −0,1 0 +0,1
CAN_L
Differential output voltage V −0,2 0 +0,2
Diff
NOTE  See 5.5.6 to determine when bias is inactive.
a
Measurement setup according to Figure 2:
R > 10 Ω (not present)
L
C = 0 pF (not present)
C = 0 pF (not present)
C = 0 pF (not present)
RXD
5.3.4 Dominant output characteristics
Table 5 specifies the output characteristics during dominant state. Figure 3 illustrates the voltage range for
the dominant state.
Table 5 — HS-PMA dominant output characteristics
a
Value
b
Parameter Notation Condition
Min. Nom. Max.
[V] [V] [V]
Single-ended voltage on CAN_H V +2,75 +3,5 +4,5 R = 50 Ω to 65 Ω
CAN_H L
Single-ended voltage on CAN_L V +0,5 +1,5 +2,25 R = 50 Ω to 65 Ω
CAN_L L
Differential voltage on normal bus load V +1,5 +2,0 +3,0 R = 50 Ω to 65 Ω
Diff L
Differential voltage on effective resistance Not
V +1,5 +5,0 R = 2 240 Ω (See NOTE)
Diff L
during arbitration defined
Optional: Differential voltage on extended
V +1,4 +2,0 +3,3 R = 45 Ω to 70 Ω
Diff L
bus load range
NOTE  Assuming a maximum R of 70 Ω, this scenario covers a 32-node network (2 240 Ω/70 Ω = 32), 2 240 Ω is emulating a
L
situation with up to 32 nodes transmitting dominant value simultaneously. In such case, the effective load resistance for single
nodes decreases (a node does drive only a part of the nominal bus load).
a
Requirements given in this table apply concurrently. Therefore, not all combinations of V and V are compliant with
CAN_H CAN_L
the defined differential voltage (see Figure 3).
b
Measurement setup according to Figure 2:
C = 0 pF (not present)
C = 0 pF (not present)
C = 0 pF (not present)
RXD
Key
Y V and V
CAN_H CAN_L
1 range of V
CAN_H(dom)
V differential voltage between CAN_H and CAN_L wires
Diff
V single-ended voltage on CAN_H wire
CAN_H
V single-ended voltage on CAN_L wire
CAN_L
Figure 3 — Voltage range of V during dominant state of CAN node, when V varies from
CAN_H CAN_L
minimum to maximum voltage level (50-Ω to 65-Ω bus-load condition)
5.3.5 Maximum driver output current
Table 6 specifies the maximum HS-PMA driver output current.
Table 6 — Maximum HS-PMA driver output current
a
Value
Parameter Notation Condition
Min. Max.
[mA] [mA]
Absolute current on CAN_H I not specified 115 −3 V ≤ V ≤ +18 V
CAN_H CAN_H
Absolute current on CAN_L I not specified 115 −3 V ≤ V ≤ +18 V
CAN_L CAN_L
NOTE It is expected that the implementation does not stop driving its output dominant when the differential voltage between
CAN_H and CAN_L is outside the limits given in the condition column. The minimum output current is implicitly specified in
Table 5 and thus can be expected to be above 30 mA.
a
Measurement setup according to Figure 2:
R > 10 Ω (not present)
L
C = 0 pF (not present)
C = 0 pF (not present)
C = 0 pF (not present)
RXD
5.3.6 PMA static receiver input characteristics, bus biasing active and inactive
Table 7 specifies the voltage ranges for the HS-PMA static receiver in low-power mode, when the bus biasing
is active.
Table 7 — HS-PMA static receiver input characteristics, bus biasing active
a
Value
Parameter Notation Condition
Min. Max.
[V] [V]
Recessive state differential input voltage range −12,0 V ≤ V ≤ +12,0 V
CAN_L
V −3,0 +0,5
Diff
−12,0 V ≤ V ≤ +12,0 V
CAN_H
Dominant state differential input voltage range −12,0 V ≤ V ≤ +12,0 V
CAN_L
V +0,9 +8,0
Diff
12,0 V ≤ V ≤ +12,0 V
CAN_H
a
Measurement setup according Figure 2:
R > 10 Ω (not present)
L
C = 0 pF (not present)
C = 0 pF (not present)
C = 0 pF (not present)
RXD
NOTE A negative differential voltage can temporarily occur when the HS-PMA is connected to a medium in which common
mode chokes and/or unterminated stubs are present. The maximum positive differential voltage can temporarily occur when the
HS-PMA is connected to a medium while more than one HS-PMA is sending dominant and concurrently a ground shift between
the sending HS-PMAs is present.
Table 8 specifies the the voltage ranges for the HS-PMA static receiver in low-power mode, when the bus
biasing is inactive.
Table 8 — HS-PMA static receiver input characteristics, bus biasing inactive
a
Value
Parameter Notation Condition
Min. Max.
[V] [V]
Recessive state differential input −12,0 V ≤ V ≤ +12,0 V
CAN_L
V −3,0 +0,4
Diff
voltage range
−12,0 V ≤ V ≤ +12,0 V
CAN_H
Dominant state differential input −12,0 V ≤ V ≤ +12,0 V
CAN_L
V +1,15 +8,0
Diff
voltage range
−12,0 V ≤ V ≤ +12,0 V
CAN_H
a
Measurement setup according Figure 2:
R > 10 Ω (not present)
L
C = 0 pF (not present)
C = 0 pF (not present)
C = 0 pF (not present)
RXD
NOTE A negative differential voltage can temporarily occur when the HS-PMA is connected to a medium in which common
mode chokes and/or unterminated stubs are present. The maximum positive differential voltage can temporarily occur when the
HS-PMA is connected to a medium while more than one HS-PMA is sending dominant and concurrently a ground shift between
the sending HS-PMAs is present.
5.3.7 Receiver input resistance
Figure 4 shows an equivalent circuitry of the HS-PMA internal differential input resistance. Table 9 specifies
the HS-PMA receiver input resistance parameter. Table 10 specifies the HS-PMA receiver input resistance
matching parameters.
Figure 4 — Illustration of HS-PMA internal differential input resistance
Table 9 — HS-PMA receiver input resistance
Value
Parameter Notation Condition
Min. Max.
[kΩ] [kΩ]
a
Differential internal resistance R 12 100
DIFF_pas_rec
−2 V ≤ V
CAN_L
R
SE_pas_rec_H
V ≤ +7 V
Single-ended internal resistance 6 50
CAN_H
R
SE_pas_rec_L
a
R = R + R .
DIFF_pas_rec SE_pas_rec_H SE_pas_rec_L
Table 10 — HS-PMA receiver input resistance matching
Value
Parameter Notation Condition
Min. Max.
V , V :
CAN_L CAN_H
a
Matching of internal resistance m −0,03 +0,03
R
+5 V
a
The matching shall be calculated as m = 2 × (R − R )/(R + R ).
R SE_H SE_L SE_H SE_L
5.3.8 Maximum leakage currents of CAN_H and CAN_L
An unpowered HS-PMA implementation shall not disturb the communication of other HS-PMAs that are
connected to the same medium. Table 11 specifies the HS-PMA maximum leakage currents.
Table 11 — HS-PMA maximum leakage currents on CAN_H and CAN_L, unpowered
Value
Parameter Notation
Min. Max.
[µA] [µA]
I ,
CAN_H
Leakage current on CAN_H, CAN_L −10 +10
I
CAN_L
V = 5 V, V = 5 V, all supply inputs are connected to GND.
CAN_H CAN_L
Positive currents are flowing into the implementation.

5.4 Dynamic parameter
5.4.1 Driver symmetry
In order to achieve a level of RF emission that is acceptably low, the transmitter shall meet the driver signal
symmetry as specified in Table 12.
Table 12 — HS-PMA driver symmetry
c
Value
Parameter Notation
Min. Nom. Max.
a
Driver symmetry based on V v +0,9 +1,0 +1,1
CC sym_vcc
b
Driver symmetry based on V v +0,9 +1,0 +1,1
rec_sum sym_vrec
a
v = (V + V )/V , with V being the power supply of the transmitter
sym_vcc CAN_H CAN_L CC CC
b
v = (V + V )/V , without V reference
sym_vrec CAN_H CAN_L sum CC
V = V + V
rec_sum CAN_H_rec CAN_L_rec
V and V shall be observed during dominant state and recessive state and also during the transition
sym_vcc sym_vrec
from dominant to recessive and vice versa, while TXD is stimulated by a square wave signal with a frequency that
corresponds to the highest bit rate for which the HS-PMA implementation is intended, however, at most 1 MHz
(2 Mbit/s) (HS-PMA in normal-power mode).
c
Measurement setup according to Figure 2:
R = 60 Ω (tolerance ≤ ± 1 %)
L
C = 4,7 nF (tolerance ≤ ± 5 %)
C = 0 pF (not present)
C = 0 pF (not present)
RXD
5.4.2 Optional transmit dominant timeout
An implementation of an HS-PMA may limit the duration of dominant transmission in order not to
prevent other CAN nodes from communication when the TXD input is permanently asserted. The HS-PMA
implementation should implement a timeout. Table 13 recommends the optional HS-PMA transmit dominant
timeout value range.
Table 13 — Optional HS-PMA transmit dominant timeout
a
Value
Parameter Notation
Min. Max.
[ms] [ms]
a
Transmit dominant timeout t 0,8 10,0
dom
a
A minimum value of 0,3 ms is accepted for legacy implementations.
NOTE There is a relation between the t minimum value and the minimum bit rate. A t minimum value of
dom dom
0,8 ms accommodates 17 consecutive dominant bits at bit rates greater than or equal to 21,6 kbit/s and 36 consecutive
dominant bits at bit rates greater than or equal to 45,8 kbit/s. The value 17 reflects PMA implementation attempts to
send a dominant bit and every time sees a recessive level at the receive data input. The value 36 reflects six consecutive
error frames when there is a bit error in the last bit of the first five attempts.
5.4.3 Transmitter and receiver timing behaviour
Figure 5 defines the HS-PMA implementation timing. Table 14 specifies the the HS-PMA implementation
loop-delay requirements for parameter set A, parameter set B, and parameter set C. Table 15 specifies the
HS-PMA implementation data signal timing requirements for parameter set A. Table 16 specifies the HS-
PMA implementation data signal timing requirements for parameter set B. Table 17 and Table 18 specify
HS-PMA implementation data signal timing requirements for parameter set C.
NOTE HS-PMA implementations with signal improvement capability developed prior to this document can refer
to the CiA 601–4 specification.

Key
t nominal bit time of the bit rates the HS-PMA supports
Bit(TXD)
Figure 5 — HS-PMA implementation timing definitions
Table 14 — HS-PMA implementation loop-delay requirement for parameter sets A, B and C
b
Value
Parameter Notation
Min. Max.
[ns] [ns]
a
Loop delay for parameter set A and parameter set B t not specified 255
Loop
a
Loop delay for parameter set C t not specified 190
Loop
Propagation delay from TXD to CAN_H/CAN_L for
t not specified 80
prop(TXD_BUS)
parameter set C
Propogation delay from CAN_H/CAN_L to RXD for
t not specified 110
prop(BUS_RXD)
parameter set C
a
Time span from signal edge on TXD input to the next signal edge with the same polarity on RXD output, the
maximum of delay of both signal edges is to be considered.
b
Measurement setup according to Figure 2:
R = 60 Ω (tolerance ≤ ± 1 %)
L
C = 0 pF (not present)
C = 100 pF (tolerance ≤ ± 1 %)
C = 15 pF (tolerance ≤ ± 1 %)
RXD
Measurement according to Figure 5:
The input signal on TXD shall have rise and fall times (10 %/90 %) of less than 10 ns.

Table 15 — HS-PMA implementation data signal timing requirements for parameter set A
d
Value
Parameter Notation
Min. Max.
[ns] [ns]
a
Transmitted recessive bit width variation t −65 +30
ΔBit(Bus)
b
Received recessive bit width variation t −100 +50
ΔBit(RXD)
c
Receiver timing symmetry t −65 +40
ΔREC
a
tt=− t
ΔBitB()us BitB()us BitT()XD
b
tt=− t
ΔBitRXD BitRXD BitTXD
() () ()
c
tt=− t
ΔRec BitR()XD BitB()us
The requirements in this table apply concurrently. Therefore, not all combinations of t and t are
ΔBit(Bus) ΔRec
compliant with t .
ΔBit(RXD)
d
Measurement setup according to Figure 2:
R = 60 Ω (tolerance ≤ ± 1 %)
L
C = 0 pF (not present)
C = 100 pF (tolerance ≤ ± 1 %)
C = 15 pF (tolerance ≤ ± 1 %)
RXD
Measurement according to Figure 5:
The input signal on TXD shall have rise and fall times (10 %/90 %) of less than 10 ns.
NOTE Limits for t and t are not defined for intended use with bit rates up to 1 Mbit/s.
Bit(Bus) Bit(RXD)
Table 16 — HS-PMA implementation data signal timing requirements for parameter set B
d
Value
Parameter Notation
Min. Max.
[ns] [ns]
a
Transmitted recessive bit width variation −45 +10
t
ΔBitB()us
b
Received recessive bit width variation t −80 +20
ΔBitRXD
()
c
Receiver timing symmetry variation −45 +15
t
ΔRec
a
tt=− t
ΔBitBus BitBus BitTXD
() () ()
b
tt=− t
ΔBitR()XD BitR()XD BitT()XD
c
tt=− t
ΔRec BitR()XD BitB()us
The requirements in this table apply concurrently. Therefore, not all combinations of t and t are
ΔBit(Bus) ΔRec
compliant with t .
ΔBit(RXD)
d
Measurement setup according to Figure 2:
R = 60 Ω (tolerance ≤ ± 1 %)
L
C = 0 pF (not present)
C = 100 pF (tolerance ≤ ± 1 %)
C = 15 pF (tolerance ≤ ± 1 %)
RXD
Measurement according to Figure 5:
The input signal on TXD shall have rise and fall times (10 %/90 %) of less than 10 ns.
NOTE Limits for t and t are not defined for intended use with bit rates up to 1 Mbit/s.
Bit(Bus) Bit(RXD)
Table 17 — HS-PMA implementation data signal timing requirements for parameter set C
d
Value
Parameter Notation
Min. Max.
[ns] [ns]
a
Transmitted recessive bit width variation t −10 +10
ΔBitB()us
b
Received recessive bit width variation −30 +20
t
ΔBitR()XD
c
Receiver timing symmetry variation −20 +15
t
ΔRec
a
tt=− t
ΔBitB()us BitB()us BitT()XD
b
tt=− t
ΔBitR()XD BitR()XD BitT()XD
c
tt=− t
ΔRec BitR()XD BitB()us
All requirements in this table apply concurrently. Therefore, not all combinations of t and t are
ΔBit(Bus) ΔRec
compliant with t .
ΔBit(RXD)
d
Measurement setup according to Figure 2:
R = 60 Ω (tolerance ≤ ± 1 %)
L
C = 0 pF (not present)
C = 100 pF (tolerance ≤ ± 1 %)
C = 15 pF (tolerance ≤ ± 1 %)
RXD
Table 18 specifies the HS-PMA implementation SIC timing and impedance for parameter set C.
Table 18 — HS-PMA implementation SIC timing and impedance for parameter set C
Value
Parameter Notation Condition
Min. Max.
Differential internal resistance R 75 Ω 133 Ω +2 V ≤ V ≤ V –2 V, if
DIFF_act_rec CAN_H/L CC
(CAN_H to CAN_L) R fulfils R otherwise
SE SE_act_rec
–12 V ≤ V ≤ +12 V
CAN_H/L
Optional internal single-ended resist- R 37,5 Ω 66,5 Ω +2 V ≤ V ≤ V –2 V, if R fulfils
SE_SIC_act_rec CAN_H/L CC SE
ance R otherwise −12 V ≤ V ≤ V
SE_SIC CAN_H/L CC
+12 V
Start time of active signal improve- t n.a. 120 ns Measured from rising TXD edge
act_rec_start
ment phase with <5 ns slope at 50 % threshold
End time of active signal improve- t 355 ns n.a.
act_rec_end
ment phase
Start time of passive recessive phase t n.a. 530 ns Measured from rising TXD edge
pas_rec_start
with < 5 ns slope at 50 % threshold with
a
R ≥ min. R and R ≥ min. R .
DIFF DIFF_REC SE SE
a
Formerly specified in ISO 11898-2:2016, Table 10.
Figure 6 defines the SIC timing.

Figure 6 — SIC timing definitions
5.5 Wake-up from low-power mode
5.5.1 Wake-up procedures
When an implementation comprising one or more HS-PMAs implements a low-power mode, the HS-PMA can
signal a wake-up event. Table 19 lists the wake-up procedures for defined types of HS-PMA implementations.
Table 19 — HS-PMA wake-up implementations
Type of HS-PMA implementation Required wake-up mechanism
Without low-power mode No wake-up
With low-power mode, but without selective wake- Either basic wake-up or wake-up pat-
up tern (WUP) wake-up
With selective wake-up Selective wake-up frame (WUF) and
wake-up pattern (WUP) wake-up
5.5.2 General requirement
In case more than one wake-up procedure is implemented in an HS-PMA, the wake-up procedure to be used
shall be configurable.
5.5.3 Basic wake-up
After having received a dominant state for the duration of at least t , the HS-PMA shall detect a wake-up.
Filter
5.5.4 Via wake-up pattern
Upon receiving two consecutive dominant states each for duration of at least t , separated by a recessive
Filter
state with a duration of at least t , a wake-up event shall happen. This method is illustrated inFigure 7.
Filter
Key
1 INI state
2 state A
3 state B
4 state C: wake-up detected, entering this state shall signal the bus wake-up event
5 wait state
Figure 7 — Wake-up finite state machine
The finite state machine in Figure 7 specifies the wake-up behaviour for all operation modes. When entering
state A the optional timer, t , shall be reset and when entering the Wait state the t timer shall be
Wake Filter
reset. Table 20 specifies the wake-up control timings and Figure 8 defines the wake-up reaction time.

Table 20 — PMA voltage wake-up control timings
Value
Parameter Notation Condition
Min. Max.
[µs] [µs]
a
CAN activity filter time, long t 0,5 5,0 Bus voltages shall be as specified in
Filter
Table 8.
b
CAN activity filter time, short t 0,15 1,8 Bus voltages shall be as specified in
Filter
Table A.2.
Wake-up timeout t 800,0 10 000,0 Optional timer
Wake
Wake-up pattern signalling t not defined 250,0 Measured from the completed wake-
Flag
up pattern, see Figure 8
a
Implementations do not need to meet this timing, in case the “CAN activity filter time, short” is met. It should be noted that
the maximum filter time has an impact to the suitable wake-up pattern, especially at high bit rates. For example, in a 500-kbit/s
network, a wake-up pattern shall carry at least three similar bit levels in a row in order to safely pass the wake-up filter. Shorter
filter time implementations can increase the risk for unwanted bus wake-ups due to noise. The specified range is a compromise
between robustness against unwanted wake-ups and freedom in frame selection.
b
Implementations do not need to meet this timing, in case the “CAN activity filter time, long” is met.
a) Correct wake-up pattern with PMA low-power mode
b) Incorrect wake-up pattern, dominant phase longer than t
Wake
c) Incorrect wake-up pattern, recessive phase longer than t
Wake
Key
1 INI state
2 in state A
3 in state B
4 in state C
5 in Wait state
6 in low-power mode
7 wake-up detected
8 wake-up flagged
Figure 8 — Wake-up reaction time, a) to c)
5.5.5 Selective wake-up
5.5.5.1 General
Upon detection of a wake-up frame (WUF), a wake-up event shall happen. Decoding of CAN frames in either
classical base frame format (CBFF) or classical extended frame format (CEFF) and acceptance as a WUF is
done by the HS-PMA. If enabled, decoding of CAN frames shall be possible in normal-power mode and low-
power mode. The acceptance procedure is described in detail in the following subclauses.
After the bias reaction time, t , has elapsed, the implementation may ignore up to four (or up to eight
Bias
when bit rate higher than 500 kbit/s) frames in CBFF and CEFF and shall not ignore any following frame in
CBFF and CEFF.
In case of erroneous communication, the HS-PMA shall signal a wake-up upon or after an overflow of the
internal error counter.
5.5.5.2 Behaviour during transitions between normal-power mode to low-power mode
If selective wake-up is enabled prior to the mode change and the HS-PMA is not anymore ignoring frames,
decoding of CAN data frames and CAN remote frames shall also be supported during mode transitions,
which have the frame detection functionality enabled. If the received frame is a valid WUF, the transceiver
shall indicate a wake-up. If enabled, decoding of CAN data shall be possible in normal-power mode and low-
power mode.
5.5.5.3 Bit decoding
A received classical CAN frame shall be decoded correctly w
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