SIST-TP CEN/CLC/TR 18202:2025
(Main)Layer model of Quantum Computing
Layer model of Quantum Computing
This document defines a layer model that covers the entire stack of universal gate-based quantum computers. The group of lower-level (hardware) layers are organized in different hardware stacks tailored to different hardware architectures, while the group of higher-level (software) layers are built on top of these and expected to be common for all quantum computing systems. The higher-up in the stack, the more agnostic it will be from underlying layers. Reducing the dependencies between higher and lower layers is a crucial point for optimized quantum computations. A co-requisite point is to allow for a free but well-defined flow of information up and down the higher and lower layers to allow for co-designing hardware and software.
The scope of this Technical Report is restricted to a universal gate-based quantum-computing model, also known as a digital or circuit quantum-computing model, on multiple physical systems such as transmon, spin-qubit, ion-trap, neutral-atom, and others. This document does not apply to technologies like the universal adiabatic quantum-computing model and its heuristic form quantum annealing, if they do not correspond to a gate-based quantum circuit. Due to major architecture differences in lower layers, it does not apply either to the universal photonic one-way quantum computing model even though it is fully compatible with gate-based quantum-computing model. Moreover, quantum computing models that are not universal, such as quantum simulators and special purposes, are also out of scope.
Limiting the scope to a universal gate-based quantum computing model is justified by expected commonalities at the higher layers, mainly above the hardware abstraction layer (HAL), up to the service layer. These commonalities imply a market for software products usable for this wide range of quantum computing technologies.
The present Technical Report is focussed on a high-level (functional) description of the layers involved. Additional details of the individual layers are reserved for other future CEN/CLC/TRs.
Schichtenmodell des Quantencomputings
Modèle en couches de l'informatique quantique
Slojni model kvantnega računalništva
General Information
Standards Content (Sample)
SLOVENSKI STANDARD
01-november-2025
Slojni model kvantnega računalništva
Layer model of Quantum Computing
Schichtenmodell des Quantencomputings
Modèle en couches de l'informatique quantique
Ta slovenski standard je istoveten z: CEN/CLC/TR 18202:2025
ICS:
35.020 Informacijska tehnika in Information technology (IT) in
tehnologija na splošno general
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.
TECHNICAL REPORT CEN/CLC/TR 18202
RAPPORT TECHNIQUE
TECHNISCHER REPORT
September 2025
ICS 35.020
English version
Layer model of Quantum Computing
Modèle en couches de l'informatique quantique Schichtenmodell des Quantencomputings
This Technical Report was approved by CEN on 11 August 2025. It has been drawn up by the Technical Committee CEN/CLC/JTC
22.
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Slovakia, Slovenia, Spain, Sweden, Switzerland, Türkiye and United Kingdom.
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© 2025 CEN/CENELEC All rights of exploitation in any form and by any means
Ref. No. CEN/CLC/TR 18202:2025 E
reserved worldwide for CEN national Members and for
CENELEC Members.
Contents Page
European foreword . 3
Introduction . 4
1 Scope . 5
2 Normative references . 5
3 Terms and definitions . 5
4 Abbreviations . 6
5 Overview . 6
6 Low level hardware and control layers . 8
6.1 Cryogenic solid state . 8
6.1.1 General. 8
6.1.2 Layer 1 – Quantum devices . 8
6.1.3 Layer 2 – Control highway . 8
6.1.4 Layer 3 – Control electronics . 9
6.1.5 Layer 4 – Control software . 9
6.2 Room temperature solid state . 10
6.3 Trapped ions . 10
6.4 Neutral atoms . 11
6.5 Photonic quantum computing . 11
6.6 Other architectures . 11
7 Hardware abstraction layer (HAL) . 12
7.1 General. 12
7.2 Organization of qubits . 12
7.3 The concept of native gates . 12
7.4 Concept of primitive gates . 14
7.5 Concept of measurement . 15
7.6 Interfacing considerations . 15
8 Assembly layer . 15
9 Programming layer . 15
9.1 General. 15
9.2 Programming languages and libraries . 15
9.3 Quantum compilation. 16
10 Service layer . 16
11 Communication unit . 17
11.1 General. 17
11.2 Example information flow . 17
11.2.1 Single user accessing the full quantum stack . 17
11.2.2 Multiple users accessing the full quantum stack . 18
11.2.3 User accessing lower layer . 18
Bibliography . 19
European foreword
This document (CEN/CLC/TR 18202:2025) has been prepared by Technical Committee CEN/CLC/JTC 22
“Quantum Technologies”, the secretariat of which is held by DIN.
Attention is drawn to the possibility that some of the elements of this document may be the subject of
patent rights. CEN shall not be held responsible for identifying any or all such patent rights.
Any feedback and questions on this document should be directed to the users’ national standards body.
A complete listing of these bodies can be found on the CEN website.
Introduction
A layer model is an abstract description of a (computing) system via a common stack of layers. The model
for gate-based quantum computing, in scope of this Technical Report, slices down the overall complexity
of quantum computing into two main groups of layers, addressing this quantum system. The group of
lower layers addresses mainly hardware, and is dependent of the physical platform. The group of upper
layers addresses mostly software at a higher level of abstraction.
The group of lower (hardware) layers comprises multiple stacks, one for each identified architecture
family.
The higher up in the stack the more hardware-agnostic the inner layers of the upper (software) main
layer model will gradually be. By agnostic it is meant that the same system works for different quantum
computing hardware platforms such as solid state quantum computing, ion traps, neutral atoms, optical
quantum computing and topological quantum computing.
This structure decouples the software design from the hardware design to some extent, which has clear
advantages, such as the reputability of algorithms for different hardware. At the same time the structure
does not impose a fully hardware-agnostic group of upper layers to encompass the design of quantum
hardware and software in a co-design approach, that is, adapt software to make optimal use of the
hardware used and the vice versa. This approach is inevitable for current and near-future quantum
computer development, just as it turned out to be vital for classical computers in early stage and current
classical computing disciplines, e.g. in micro-controller design.
One purpose of this document is to define a common language that can be used to describe the features
and functional requirements for each layer of the stack of a quantum computer. Another purpose is to
analyse and describe the interaction between the layers by means of well-defined interfaces. These are
essential steps towards interworking between modules from different origins. The functional description
of each layer ought to offer sufficient guidance on where a desired functionality is to be described, and
what kind of exchange is needed with other modules through the interfaces. The boundaries between the
layers are natural locations for such interfaces. Correctly defining such boundaries demand for careful
analysis of the interaction between the layers.
This limitation keeps technologies like the universal adiabatic quantum-computing model, the universal photonic
one-way quantum computing model and its heuristic form quantum annealing, as out of scope if they do not
correspond to a gate-based quantum circuit.
1 Scope
This document defines a layer model that covers the entire stack of universal gate-based quantum
computers. The group of lower-level (hardware) layers are organized in different hardware stacks
tailored to different hardware architectures, while the group of higher-level (software) layers are built
on top of these and expected to be common for all quantum computing systems. The higher-up in the
stack, the more agnostic it will be from underlying layers. Reducing the dependencies between higher
and lower layers is a crucial point for optimized quantum computations. A co-requisite point is to allow
for a free but well-defined flow of information up and down the higher and lower layers to allow for co-
designing hardware and software.
The scope of this Technical Report is restricted to a universal gate-based quantum-computing model, also
known as a digital or circuit quantum-computing model, on multiple physical systems such as transmon,
spin-qubit, ion-trap, neutral-atom, and others. This document does not apply to technologies like the
universal adiabatic quantum-computing model and its heuristic form quantum annealing, if they do not
correspond to a gate-based quantum circuit. Due to major architecture differences in lower layers, it does
not apply either to the universal photonic one-way quantum computing model even though it is fully
compatible with gate-based quantum-computing model. Moreover, quantum computing models that are
not universal, such as quantum simulators and special purposes, are also out of scope.
Limiting the scope to a universal gate-based quantum computing model is justified by expected
commonalities at the higher layers, mainly above the hardware abstraction layer (HAL), up to the service
layer. These commonalities imply a market for software products usable for this wide range of quantum
computing technologies.
The present Technical Report is focussed on a high-level (functional) description of the layers involved.
Additional details of the individual layers are reserved for other future CEN/CLC/TRs.
2 Normative references
There are no normative references in this document.
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminology databases for use in standardization at the following addresses:
— ISO Online browsing platform: available at https://www.iso.org/obp/
— IEC Electropedia: available at https://www.electropedia.org/
3.1
codesign
design approach where (software) modules query lower layers for identifying the (hardware)
capabilities and limitations of a system and subsequently tailor their behaviour to these capabilities and
limitation
Note 1 to entry: This approach allows for hardware-specific optimizations and adaptations to optimize quantum
computations.
3.2
gate-based quantum computing
sequence of instructions (called a quantum circuit) to chan
...
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