SIST ETS 300 213 E1:2003

Network Aspects (NA); Metropolitan Area Network (MAN); Physical layer convergence procedure for 2,048 Mbit/s

DE/NA-053025

Omrežni vidiki (NA) – Velemestno omrežje (MAN) – Konvergenčni postopek na fizični plasti (PLCP) za hitrost 2,048 Mbit/s

General Information

• Status: Published
• Publication Date: 30-Nov-2003
• ICS: 35.110 - Networking
• Technical Committee: SS EIT - Technical Board for the electrotechnical, information technology and telecommunications fields
• Current Stage: 6060 - National Implementation/Publication (Adopted Project)
• Start Date: 01-Dec-2003
• Due Date: 01-Dec-2003
• Completion Date: 01-Dec-2003
• Ref Project: ETSI ETS 300 213 ed.1 (1992-12) - Network Aspects (NA); Metropolitan Area Network (MAN); Physical layer convergence procedure for 2,048 Mbit/s

Standards Content (Sample)

SLOVENSKI STANDARD
SIST ETS 300 213 E1:2003
01-december-2003
2PUHåQLYLGLNL1$±9HOHPHVWQRRPUHåMH0$1±.RQYHUJHQþQLSRVWRSHNQD
IL]LþQLSODVWL3/&3]DKLWURVW0ELWV
Network Aspects (NA); Metropolitan Area Network (MAN); Physical layer convergence
procedure for 2,048 Mbit/s
Ta slovenski standard je istoveten z: ETS 300 213 Edition 1
ICS:
35.110 Omreževanje Networking
SIST ETS 300 213 E1:2003 en
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

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SIST ETS 300 213 E1:2003

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SIST ETS 300 213 E1:2003
EUROPEAN ETS 300 213
TELECOMMUNICATION December 1992
STANDARD
Source: ETSI TC-NA Reference: DE/NA-053025
ICS: 33.040
Network, access, MAN
Key words:
Network Aspects (NA);
Metropolitan Area Network (MAN)
Physical layer convergence procedure for
2,048 Mbit/s
ETSI
European Telecommunications Standards Institute
ETSI Secretariat
F-06921 Sophia Antipolis CEDEX - FRANCE
Postal address:
650 Route des Lucioles - Sophia Antipolis - Valbonne - FRANCE
Office address:
c=fr, a=atlas, p=etsi, s=secretariat - [e-mail]
X.400: Internet:
Tel.: [phone] - Fax: [phone]
Copyright Notification: No part may be reproduced except as authorized by written permission. The copyright and the
foregoing restriction extend to reproduction in all media.
© European Telecommunications Standards Institute 1992. All rights reserved.
New presentation - see History box

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ETS 300 213: December 1992
Whilst every care has been taken in the preparation and publication of this document, errors in content,
typographical or otherwise, may occur. If you have comments concerning its accuracy, please write to
"ETSI Editing and Committee Support Dept." at the address shown on the title page.

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ETS 300 213: December 1992
Contents
Foreword .5
1 Scope .7
2 Normative references.7
3 Definitions.7
4 Symbols and abbreviations .7
1)
5 Physical Layer Convergence Procedure (PLCP) for(E1 based systems .8
5.1 Introduction .8
5.1.1 E1 relationship to the PLCP .8
5.2 The PLCP frame format.8
5.3 PLCP field definitions.9
5.3.1 Framing octets (A1, A2) .9
5.3.2 Path overhead identifier (P0.P9) .9
5.3.3 PLCP path overhead octets .10
5.3.3.1 PLCP path user channel (F1) .10
5.3.3.2 Bit interleaved parity - 8 (B1) .10
5.3.3.3 PLCP path status (G1) .10
5.3.3.4 DQDB layer management information octets (M1, M2) .11
5.3.3.5 Stuffing (octet C1).11
5.3.3.6 Growth octets (Z1.Z4).11
5.3.4 Trailer octets.11
5.4 PLCP behaviour during faults .12
5.5 PLCP behaviour during DQDB layer out of service .12
5.6 PLCP framing .12
5.6.1 Link status signal operations table .15
5.6.2 Physical layer frame timing operations table.16
History.17

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ETS 300 213: December 1992
Foreword
This European Telecommunication Standard (ETS) has been prepared by the Network Aspects (NA)
Technical Committee of the European Telecommunications Standards Institute (ETSI).
This ETS details the physical layer convergence procedure for an European Metropolitan Area Network
(MAN) based on the Distributed Queue Dual Bus (DQDB) access method as defined in IEEE Standard
802.6 [6] operating at a transmission rate of 2,048 Mbit/s in accordance with CCITT Recommendation
G.703 [2].

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1 Scope
This European Telecommunication Standard (ETS) defines the physical layer convergence procedure at
2,048 Mbit/s for use in the context of a subnetwork of a Metropolitan Area Network (MAN). Additional slot
mappings for use in transit networks and use of methods defined in this ETS for other purposes are
outside the scope of this ETS.
Methods of testing will be the subject of separate arrangements.
2 Normative references
This ETS incorporates, by dated or undated reference, provisions from other publications. These
normative references are cited at the appropriate places in the text and the publications are listed
hereafter. For dated references, subsequent amendments to, or revisions of any of these publications
apply to this ETS only when incorporated in it by amendment or revision. For undated references the latest
edition of the publication referred to applies.
[1] CCITT Recommendation G.704 (1991): "Synchronous frame structures used at
primary and secondary hierarchical levels".
[2] CCITT Recommendation G.703 (1991): "Physical/electrical characteristics of
hierarchical digital interfaces".
[3] CCITT Recommendation G.707 (1991): "Synchronous digital hierarchy bit
rates".
[4] CCITT Recommendation G.708 (1991): "Network node interface for the
synchronous digital hierarchy".
[5] CCITT Recommendation G.709 (1991): "Synchronous multiplexing structure".
[6] IEEE Standard 802.6 (1990): "Distributed Queue Dual Bus (DQDB) Subnetwork
of a Metropolitan Area Network (MAN)".
3 Definitions
For the purposes of this ETS, the definitions as defined in IEEE Standard 802.6 [6] shall apply.
4 Symbols and abbreviations
For the purposes of this ETS, the symbols and abbreviations as defined in IEEE Standard 802.6 [6] shall
apply.

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1)
5 Physical Layer Convergence Procedure (PLCP) for(E1 based systems
5.1 Introduction
This ETS provides a convergence procedure in which the Distributed Queue Dual Bus (DQDB) layer is
mapped into a standard transmission system according to CCITT Recommendations G.704 [1] and
G.703 [2] operating at 2,048 Mbit/s as used in public networks. Beyond the provisions of CCITT
Recommendations G.704 [1] and G.703 [2], a 2,375 ms framing period shall be provided to support
transportation of full DQDB slots.
NOTE: The CCITT Recommendation G.704 [1] structure itself provides a 125 μs frame and
physical layer management information.
5.1.1 E1 relationship to the PLCP
The rate, format, electrical characteristics and other attributes of the E1 signal shall be as defined in
CCITT Recommendations G.704 [1] and G.703 [2]. The 1st and 17th octet (time slots 0 and 16) of each
CCITT Recommendation G.704 [1] frame shall not be used for the PLCP. They are left for E1
synchronisation (i.e. frame alignment) and overhead bits compatible with existing equipment.
Therefore, the net bit rate available to the PLCP is 1,920 Mbit/s. The CCITT Recommendation G.704 [1]
nominal frame rate is 8 kHz.
NOTE: The PLCP shall provide sufficient buffering or other provisions to accommodate the
"jump" resulting from the passing of the 2 unavailable octets.
The 2,375 ms PLCP frame shall be aligned with the 0,125 ms (8 kHz) frame of the transmission system.
Therefore, every second 2,375 ms frame starts with a synchronisation octet of an E1 frame. 19 CCITT
Recommendation G.704 [1] frames are contained in one PLCP frame of 2,375 ms. In such a PLCP frame
of 608 octets, 570 octets are available to the PLCP.
5.2 The PLCP frame format
A frame duration of 2,375 ms is chosen to allow efficient mapping of DQDB slots into the E1 frames
based on octets. 4 octets shall be added to each DQDB slot of 53 octets to provide framing and overhead
functions so that each row contains 57 octets. 10 of these rows are placed into one 2,375 ms frame. No
trailing octets are provided (they are not needed as the CCITT Recommendation G.704 [1] systems are
synchronous).
The complete frame structure is shown in figure 1. Each row of bits in the PLCP frame format illustrated in
figure 1 shall be transmitted left to right, top to bottom.

1)
The designation E1 is used for a 2,048 Mbit/s transmission system according to CCITT Recommendations G.703 [2] and
G.704 [1]. It is the first level of the plesiochronous digital hierarchy.

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1 1 1 1 53 octets
A1 A2 P9 Z4 First DQDB Slot
A1 A2 P8 Z3 DQDB Slot
A1 A2 P7 Z2 DQDB Slot
A1 A2 P6 Z1 DQDB Slot
A1 A2 P5 F1 DQDB Slot
A1 A2 P4 B1 DQDB Slot
A1 A2 P3 G1 DQDB Slot
A1 A2 P2 M2 DQDB Slot
A1 A2 P1 M1 DQDB Slot
A1 A2 P0 C1 Last DQDB Slot
2,375 ms
A1,A2: framing octets.
P0.P9: path overhead identifier octet.
C1: cycle stuff counter.
M1,M2: DQDB layer management information octets.
G1: PLCP path status.
B1: Bit Interleaved Parity-8 (BIP-8).
F1: PLCP path user channel.
Z1.Z4: growth octets.
Figure 1: The E1 PLCP frame format
5.3 PLCP field definitions
(Refer to figure 1). The values of fields are described as bit patterns. The leftmost bit of each octet is the
most significant.
5.3.1 Framing octets (A1, A2)
The first two columns (A1, A2) may be used to provide slot delineation. The encoding of the A1 and A2
octets is:
A1 A2
11110110 00101000
These codes are the same patterns as used in the Synchronous Digital Hierarchy (SDH) (CCITT
Recommendations G.707 [3], G.708 [4] and G.709 [5]). Alternatively, slot delineation based on the Header
Check Sequence (HCS) of the DQDB header may be used.
5.3.2 Path overhead identifier (P0.P9)
The third column identifies the PLCP overhead octets contained in the fourth column of figure 1. The
leftmost 6 bits of these octets provide numbering of the 10 rows. The 7th bit is reserved and the rightmost
bit (Least Significant Bit (LSB)) is a parity bit. The reserved bit shall be set to (0). The parity bit provides
odd parity over this field.
Table 1 defines the codes P0.P9, which shall be generated by the PLCP at each node. All other codes
shall be invalid. A code shall also be considered invalid if the parity bit contained in the LSB is not correct.
The response to invalid codes is described in subclause 5.6.

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Table 1: Path overhead identifier codes
P9 001 001 0 1
P8 001 000 0 0
P7 000 111 0 0
P6 000 110 0 1
P5 000 101 0 1
P4 000 100 0 0
P3 000 011 0 1
P2 000 010 0 0
P1 000 001 0 0
P0 000 000 0 1
5.3.3 PLCP path overhead octets
The PLCP path is defined between two adjacent peer PLCP entities. The F1, B1, G1 and C1 PLCP path
overhead octets are related to PLCP operation and shall be terminated/generated at each PLCP on the
subnetwork. The M1 and M2 octets are provided for the transport of DQDB layer management information
octets and shall not be processed by the PLCP sublayer.
5.3.3.1 PLCP path user channel (F1)
The F1 octet is the user channel, which is allocated for user communication purposes between adjacent
PLCPs. The use of this octet in DQDB subnetworks is for further study. The default code for this octet
shall be (00000000).
5.3.3.2 Bit interleaved parity - 8 (B1)
One octet is allocated for PLCP path error monitoring. This function shall be a Bit Interleaved Parity - 8
(BIP-8) code using even parity. The PLCP path BIP-8 is calculated over the 10 x 54 octet structure
(columns 4 to 57, 1 PLCP path overhead octet and 53 DQDB slot octets per row) of the previous PLCP
frame and inserted into the B1 octet of the current PLCP frame.
A BIP-8 is an 8 bit code in which the first bit represents even parity calculated over the first bit of each
octet in the 10 x 54 octet structure, the second bit represents even parity over the second bit of each octet
in the 10 x 54 octet structure, etc. Therefore the BIP-8 code provides for 8 separate even parity codes
covering the corresponding bit of each octet in the 10 x 54 octet structure.
5.3.3.3 PLCP path status (G1)
The G1 octet is allocated to convey the received PLCP status and performance back to the transmitting
PLCP. This octet permits the status of the full duplex PLCP path to be monitored at either PLCP entity.
The G1 octet shall consist of:
- 4 bits for the Far End Block Error (FEBE) code;
- 1 bit for the Alarm Signal (AS);
- 3 bits for a Link Status S
...