ASTM F1771-97
(Test Method)Standard Test Method for Evaluating Gate Oxide Integrity by Voltage Ramp Technique
Standard Test Method for Evaluating Gate Oxide Integrity by Voltage Ramp Technique
SCOPE
1.1 The techniques outlined in this standard are for the purpose of standardizing the procedure of measurement, analysis, and reporting of oxide integrity data between interested parties. This test method makes no representation regarding actual device failure rates or acceptance/rejection criteria. While some suggestions for data analysis are included in later sections of this test method, interpretation of results is beyond the scope of this standard. Any such interpretations should be agreed upon between interested parties prior to testing. For example, a variety of failure criteria are included to permit separation of so-called intrinsic and extrinsic oxide failures.
1.2 This test method covers the procedure for gaging the electrical strength of silicon dioxide thin films with thicknesses ranging from approximately 3 nm to 50 nm. In the analysis of films of 4 nm or less, the impact of direct tunneling on the current-voltage characteristics, and hence the specified failure criteria defined in 5.4, must be taken into account. Since oxide integrity strongly depends on wafer defects, contamination, cleanliness, as well as processing, the users of this test method are expected to include wafer manufacturers and device manufacturers.
1.3 This test method is not structure specific, but notes regarding options for different structures may be found in the appendix. The three most likely structures are simple planar metal-oxide semiconductor (MOS-capacitors) (fabricated or mercury probe), various isolation structures (for example, local oxidation of silicon (LOCOS)), and field effect transistors. This test method assumes that a low resistance ohmic contact is made to the backside of each wafer in each case. For a more detailed discussion of the design and evaluation of test structures for this test method, the reader is referred to the EIA/JEDEC Standard 35-1.
1.4 Failure criteria specified in this test method include both the fixed current limit (soft) and destructive (hard) types. In the past, use of a fixed current limit of 1 µA or more virtually ensured measurement of hard failure, as the thicker, more heavily contaminated oxides of those days typically failed catastrophically as soon as measurable currents were passed. The cleaner processing of thinner oxides now means that oxides will sustain relatively large currents with little or no evidence of failure. While use of fixed current limit testing may still be of value for assessing uniformity issues, it is widely felt that failure to continue oxide breakdown testing to the point of catastrophic oxide failure may mask the presence of defect tails, which are of critical importance in assessing long-term oxide reliability. For this reason, this test method makes provision for use of fixed limit failure criteria if desired and agreed upon by the parties to the testing, but specifies that testing be continued until hard failure is sensed.
1.5 This test method specifically does not include measurement of a charge-to-breakdown (Qbd) parameter. Industry experience with this parameter measured in a ramp-to-failure test such as this indicates that Qbd values so obtained may be unreliable indicators of oxide quality. This is because a large fraction of the value determined is collected in the last steps of the test, and the result is subject to large deviations. Qbd should be measured in a constant current or bounded current ramp test.
1.6 This test method is applicable to both n-type and p-type wafers, polished or having an epitaxial layer. In wafers with epitaxial layers, the conductivity type of the layer should be the same as that of the bulk wafer. While not excluding depletion polarity, it is preferred that measurement polarity should be in accumulation to avoid the complication of a voltage drop across the depletion layer.
1.7 While this test method is primarily intended for use in characterizing the SiO2-silicon systems as stated above, it may be ...
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Designation: F 1771 – 97
Standard Test Method for
Evaluating Gate Oxide Integrity by Voltage Ramp
1
Technique
This standard is issued under the fixed designation F 1771; the number immediately following the designation indicates the year of
original adoption or, in the case of revision, the year of last revision. A number in parentheses indicates the year of last reapproval. A
superscript epsilon (e) indicates an editorial change since the last revision or reapproval.
1. Scope catastrophically as soon as measurable currents were passed.
The cleaner processing of thinner oxides now means that
1.1 The techniques outlined in this standard are for the
oxides will sustain relatively large currents with little or no
purpose of standardizing the procedure of measurement, analy-
evidence of failure. While use of fixed current limit testing may
sis, and reporting of oxide integrity data between interested
still be of value for assessing uniformity issues, it is widely felt
parties. This test method makes no representation regarding
that failure to continue oxide breakdown testing to the point of
actual device failure rates or acceptance/rejection criteria.
catastrophic oxide failure may mask the presence of defect
While some suggestions for data analysis are included in later
tails, which are of critical importance in assessing long-term
sections of this test method, interpretation of results is beyond
oxide reliability. For this reason, this test method makes
the scope of this standard. Any such interpretations should be
provision for use of fixed limit failure criteria if desired and
agreed upon between interested parties prior to testing. For
agreed upon by the parties to the testing, but specifies that
example, a variety of failure criteria are included to permit
testing be continued until hard failure is sensed.
separation of so-called intrinsic and extrinsic oxide failures.
1.5 This test method specifically does not include measure-
1.2 This test method covers the procedure for gaging the
ment of a charge-to-breakdown (Q ) parameter. Industry
electrical strength of silicon dioxide thin films with thicknesses bd
experience with this parameter measured in a ramp-to-failure
ranging from approximately 3 nm to 50 nm. In the analysis of
test such as this indicates that Q values so obtained may be
films of 4 nm or less, the impact of direct tunneling on the bd
unreliable indicators of oxide quality. This is because a large
current-voltage characteristics, and hence the specified failure
fraction of the value determined is collected in the last steps of
criteria defined in 5.4, must be taken into account. Since oxide
the test, and the result is subject to large deviations. Q should
bd
integrity strongly depends on wafer defects, contamination,
be measured in a constant current or bounded current ramp test.
cleanliness, as well as processing, the users of this test method
1.6 This test method is applicable to both n-type and p-type
are expected to include wafer manufacturers and device
wafers, polished or having an epitaxial layer. In wafers with
manufacturers.
epitaxial layers, the conductivity type of the layer should be the
1.3 This test method is not structure specific, but notes
same as that of the bulk wafer. While not excluding depletion
regarding options for different structures may be found in the
polarity, it is preferred that measurement polarity should be in
appendix. The three most likely structures are simple planar
accumulation to void the complication of a voltage drop across
metal-oxide semiconductor (MOS-capacitors) (fabricated or
the depletion layer.
mercury probe), various isolation structures (for example, local
1.7 While this test method is primarily intended for use in
oxidation of silicon (LOCOS)), and field effect transistors. This
characterizing the SiO -silicon systems as stated above, it may
test method assumes that a low resistance ohmic contact is 2
be applied in general terms to the measurement of other
made to the backside of each wafer in each case. For a more
metal-insulator-semiconductor structures if appropriate consid-
detailed discussion of the design and evaluation of test struc-
eration of the characteristics of the other materials is made.
tures for this test method, the reader is referred to the
2 1.8 Measurement conditions specified in this test method
EIA/JEDEC Standard 35-1.
are conservative, intended for thorough analysis of high quality
1.4 Failure criteria specified in this test method include both
oxide-silicon systems, and to provide a regime in which new
the fixed current limit (soft) and destructive (hard) types. In the
users may safely begin testing without encountering undue
past, use of a fixed current limit of 1 μA or more virtually
experimental artifacts. It is recognized that some experienced
ensured measuremen
...
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