ASTM F419-94

Test Method for Determining Carrier Density in Silicon Epitaxial Layers by Capacitance-Voltage Measurements on Fabricated Junction or Schottky Diodes (Withdrawn 2001)

SCOPE
1.1 This test method covers the measurement of carrier density in silicon epitaxial layers. The precision that can be expected depends upon the carrier-density inhomogeneities parallel and perpendicular to the junction and upon the carrier-density level.  
1.2 The measurement requires the formation of Schottky or p-n junction diodes on or in the epitaxial layer. In this sense the method is destructive (see, however, 5.2).  
1.3 Both n- and -type epitaxial layers can be evaluated, on substrates of the same or opposite types, if the layer thickness is greater than twice the zero-bias depletion width plus, for diffused diodes only, the junction depth (1).  This test method is also applicable to bulk material.
1.4 This test method covers the carrier density range from about 4 X 10 13  to about 8 X 10 16  carriers/cm  (resistivity range from about 0.1 to about 100 [omega][dot]cm in -type wafers and from about 0.24 to about 330 [omega][dot]cm in -type wafers).  
1.5 This test method includes procedures for checking both capacitance- and voltage-measuring equipment.
1.6 This test method provides two means of calculating the carrier density from capacitance-voltage data: an incremental method (12.3.1) and a curve-fitting method (12.3.2). Note 1-An alternative method for determining carrier density in epitaxial layers is given in Test Method F1392. This and a related method, DIN 50439, use a mercury-probe Schottky barrier contact rather than a fabricated p-n junction or Schottky diode. Therefore, measurements by Test Method F1392 and DIN 50439 may not be entirely comparable to those made by this test method. DIN 50439 is also applicable to gallium arsenide as well as to silicon.
1.7 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use. Specific hazard statements are given in 11.8 and 11.14.

General Information

• Status: Withdrawn
• Publication Date: 31-Dec-1993
• Withdrawal Date: 09-Oct-2001
• ICS: 31.080.10 - Diodes
• Technical Committee: F01 - Electronics

Standards Content (Sample)

NOTICE: This standard has either been superseded and replaced by a new version or discontinued.
Contact ASTM International (www.astm.org) for the latest information.
Designation: F 419 – 94
Standard Test Method for
Determining Carrier Density in Silicon Epitaxial Layers by
Capacitance-Voltage Measurements on Fabricated Junction
or Schottky Diodes
This standard is issued under the fixed designation F 419; the number immediately following the designation indicates the year of
original adoption or, in the case of revision, the year of last revision. A number in parentheses indicates the year of last reapproval. A
superscript epsilon (e) indicates an editorial change since the last revision or reapproval.
1. Scope 2. Referenced Documents
1.1 This test method covers the measurement of carrier 2.1 ASTM Standards:
density in silicon epitaxial layers. The precision that can be F 95 Test Method for Thickness of Lightly-Doped Silicon
expected depends upon the carrier-density inhomogeneities Epitaxial Layers on Heavily-Doped Silicon Substrates
parallel and perpendicular to the junction and upon the Using an Infrared Dispersive Spectrophotometer
carrier-density level. F 110 Test Method for Thickness of Epitaxial or Diffused
1.2 The measurement requires the formation of Schottky or Layers in Silicon by the Angle Lapping and Staining
p-n junction diodes on or in the epitaxial layer. In this sense the Technique
method is destructive (see, however, 5.2). F 723 Practice for Conversion Between Resistivity and
1.3 Both n- and p-type epitaxial layers can be evaluated, on Dopant Density for Boron-Doped and Phosphorus-Doped
substrates of the same or opposite types, if the layer thickness Silicon
is greater than twice the zero-bias depletion width plus, for F 1392 Test Method for Determining Net Carrier Density
diffused diodes only, the junction depth (1). This test method Profiles in Silicon Wafers by Capacitance-Voltage Mea-
is also applicable to bulk material. surements With a Mercury Probe
1.4 This test method covers the carrier density range from 2.2 DIN Standard:
13 16 3
about 4 3 10 to about 8 3 10 carriers/cm (resistivity DIN 50 439 Determination of the Dopant Concentration
range from about 0.1 to about 100 V·cm in n-type wafers and Profile of a Single Crystal Semiconductor Material by
from about 0.24 to about 330 V·cm in p-type wafers). Means of the Capacitance-Voltage Method and Mercury
1.5 This test method includes procedures for checking both Contact
capacitance- and voltage-measuring equipment.
3. Terminology
1.6 This test method provides two means of calculating the
carrier density from capacitance-voltage data: an incremental 3.1 Definitions of Terms Specific to This Standard:
3.1.1 breakdown voltage— for the purposes of this test
method (12.3.1) and a curve-fitting method (12.3.2).
method, the reverse bias voltage at which the test diode
NOTE 1—An alternative method for determining carrier density in
exhibits a leakage current density of 3 mA/cm .
epitaxial layers is given in Test Method F 1392. This and a related method,
DIN 50 439, use a mercury-probe Schottky barrier contact rather than a
4. Summary of Test Method
fabricated p-n junction or Schottky diode. Therefore, measurements by
Test Method F 1392 and DIN 50 439 may not be entirely comparable to 4.1 The small-signal, high-frequency capacitance of p-n
those made by this test method. DIN 50 439 is also applicable to gallium
junction or Schottky diode is measured as a function of reverse
arsenide as well as to silicon.
bias voltage. The carrier density as a function of depth is
determined from the measured values of capacitance and
1.7 This standard does not purport to address all of the
safety concerns, if any, associated with its use. It is the reverse bias voltage.
responsibility of the user of this standard to establish appro-
5. Significance and Use
priate safety and health practices and determine the applica-
5.1 The carrier density is an important material acceptance
bility of regulatory limitations prior to use. Specific hazard
requirement. In material that is neither too heavily doped nor
statements are given in 11.8 and 11.14.
significantly compensated by impurities of the opposite con-
ductivity type, the resistivity of the epitaxial layer may be
This test method is under the jurisdiction of ASTM Committee F-1 on
determined from the carrier density in accordance with Practice
Electronics and is the direct responsibility of Subcommittee F01.06 on Silicon
Materials and Process Control. F 723.
Current edition approved Aug 15, 1994. Published October 1994. Originally
published as F 419 – 75 T. Last previous edition F 419 – 88.
The boldface numbers in parentheses refer to the list of references at the end of
this test method. Annual Book of ASTM Standards, Vol 10.05.
Copyright © ASTM, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959, United States.
F 419
5.2 This test method is suitable for specification acceptance, 7.9 Toolmaker’s Microscope, Shadowgraph, or Planimeter
process control, and research purposes. Because this test capable of measuring the junction diameter to an accuracy of
method is destructive, measurements are generally made on a 0.5 % or better or the junction area to an accuracy of 1 % or
sampling basis unless the test diode to be fabricated is made an better.
integral part of the device into which the wafer is being 7.10 Shielded Cables for making electrical connections
fabricated. between the probe fixture, power supply, capacitance bridge or
meter, and digital voltmeter or potentiometer.
6. Interferences
8. Sampling
6.1 Stray inductance and capacitance, caused by excessive
lengths of connecting cable, or improper zeroing of the 8.1 Because this test method is destructive (see, however,
capacitance bridge or meter can cause significant errors in the
5.2), it is not generally practical to measure every wafer in a
capacitance measurement. In homogeneous material, such particular lot. A wafer sampling plan shall therefore be agreed
errors result in the calculation of monotonically increasing or
upon between the parties to the test.
decreasing values of carrier density with distance away from 8.2 If the specimen preparation (see 9.1) involves the
the junction.
fabrication of an array of diodes on a given wafer, it may not
6.2 Alternating-frequency test sigals greater than 0.05 V be practical to measure every diode on that wafer. A diode
rms can lead to errors in the measured capacitance.
sampling plan shall therefore be agreed upon between the
parties to the test.
7. Apparatus
9. Test Specimen
7.1 Facilities for fabricating p-n junction or Schottky diodes
on the test specimen.
9.1 Fabricate p-n junctions or Schottky diodes on the
7.2 Capacitance Bridge or Meter, having ranges from 1 to epitaxial layer using planar or mesa technology (see 11.2).
1000 pF full scale, or greater, in multiples of 10 or less. The
10. Calibration
measurement frequency shall be in the range from 0.09 to 1.1
MHz inclusive. The accuracy shall be 1.0 % of full scale or 10.1 Connect shielded cables of a length suitable for mea-
better for each range, and the reproducibility shall be 0.25 % of suring the standard capacitors (see 6.1) to the capacitance
full scale or better. The instrument shall be capable of bridge or meter. Zero the capacitance bridge or meter with the
sustaining external d-c bias of 6200 V or greater and shall be cables connected to the bridge or meter but not to the standard
capable of compensating for an external probe fixture with capacitors.
stray capacitance up to 5 pF or greater. The internal a-c 10.2 Connect the cables to one of the standard capacitors;
measuring signal shall be 0.05 V rms or less. then measure and record the capacitance in picofarads. Dis-
7.3 Digital Voltmeter or Potentiometer, having a sensitivity connect the capacitor.
of 1 mV or better, an accuracy of 0.5 % of full scale or better, 10.3 Connect the cables to the other standard capacitor;
a reproducibility of 0.25 % of full scale or better, an input
measure and record the capacitance in picofarads. Disconnect
impedance of 100 MV or greater, and a common-mode the capacitor.
rejection of 100 dB or greater at 60 Hz.
10.4 To verify that the digital voltmeter or potentiometer is
7.4 D-C Power Supply, continuously variable, capable of within specification over the range from 1 to 200 V, inclusive,
supplying 0 to 6200 V (open circuit) with a ripple of 1 % of
use it to measure the precision voltage source at five or more
the d-c output or less. voltages in that range.
7.5 Curve Tracer, capable of monitoring the reverse and
10.5 If either the capacitance- or voltage-measuring equip-
forward current-voltage characteristics of the diode. The curve ment is not within the required specifications (see 7.2 and 7.3
tracer shall be capable of applying 200 V at 0.1 mA in the
for values), make necessary adjustments in accordance with the
reverse direction and 1.1 V at 1 mA in the forward direction, appropriate instrument instruction manuals to bring equipment
and have a sensitivity of 10 μA/division or better. to within specifications before proceeding with the measure-
7.6 Standard Capacitors of accuracy 0.25 % or better at the ment of the specimen.
measurement frequency. One capacitor shall be in the range
11. Procedure
from 1 to 10 pF inclusive and one shall be in the range from 10
to 100 pF inclusive. 11.1 Unless the epitaxial layer thickness is already known,
measure the epitaxial layer thickness by Test Method F 95 or
7.7 Precision Voltage Source, capable of providing output
voltages from 0 to 200 V. The accuracy of this source shall be Test Method F 110, depending on whether the layer and
substrate are the same or opposite conductivity type, respec-
0.1 % of the output voltage or better.
7.8 Probe Fixture that holds the specimens containing the tively. Estimate the carrier density in the layer to be measured.
diodes; provides probes for making ohmic contact both to the Consult Ref (1) to determine the depletion region width at zero
diffused or barrier region, and to the epitaxial layer; and keeps bias. Double this width to allow for the depletion region
the diode in the dark during the measurement. Vacuum widening that will occur when the required reverse biases are
clamping shall be provided. Contact to the epitaxial layer shall applied (see 11.13 and 11.14). If a diffused junction diode is to
be made either by a front-surface contact or, when the layer and be fabricated, add the anticipated junction depth to this wider
substrate are of the same type, by electrical contact to the depletion width. Make measurements in accordance with the
substrate by means of the vacuum chuck. following procedure only if this wider depletion region width
F 419
(plus junction depth if applicable) is less than or equal to the or meter is connected to the epitaxial layer or substrate (see
epitaxial layer thickness. 11.4), and the high side of the bridge or meter is connected to
the probe that is to contact the barrier or diffused region.
11.2 By means customarily used in microelectronic opera-
tions, fabricate several gated or ungated diodes with an active 11.12 Zero the capacitance bridge or meter as follows:
−4 −2 2
11.12.1 With a nominal 1-V reverse bias applied, and with
area in the range from 5 3 10 to 3 3 10 cm inclusive.
(For circular active areas this range corresponds to diameters in the capacitance bridge or meter set to its least sensitive range,
gently lower the probe so that it just makes contact with the
the range from 0.025 to 0.142 cm (9.9 to 76.8 mils).)
11.2.1 Fabricate junction diodes to have a surface carrier barrier or diffused region of the test diode. Detect the point of
contact by a positive deflection of the capacitance bridge or
density at least 100 times the carrier density of the epitaxial
layer, and a junction depth less than 1.5 μm. meter.
11.12.2 Select the most sensitive range of the capacitance
11.3 Measure and record the active device area, in square
bridge or meter for which the indication does not exceed full
centimetres, to an accuracy of 1 %, or, if the device is circular,
scale.
the device diameter, in centimetres, to an accuracy of 0.5 %.
11.12.3 Raise the probe so that electrical contact to the
NOTE 2—Refer to Appendix X1 for suggested data sheet formats for
barrier or diffused region is just broken.
recording the data if the data collection and calculations are carried out
11.12.4 Adjust the capacitance bridge or meter so that the
manually or off-line.
indication on the selected range, within the accuracy of the
11.4 Transfer the specimen to the probe fixture. Make an
instrument, is 0 pF.
electrical connection from the probe fixture to the epitaxial
11.13 Lower the probe to contact the barrier or diffused
layer as near to the active region as possible. (For epitaxial
region. Apply a nominal 1-V reverse bias to the test diode and
layers on substrates of the same conductivity type, the connec-
measure the capacitance in picofarads. Record the applied
tion can be made to the substrate.)
voltage and measured capacitance, each to three or more
11.5 Make an electrical connection to the barrier or diffused
significant figures, as V and C , respectively. Consider the
1 1
region of the diode by means of a probe. Take care to avoid
voltages to be positive numbers even though reverse biases are
probe forces high enough to cause the probe to penetrate the
involved.
diffused layer of shallow diffused diodes and cause shorting or
11.14 Adjust the voltage to obtain a new value of capaci-
excessive leakage.
tance 4 to 6 % lower than the previous value. Record the
11.6 Connect shielded cables from the probe fixture to the
voltage and capacitance each to three or more significant
curve tracer (see 7.5).
figures as V and C , respectively. Caution—Avoid contact
2 2
11.7 Measure the diode forward resistance, R, in ohms, at
with the probes when bias is applied.
1-V forward bias as follows:
11.15 Repeat 11.14, adjusting the voltage fora4to6%
11.7.1 Measure the diode current that exists at 0.9-V for-
decrease in capacitance at each step, until either the breakdown
ward bias, in milliamperes.
voltage is reached or the capacitance values start to increase
11.7.2 Measure the diode current that exists at 1.1-V for-
with increased reverse bias. When the measurement sequence
ward bias, in milliamperes.
is complete, reduce all biases to zero, raise the probe or probes
11.7.3 Calculate and record R as follows:
and remove the specimen from the probe fixture. Use a
minimum of four data points for the incremental method (see
R 5 200/~I 2 I !
2 1
12.3.1). For the curve-fitting method (see 12.3.2) use a number
where:
of data points consonant with the order of fit expected.
I 5 diode current at 1.1-V forward bias, mA, and
12. Calculations
I 5 diode current at 0.9-V forward bias, mA
...