ASTM F1152-93

Standard Test Method for Dimensions of Notches on Silicon Wafers

SCOPE
1.1 This test method covers a nondestructive procedure to determine whether or not the dimensions of fiducial notches on silicon wafers fall within specified limits.
1.2 The values stated in SI units are to be regarded as the standard. The values given in parentheses are for information only.
1.3  This standard does not purport to address all of the safety problems, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

General Information

• Status: Historical
• Publication Date: 09-Jan-2002
• Technical Committee: F01 - Electronics

Relations

• Replaced By: ASTM F1152-93(2001) - Standard Test Method for Dimensions of Notches on Silicon Wafers
• Effective Date: 10-Jan-2002

Standards Content (Sample)

NOTICE: This standard has either been superseded and replaced by a new version or
withdrawn. Contact ASTM International (www.astm.org) for the latest information.
Designation: F 1152 – 93
AMERICAN SOCIETY FOR TESTING AND MATERIALS
100 Barr Harbor Dr., West Conshohocken, PA 19428
Reprinted from the Annual Book of ASTM Standards. Copyright ASTM
Standard Test Method for
1
Dimensions of Notches on Silicon Wafers
This standard is issued under the fixed designation F 1152; the number immediately following the designation indicates the year of
original adoption or, in the case of revision, the year of last revision. A number in parentheses indicates the year of last reapproval. A
superscript epsilon (e) indicates an editorial change since the last revision or reapproval.
1. Scope maximum and minimum lines on the template.
3.4 The image of the notch sides are compared with a series
1.1 This test method covers a nondestructive procedure to
of angles on the notch angle template and the angle that makes
determine whether or not the dimensions of fiducial notches on
the best fit is chosen as the value of the notch angle.
silicon wafers fall within specified limits.
3.5 No test is provided for the blend radius at the apex of the
1.2 The values stated in SI units are to be regarded as the
notch.
standard. The values given in parentheses are for information
only.
4. Significance and Use
1.3 This standard does not purport to address all of the
4.1 Wafers must be accurately aligned in various processing
safety problems, if any, associated with its use. It is the
equipment during integrated circuit manufacture.
responsibility of the user of this standard to establish appro-
4.2 A notch ground into the edge of the wafer at a specified
priate safety and health practices and determine the applica-
orientation provides a positive method for such alignment. The
bility of regulatory limitations prior to use.
accuracy of the critical dimensions of the notch controls the
2. Referenced Documents possible accuracy of the alignment.
4.3 This test method is specifically directed to the notch
2.1 ASTM Standards:
dimensions specified in SEMI Specifications M 1, but with
E 122 Practice for Choice of Sample Size to Estimate a
2 suitable modifications, the principles of this test method may
Measure of Quality of a Lot or Process
be applied to any desired notch dimensions.
2.2 Military Standard:
4.4 This test method may be used for process control,
MIL-STD-105E Sampling Procedures and Tables for In-
3
quality control, and incoming or outgoing inspection.
spection by Attributes
4.5 Until an index of precision is determined based on an
2.3 SEMI Standard:
4
interlaboratory evaluation, this test method is not recom-
M 1 Specifications for Monocrystalline Silicon Wafers
mended for use in decisions between purchasers and suppliers.
3. Summary of Test Method
5. Interferences
3.1 The wafer is aligned in position on an optical compara-
5.1 Any foreign material or rough spots on the notch edge in
tor and the image of the notch is compared with a series of
the light path may present a distorted image which can result in
templates projected on the screen of the comparator.
the determination of incorrect dimensions.
3.2 First, the wafer is aligned so that the sides of the image
5.2 Alignment of the notch position with respect to the
of the notch contact the image of the alignment pin used to fix
center of the wafer is important in achieving an accurate
the position of the wafer in use. In this case, the image of the
determination of the notch characteristics.
notch bottom must lie on or below the designated line on the
5.3 Wear of grinding tools and process variations may result
notch form/depth template and the image of the wafer edge
in notch edges which are not exactly straight and a nonunique
must lie on or above another designated line on the template.
radius at the apex of the notch. Under these conditions, great
3.3 The wafer is then aligned so that the image of the wafer
care must be taken to align the image of the notch correctly
edge coincides with the wafer periphery line on the template.
against the appropriate portions of the template.
In this case the image of the notch bottom must lie between
6. Apparatus
1
This test method is under the jurisdiction of ASTM Committee F-1 on 6.1 Optical Comparator, capable of 20 and 503 magnifi-
Electronics and is the direct responsibility of Subcommittee F01.06 on Silicon
cation with a viewing screen large enough to display an area 5
Materials and Process Control.
by5mmat203 or2by2mmat503.
Current edition approved Aug. 15, 1993. Published October 1993. Originally
6.2 Fixture, for holding the wafer to be tested. The fixture
published as F 1152 – 88. Last previous edition F 1152 – 88.
2
Annual Book of ASTM Standards, Vol 14.02.
must provide means for positioning the wafer such that the
3
Available from Standardization Documents Order Desk, Bldg. 4 Section D, 700
plane of the surface of the wafer is perpendicular to the
R
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