ASTM F1260M-96(2003)

Standard Test Method for Estimating Electromigration Median Time-to-Failure and Sigma of Integrated Circuit Metallizations [Metric] (Withdrawn 2009)

SCOPE
1.1 This test method is designed to characterize the failure distribution of interconnect metallizations such as are used in microelectronic circuits and devices that fail due to electromigration under specified d-c current density and temperature stress. This test method is intended to be used only when the failure distribution can be described by a log-Normal distribution.
1.2 This test method is intended for use as a referee method between laboratories and for comparing metallization alloys and metallizations prepared in different ways. It is not intended for qualifying vendors or for determining the use-life of a metallization.
1.3 The test method is an accelerated stress test of four-terminal structures (see Guide F 1259M) where the failure criterion is either an open circuit in the test line or a prescribed percent increase in the resistance of the test structure.
1.4 This test method allows the test structures of a test chip to be stressed while still part of the wafer (or a portion thereof) or while bonded to a package and electrically accessible by means of package terminals.
1.5 This test method is not designed to characterize the metallization for failure modes involving short circuits between adjacent metallization lines or between two levels of metallization.
1.6 This test method is not intended for the case where the stress test is terminated before all parts have failed.
1.7 This test method is primarily designed to analyze complete data. An option is provided for analyzing censored data (that is, when the stress test is halted before all parts under test have failed).
1.8 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.
WITHDRAWN RATIONALE
This test method is designed to characterize the failure distribution of interconnect metallizations such as are used in microelectronic circuits and devices that fail due to electromigration under specified d-c current density and temperature stress.
This guide is being withdrawn because the committee is not aware of the need to maintain the standard. Reference to the standard will remain available, but at this time, the committee does not wish to actively maintain the standard.
Formerly under the jursidiction of Committee F01 on Electronics and the direct responsibility of Subcommittee F01.11 on Nuclear and Space Radiation Effects, this test method was withdrawn in December 2009 with no replacement.

General Information

• Status: Withdrawn
• Publication Date: 09-Jun-1996
• Withdrawal Date: 30-Nov-2009
• Technical Committee: F01 - Electronics
• Drafting Committee: F01.11 - Nuclear and Space Radiation Effects

Relations

• Replaces: ASTM F1260M-96 - Standard Test Method for Estimating Electromigration Median Time-To-Failure and Sigma of Integrated Circuit Metallizations [Metric]
• Effective Date: 10-Jun-1996

Standards Content (Sample)

NOTICE: This standard has either been superseded and replaced by a new version or withdrawn.
Contact ASTM International (www.astm.org) for the latest information.
Designation: F1260M – 96 (Reapproved 2003)
Standard Test Method
for Estimating Electromigration Median Time-To-Failure and
Sigma of Integrated Circuit Metallizations (Metric)
This standard is issued under the fixed designation F1260M; the number immediately following the designation indicates the year of
original adoption or, in the case of revision, the year of last revision.Anumber in parentheses indicates the year of last reapproval.A
superscript epsilon (´) indicates an editorial change since the last revision or reapproval.
1. Scope 2. Referenced Documents
1.1 This test method is designed to characterize the failure 2.1 ASTM Standards:
distribution of interconnect metallizations such as are used in F1259M GuideforDesignofFlat,Straight-LineTestStruc-
microelectronic circuits and devices that fail due to electromi- tures for Detecting Metallization Open-Circuit or
gration under specified d-c current density and temperature Resistance-Increase Failure Due to Electromigration (Met-
stress. This test method is intended to be used only when the ric)
failure distribution can be described by a log-Normal distribu- F1261M Test Method for Determining theAverage Electri-
tion. cal Width of a Straight, Thin-Film Metal Line (Metric)
1.2 This test method is intended for use as a referee method 2.2 Other Standards:
between laboratories and for comparing metallization alloys EIA/JEDEC Standard33-A— Standard Method for Mea-
andmetallizationspreparedindifferentways.Itisnotintended suring and Using the Temperature Coefficient of Resis-
for qualifying vendors or for determining the use-life of a tance to Determine the Temperature of a Metallization
metallization. Line
1.3 The test method is an accelerated stress test of four- EIA/JEDEC Standard37— Lognormal Analysis of Uncen-
terminal structures (see Guide F1259M) where the failure sored Data, and of Singly Right-Censored Data Utilizing
criterioniseitheranopencircuitinthetestlineoraprescribed the Persson and Rootzen Method
percent increase in the resistance of the test structure.
3. Terminology
1.4 This test method allows the test structures of a test chip
3.1 Definitions of Terms Specific to This Standard:
tobestressedwhilestillpartofthewafer(oraportionthereof)
3.1.1 metallization—the thin-film metallic conductor used
or while bonded to a package and electrically accessible by
means of package terminals. as electrical interconnects in a microelectronic integrated
circuit.
1.5 This test method is not designed to characterize the
metallization for failure modes involving short circuits be- 3.1.2 test chip—an area on a wafer containing one or more
test structures that are stressed according to the test method
tween adjacent metallization lines or between two levels of
metallization. while either is still part of the wafer or after having been
separated and packaged.
1.6 This test method is not intended for the case where the
stress test is terminated before all parts have failed. 3.1.3 test line—a straight metallization line of designed
uniform width that is subjected to the current density and
1.7 This test method is primarily designed to analyze
complete data. An option is provided for analyzing censored temperature stresses prescribed in the test method.
3.1.4 test structure—a passive metallization structure, with
data(thatis,whenthestresstestishaltedbeforeallpartsunder
test have failed). terminals to permit electrical access, that is fabricated on a
semiconductor wafer by the normal procedures used to manu-
1.8 This standard does not purport to address all of the
safety concerns, if any, associated with its use. It is the facture microelectronic integrated devices.
responsibility of the user of this standard to establish appro-
priate safety and health practices and determine the applica-
bility of regulatory limitations prior to use.
For referenced ASTM standards, visit the ASTM website, www.astm.org, or
contact ASTM Customer Service at [e-mail]. For Annual Book of ASTM
This test method is under the jurisdiction of ASTM Committee F01 on Standards volume information, refer to the standard’s Document Summary page on
Electronics and is the direct responsibility of Subcommittee F01.11 on Nuclear and the ASTM website.
Space Radiation Effects. Withdrawn. The last approved version of this historical standard is referenced
Current edition approved June 10, 2003. Published June 2003. Originally on www.astm.org.
approved in 1989. Last previous edition approved in 1996 as F1260M–96. DOI: Available from Global Engineering Documents, 15 Inverness Way, East
10.1520/F1260M-96R03. Englewood, CO 80112-5704, http://www.global.ihs.com.
Copyright © ASTM International, 100 Barr Harbor Drive, PO Box C700, West Conshohocken, PA 19428-2959, United States.
F1260M – 96 (2003)
4. Summary of Test Method
J = mean current density stress,
E = activation energy (see 4.2),
4.1 This test method is used to obtain sample estimates of
k = Boltzmann constant, and
the median-time-to-failure, t , and sigma that describe the
T = mean stress temperature of the test lines stressed.
failure distribution of metallization test lines subjected to
For typical conditions, the induced percent error in t can
50s
current density and temperature stress. This involves subject-
be between two and three times the percent error in estimating
ing a sample of N test structures to high current density and
J, and can be between 15 and 20% if there is a 5°C error in
highambienttemperaturestress,calculatingthestresstempera-
estimating T for temperatures between 150 and 200°C.
ture of the metallization during the test, (which takes account
6.2 Structure-to-structure deviations from the stress means
of joule heating) and measuring the time to failure of each
produce changes in the time-to-fail, t, of the individual test
f
structure. The time-to-fail of the test structures is empirically
structures. These changes lead to increases in s and in the
describedbyalog-Normaldistribution.Thesampleestimateof
confidencelimitsfor t andsigma. Deviationsshouldbekept
t is equal to the exponential of the mean of the logarithm of
small enough that they do not produce changes in t by more
f
the time-to-fail values as follows:
than20%. Thisisespeciallyimportantwhensigma<0.4.The
t 5expln t
50S f
effect of stress deviations on t is calculated from (Eq 3) by
f
(1)
substituting t for t .
f 50s
The sample estimate of sigma, s, is equal to the standard
6.3 The effect of thermal interactions must be considered in
deviation of the logarithm of the time-to-fail values, scaled to
estimating the mean stress temperature of the structures under
remove the bias:
test when more than one test structure on a test chip is stressed
at a time and when joule heating is significant. These interac-
N 2
1 ( ln t 2ln t !
~
i 51 fi f
s 5 1 1 · (2)
F GΠtions are accounted for in 10.11. When the failure mode is a
4 N 21 N 21
~ !
prescribed increase in resistance, separate corrections may be
The failure times are plotted on a logarithm scale versus a
necessary if the currents to these structures have not been
Normal probability scale of cumulative percent failed to verify
reduced and increases in the resistances of the failed structures
that the points plotted fall along a straight line and thereby
duringtheremainderofthetestproducesignificantincreasesin
demonstrate that they belong to a well-behaved, log-Normal
the power dissipation on the test chip. See 10.9.4 to avoid the
distribution.
need for these corrections.
4.2 Before this test method can be implemented, a number
6.4 The selection of a percent change in resistance as the
of parameters must be selected and agreed upon between the
failure criterion (4.2, 10.9.2) is required for a multilayered
partiestothetest.Thesearetheambientstresstemperature;the
metallization that has one or more refractory metal layers.The
current-densitystress;thetemperature,T ,towhichthefailure-
n
value selected may affect significantly the measured activation
time data shall be normalized (6.10); the failure criterion (6.3, 5
energy, the value for n in (Eq 3), and t . The use of a large
50s
6.4,and10.9.2);thenumber,N,ofteststructurestobestressed;
percent increase in resistance ($30%) as the failure criterion
thedesignwidthofthetestlines(3.3)tobestressed(6.11);and 5
may lead to undesirably large variability in test results and to
theactivationenergy,E (6.10).BothNandsareusedin10.14
A
resistance oscillations due to open circuits in all but the
to determine the confidence limits for t and sigma.
refractory layer, especially when testing passivated metalliza-
tions.
5. Significance and Use
6.5 Some abnormalities in the test line and structure, other
5.1 Electromigration is a metallization failure mechanism
than those detectable from a visual inspection (7.2), may be
thatisofgreatconcernespeciallyforthereliabilityassessment
indicated by an abnormal value for R(TS) (10.3).
L
of very large-scale integrated (VLSI) microelectronic devices.
6.6 Thevoltagelimitimposedontheteststructure(8.1.4)is
5.2 This accelerated stress test is used to obtain sample
intended to reduce the possibility of the healing of an open
estimates of parameters that describe the failure distribution of
circuit at the moment of failure due to arcing.
themetallizationatthestressconditionsusedinthetest.These
6.7 It is possible, especially for passivated structures, that a
estimates are used in assessing metallization reliability and in
test line, having failed due to an open circuit, will resume
making major decisions for the selection of metallization and
conduction spontaneously later in the test or when the stress
processing technologies.
conditions are interrupted for a period. The current to these
structures shall be reduced as soon as practicable after their
6. Interferences
recovery has been detected.
6.1 Errors in estimating the mean current density and
6.8 Themetallizationtobetestedmustbesufficientlystable
temperature stresses will lead to errors in the sample estimate
so that when it is subjected to the stress temperature of the test
of t (t ) that can be calculated by the following empirical
50 50s
equation:
n
t 5A~1/J! exp~E /kT!
Ondrusek, J. C., Nishimura, A., Hoang, H. H., Sugiura, T., Blumenthal, R.,
50s a
(3) Kitagawa, H., and McPherson, J. W., “Effective Kinetic Variations with Stress
Duration for Multilayered Metallizations,” Proceedings International Reliability
Physics Symposium, 1988, p. 179.
where:
Maiz, J. A., and Sabi, B., “Electromigration Testing of Ti/Al-Si Metallization
A = constant,
for Integrated Circuits,” Proceedings International Reliability Physics Symposium,
n = constant,
1987, p. 145.
F1260M – 96 (2003)
(but not the stress current), no significant change will occur enough to the electromigration test structures to be stressed so
withtimeintheresistanceoftheindividualteststructuresorin that no significant change in line width over the wafer is
the failure characteristics (t and sigma) of the metallization expected.
due to electromigration. 7.4 Metallization Cross-Sectional Area—Calculate an aver-
age value for the cross-sectional area of the test lines to be
6.9 The test is applicable only for cases where t is large
enough so that the resistance of the test structure under power, stressedonatestchipbytakingtheproductofthemetallization
thickness obtained from 7.1 and the line width from 7.3.An
R(TS) ,(10.8.1 and 10.8.3) can be measured before significant
P
changesoccurintheresistanceorinthetemperaturecoefficient approximate estimate for the cross-sectional area of the test
line may be obtained by an electrical method that involves the
of resistance, TCR, (10.5) of the test structures under test due
to changes induced by electromigration. measurement of the resistance of a special, nearby test struc-
ture (see Test Method F1261M) at two temperatures when the
6.10 TheselectionofthenormalizationtemperatureT (4.2)
n
primary electrical conduction of the line is by means of an
can affect the accuracy of the sample estimate of t to the
aluminum alloy. Ignoring deviations from Matthiessen’s rule
extent that T is different from the mean of the metallization
n
and the effects of thermal expansion, an estimate of the
stress temperatures of the test structures under test (10.12) and
cross-sectional area, A, of the metal line can be obtained from
theestimateoftheactivationenergy(4.2and6.1)isinaccurate.
the following equation:
6.11 When comparing different metallizations of similar
thicknesses by their sample estimates of t , the test structures
L 30.01146·10
A 5 cm ! (4)
~
involved in the tests shall have test lines that have the same
dR/dT
designed width. Otherwise, the possible dependence of t on
where:
line width will interfere with such comparisons.
L = length of the line in the special test structure, and
dR/dT = slope of the resistance of the line with tempera-
7. Preparatory Measurements
ture.
7.1 Metallization Thickness—Obtain an estimate of the
Corrections have to be made to this estimate when making
metallization thickness from measurements made at five loca-
measurements of layered metallizations where the other layers
tions distributed over each wafer that is to provide test
are of materials with much higher electrical resistivity.
structuresforthetestmethod.Thismaybedoneafterthemetal
deposition step with an appropriate contactless method or later
8. Test Circuit
onthewaferwithaprofilometer,forexample.Inthelattercase,
8.1 The test circuit used shall have the following capabili-
account for any consumption of the underlying dielectric or of
ties:
the exposed metallization that may have occurred after the
8.1.1 The current through each test structure shall be indi-
metallization deposition. Caution is also advised if a profilo-
viduallyadjustabletothecurrentnecessarytoattainthedesired
meterisusedonpassivatedmetallization;thedepositionrateof
current density stress and be maintained constant during the
the dielectric on the metallization may be different from the
stress test to within 61% of that current or 25 µA, whichever
rate on other materials.
is greater (see 6.1 and 6.2).
7.2 MicroscopicInspection—Performamicroscopicinspec-
8.1.2 The display resolution of the voltage if used to
tion of the test structures to be stressed. Reject structures
determine the current through a test structure shall be equiva-
intended for the test which have test lines that are discontinu-
lentto0.1%oftheintendedstresscurrentor10µV,whichever
ous or have other abnormal physical features that can be
is greater (see section 6.1.).
observed. If structures are packaged, ensure that any package
8.1.3 The display resolution of the voltage between the
wir
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