F01.11 - Nuclear and Space Radiation Effects

SIGNIFICANCE AND USE
5.1 Electronic circuits used in space, military, and nuclear power systems may be exposed to various levels of ionizing radiation. It is essential for the design and fabrication of such circuits that test methods be available that can determine the vulnerability or hardness (measure of nonvulnerability) of components to be used in such systems.  
5.2 Some manufacturers currently are selling semiconductor parts with guaranteed hardness ratings. Use of this guide provides a basis for standardized qualification and acceptance testing.
SCOPE
1.1 This guide presents background and guidelines for establishing an appropriate sequence of tests and data analysis procedures for determining the ionizing radiation (total dose) hardness of microelectronic devices for dose rates below 300 rd(SiO2)/s. These tests and analysis will be appropriate to assist in the determination of the ability of the devices under test to meet specific hardness requirements or to evaluate the parts for use in a range of radiation environments.  
1.2 The methods and guidelines presented will be applicable to characterization, qualification, and lot acceptance of silicon-based MOS and bipolar discrete devices and integrated circuits. They will be appropriate for treatment of the effects of electron and photon irradiation.  
1.3 This guide provides a framework for choosing a test sequence based on general characteristics of the parts to be tested and the radiation hardness requirements or goals for these parts.  
1.4 This guide provides for tradeoffs between minimizing the conservative nature of the testing method and minimizing the required testing effort.  
1.5 Determination of an effective and economical hardness test typically will require several kinds of decisions. A partial enumeration of the decisions that typically must be made is as follows:  
1.5.1 Determination of the Need to Perform Device Characterization—For some cases it may be more appropriate to adopt some kind of worst case testing scheme that does not require device characterization. For other cases it may be most effective to determine the effect of dose-rate on the radiation sensitivity of a device. As necessary, the appropriate level of detail of such a characterization also must be determined.  
1.5.2 Determination of an Effective Strategy for Minimizing the Effects of Irradiation Dose Rate on the Test Result—The results of radiation testing on some types of devices are relatively insensitive to the dose rate of the radiation applied in the test. In contrast, many MOS devices and some bipolar devices have a significant sensitivity to dose rate. Several different strategies for managing the dose rate sensitivity of test results will be discussed.  
1.5.3 Choice of an Effective Test Methodology—The selection of effective test methodologies will be discussed.  
1.6 Low Dose Requirements—Hardness testing of MOS and bipolar microelectronic devices for the purpose of qualification or lot acceptance is not necessary when the required hardness is 100 rd(SiO2) or lower.  
1.7 Sources—This guide will cover effects due to device testing using irradiation from photon sources, such as 60Co γ irradiators,  137Cs γ irradiators, and low energy (approximately 10 keV) X-ray sources. Other sources of test radiation such as linacs, Van de Graaff sources, Dymnamitrons, SEMs, and flash X-ray sources occasionally are used but are outside the scope of this guide.
1.8 Displacement damage effects are outside the scope of this guide, as well.  
1.9 The values stated in SI units are to be regarded as the standard.

SIGNIFICANCE AND USE
Semiconductor devices can be permanently damaged by reactor spectrum neutrons (1, 2) . The effect of such damage on the performance of an electronic component can be determined by measuring the component’s electrical characteristics before and after exposure to fast neutrons in the neutron fluence range of interest. The resulting data can be utilized in the design of electronic circuits that are tolerant of the degradation exhibited by that component.
This guide provides a method by which the exposure of silicon and gallium arsenide semiconductor devices to neutron irradiation may be performed in a manner that is repeatable and which will allow comparison to be made of data taken at different facilities.
For semiconductors other than silicon and gallium arsenide, applicable validated 1-MeV damage functions are not available in codified National standards. In the absence of a validated 1-MeV damage function, the non-ionizing energy loss (NIEL) or the displacement kerma, as a function incident neutron energy, normalized to the response in the 1 MeV energy region, may be used as an approximation. See Practice E722 for a description of the method used to determine the damage functions in Si and GaAs (3).
SCOPE
1.1 This guide strictly applies only to the exposure of unbiased silicon (Si) or gallium arsenide (GaAs) semiconductor components (integrated circuits, transistors, and diodes) to neutron radiation from a nuclear reactor source to determine the permanent damage in the components. Validated 1-MeV displacement damage functions codified in National Standards are not currently available for other semiconductor materials.
1.2 Elements of this guide, with the deviations noted, may also be applicable to the exposure of semiconductors comprised of other materials except that validated 1-MeV displacement damage functions codified in National standards are not currently available.
1.3 Only the conditions of exposure are addressed in this guide. The effects of radiation on the test sample should be determined using appropriate electrical test methods.
1.4 This guide addresses those issues and concerns pertaining to irradiations with reactor spectrum neutrons.
1.5 System and subsystem exposures and test methods are not included in this guide.
1.6 This guide is applicable to irradiations conducted with the reactor operating in either the pulsed or steady-state mode. The range of interest for neutron fluence in displacement damage semiconductor testing range from approximately 109 to 1016 1-MeV n/cm2.
1.7 This guide does not address neutron-induced single or multiple neutron event effects or transient annealing.
1.8 This guide provides an alternative to Test Method 1017.3, Neutron Displacement Testing, a component of MIL-STD-883 and MIL-STD-750. The Department of Defense has restricted use of these MIL-STDs to programs existing in 1995 and earlier.
1.9 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SIGNIFICANCE AND USE
Electronic circuits used in many space, military and nuclear power systems may be exposed to various levels of ionizing radiation dose. It is essential for the design and fabrication of such circuits that test methods be available that can determine the vulnerability or hardness (measure of nonvulnerability) of components to be used in such systems.
Manufacturers are currently selling semiconductor parts with guaranteed hardness ratings, and the military specification system is being expanded to cover hardness specification for parts. Therefore test methods and guides are required to standardize qualification testing.  
Use of low energy (≈10 keV) X-ray sources has been examined as an alternative to cobalt-60 for the ionizing radiation effects testing of microelectronic devices (3, 4, 5, 6). The goal of this guide is to provide background information and guidance for such use where appropriate.
Note 3—Cobalt-60The most commonly used source of ionizing radiation for ionizing radiation (“total dose”) testing is cobalt-60. Gamma rays with energies of 1.17 and 1.33 MeV are the primary ionizing radiation emitted by cobalt-60. In exposures using cobalt-60 sources, test specimens must be enclosed in a lead-aluminum container to minimize dose-enhancement effects caused by low-energy scattered radiation (unless it has been demonstrated that these effects are negligible). For this lead-aluminum container, a minimum of 1.5 mm of lead surrounding an inner shield of 0.7 to 1.0 mm of aluminum is required. (See 8.2.2.2 and Practice E1249.)
The X-ray tester has proven to be a useful ionizing radiation effects testing tool because:
It offers a relatively high dose rate, in comparison to most cobalt-60 sources, thus offering reduced testing time.
The radiation is of sufficiently low energy that it can be readily collimated. As a result, it is possible to irradiate a single device on a wafer.
Radiation safety issues are more easily managed with an X-ray irradiator than w...
SCOPE
Electronic circuits used in many space, military and nuclear power systems may be exposed to various levels of ionizing radiation dose. It is essential for the design and fabrication of such circuits that test methods be available that can determine the vulnerability or hardness (measure of nonvulnerability) of components to be used in such systems.
Manufacturers are currently selling semiconductor parts with guaranteed hardness ratings, and the military specification system is being expanded to cover hardness specification for parts. Therefore test methods and guides are required to standardize qualification testing.  
Use of low energy (≈10 keV) X-ray sources has been examined as an alternative to cobalt-60 for the ionizing radiation effects testing of microelectronic devices (3, 4, 5, 6). The goal of this guide is to provide background information and guidance for such use where appropriate.
Note 3—Cobalt-60The most commonly used source of ionizing radiation for ionizing radiation (“total dose”) testing is cobalt-60. Gamma rays with energies of 1.17 and 1.33 MeV are the primary ionizing radiation emitted by cobalt-60. In exposures using cobalt-60 sources, test specimens must be enclosed in a lead-aluminum container to minimize dose-enhancement effects caused by low-energy scattered radiation (unless it has been demonstrated that these effects are negligible). For this lead-aluminum container, a minimum of 1.5 mm of lead surrounding an inner shield of 0.7 to 1.0 mm of aluminum is required. (See 8.2.2.2 and Practice E1249.)
The X-ray tester has proven to be a useful ionizing radiation effects testing tool because:
It offers a relatively high dose rate, in comparison to most cobalt-60 sources, thus offering reduced testing time.
The radiation is of sufficiently low energy that it can be readily collimated. As a result, it is possible to irradiate a single device on a wafer.
Radiation safety issues are more ...

SIGNIFICANCE AND USE
Many modern integrated circuits, power transistors, and other devices experience SEP when exposed to cosmic rays in interplanetary space, in satellite orbits or during a short passage through trapped radiation belts. It is essential to be able to predict the SEP rate for a specific environment in order to establish proper techniques to counter the effects of such upsets in proposed systems. As the technology moves toward higher density ICs, the problem is likely to become even more acute.
This guide is intended to assist experimenters in performing ground tests to yield data enabling SEP predictions to be made.
SCOPE
1.1 This guide defines the requirements and procedures for testing integrated circuits and other devices for the effects of single event phenomena (SEP) induced by irradiation with heavy ions having an atomic number Z ≥ 2. This description specifically excludes the effects of neutrons, protons, and other lighter particles that may induce SEP via another mechanism. SEP includes any manifestation of upset induced by a single ion strike, including soft errors (one or more simultaneous reversible bit flips), hard errors (irreversible bit flips), latchup (persistent high conducting state), transients induced in combinatorial devices which may introduce a soft error in nearby circuits, power field effect transistor (FET) burn-out and gate rupture. This test may be considered to be destructive because it often involves the removal of device lids prior to irradiation. Bit flips are usually associated with digital devices and latchup is usually confined to bulk complementary metal oxide semiconductor, (CMOS) devices, but heavy ion induced SEP is also observed in combinatorial logic programmable read only memory, (PROMs), and certain linear devices that may respond to a heavy ion induced charge transient. Power transistors may be tested by the procedure called out in Method 1080 of MIL STD 750.
1.2 The procedures described here can be used to simulate and predict SEP arising from the natural space environment, including galactic cosmic rays, planetary trapped ions, and solar flares. The techniques do not, however, simulate heavy ion beam effects proposed for military programs. The end product of the test is a plot of the SEP cross section (the number of upsets per unit fluence) as a function of ion LET (linear energy transfer or ionization deposited along the ion's path through the semiconductor). This data can be combined with the system's heavy ion environment to estimate a system upset rate.
1.3 Although protons can cause SEP, they are not included in this guide. A separate guide addressing proton induced SEP is being considered.
1.4 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SIGNIFICANCE AND USE
Overtesting should be done when (a) testing by variables is impractical because of time and cost considerations or because the probability distribution of stress to failure cannot be estimated with sufficient accuracy, and (b) an unrealistically large number of parts would have to be tested at the specification stress for the necessary confidence and survival probability.
SCOPE
1.1 This guide covers the use of overtesting in order to reduce the required number of parts that must be tested to meet a given quality acceptance standard. Overtesting is testing a sample number of parts at a stress level higher than their specification stress in order to reduce the amount of necessary data taking. This guide discusses when and how overtesting may be applied to forming probabilistic estimates for the survival of electronic piece parts subjected to radiation stress. Some knowledge of the probability distribution governing the stress-to-failure of the parts is necessary, although exact knowledge may be replaced by over-conservative estimates of this distribution.

SIGNIFICANCE AND USE
PN Junction Diode—The steady-state photocurrent of a simple p-n junction diode is a directly measurable quantity that can be directly related to device response over a wide range of ionizing radiation. For more complex devices the junction photocurrent may not be directly related to device response.
Zener Diode— In this device, the effect of the photocurrent on the Zener voltage rather than the photocurrent itself is usually most important. The device is most appropriately tested while biased in the Zener region. In testing Zener diodes or precision voltage regulators, extra precaution must be taken to make certain the photocurrent generated in the device during irradiations does not cause the voltage across the device to change during the test.
Bipolar Transistor—As device geometries dictate that photocurrent from the base-collector junction be much greater than current from the base-emitter junction, measurements are usually made only on the collector-base junction with emitter open; however, sometimes, to obtain data for computer-aided circuit analysis, the emitter-base junction photocurrent is also measured.
Junction Field-Effect Device—A proper photocurrent measurement requires that the source be shorted (dc) to the drain during measurement of the gate-channel photocurrent. In tetrode-connected devices, the two gate-channel junctions should be monitored separately.
Insulated Gate Field-Effect Device—In this type of device, the true photocurrent is between the substrate and the channel, source, and drain regions. A current which can generate voltage that will turn on the device may be measured by the technique used here, but it is due to induced conductivity in the gate insulator and thus is not a junction photocurrent.
SCOPE
1.1 This test method covers the measurement of steady-state primary photocurrent, Ipp, generated in semiconductor devices when these devices are exposed to ionizing radiation. These procedures are intended for the measurement of photocurrents greater than 10−9 A·s/Gy(Si or Ge), in cases for which the relaxation time of the device being measured is less than 25 % of the pulse width of the ionizing source. The validity of these procedures for ionizing dose rates as great as 108Gy(Si or Ge)/s has been established. The procedures may be used for measurements at dose rates as great as 1010Gy(Si or Ge)/s; however, extra care must be taken. Above 108Gy/s, the package response may dominate the device response for any device. Additional precautions are also required when measuring photocurrents of 10−9 A·s/Gy(Si or Ge) or lower.
1.2 Setup, calibration, and test circuit evaluation procedures are also included in this test method.
1.3 Because of the variability between device types and in the requirements of different applications, the dose rate range over which any specific test is to be conducted is not given in this test method but must be specified separately.
1.4 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SIGNIFICANCE AND USE
The electrical properties of gate and field oxides are altered by ionizing radiation. The method for determining the dose delivered by the source irradiation is discussed in Practices E666, E668, E1249, and Guide E1894. The time dependent and dose rate effects of the ionizing radiation can be determined by comparing pre- and post-irradiation voltage shifts, ΔVot and ΔVit. This test method provides a means for evaluation of the ionizing radiation response of MOSFETs and isolation parasitic MOSFETs.
The measured voltage shifts, ΔVot and ΔVit, can provide a measure of the effectiveness of processing variations on the ionizing radiation response.
This technique can be used to monitor the total-dose response of a process technology.
SCOPE
1.1 This test method covers the use of the subthreshold charge separation technique for analysis of ionizing radiation degradation of a gate dielectric in a metal-oxide-semiconductor-field-effect transistor (MOSFET) and an isolation dielectric in a parasitic MOSFET. , , The subthreshold technique is used to separate the ionizing radiation-induced inversion voltage shift, ΔVINV into voltage shifts due to oxide trapped charge, ΔVot and interface traps, ΔVit. This technique uses the pre- and post-irradiation drain to source current versus gate voltage characteristics in the MOSFET subthreshold region.
1.2 Procedures are given for measuring the MOSFET subthreshold current-voltage characteristics and for the calculation of results.
1.3 The application of this test method requires the MOSFET to have a substrate (body) contact.  
1.4 Both pre- and post-irradiation MOSFET subthreshold source or drain curves must follow an exponential dependence on gate voltage for a minimum of two decades of current.
1.5 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard.
1.6 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SIGNIFICANCE AND USE
The use of FXR or LINAC radiation sources for the determination of high dose-rate burnout in semiconductor devices is addressed in this guide. The goal of this guide is to provide a systematic approach to testing semiconductor devices for burnout or survivability.
The different types of failure modes that are possible are defined and discussed in this guide. Specifically, failure can be defined by a change in device parameters, or by a catastrophic failure of the device.
This guide can be used to determine if a device survives (that is, continues to operate and function within the specified performance parameters) when irradiated to a predetermined dose-rate level; or, the guide can be used to determine the dose-rate burnout failure level (that is, the minimum dose rate at which burnout failure occurs). However, since this latter test is destructive, the minimum dose-rate burnout failure level must be determined statistically.
SCOPE
1.1 This guide defines the detailed requirements for testing semiconductor devices for short-pulse high dose-rate ionization-induced survivability and burnout failure. The test facility shall be capable of providing the necessary dose rates to perform the measurements. Typically, large flash X-ray (FXR) machines operated in the photon mode, or FXR e-beam facilities are utilized because of their high dose-rate capabilities. Electron Linear Accelerators (LINACs) may be used if the dose rate is sufficient. Two modes of test are described: (1) A survivability test, and (2) A burnout failure level test.
1.2 The values stated in International System of Units (SI) are to be regarded as standard. No other units of measurement are included in this standard.

SIGNIFICANCE AND USE
5.1 Electronic circuits used in many space, military, and nuclear power systems may be exposed to various levels and time profiles of neutron radiation. It is essential for the design and fabrication of such circuits that test methods be available that can determine the vulnerability or hardness (measure of nonvulnerability) of components to be used in them. A determination of hardness is often necessary for the short term (≈100 μs) as well as long term (permanent damage) following exposure. See Practice E722.
SCOPE
1.1 This guide defines the requirements and procedures for testing silicon discrete semiconductor devices and integrated circuits for rapid-annealing effects from displacement damage resulting from neutron radiation. This test will produce degradation of the electrical properties of the irradiated devices and should be considered a destructive test. Rapid annealing of displacement damage is usually associated with bipolar technologies.  
1.1.1 Heavy ion beams can also be used to characterize displacement damage annealing (1)2, but ion beams have significant complications in the interpretation of the resulting device behavior due to the associated ionizing dose. The use of pulsed ion beams as a source of displacement damage is not within the scope of this standard.  
1.2 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard.  
1.3 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to consult and establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SIGNIFICANCE AND USE
Digital integrated circuits are specified to operate with their inputs and outputs in either a logical 1 or a logical 0 state. The occurrence of signals having voltage levels not meeting the specifications of either of these levels (an upset condition) may cause the generation and propagation of erroneous data in a digital system.
Knowledge of the radiation dose rate that causes upset in digital integrated circuits is essential for the design, production, and maintenance of electronic systems that are required to operate in the presence of pulsed radiation environments.
SCOPE
1.1 This test method covers the measurement of the threshold level of radiation dose rate that causes upset in digital integrated circuits under static operating conditions. The radiation source is either a flash X-ray machine (FXR) or an electron linear accelerator (LINAC).
1.2 The precision of the measurement depends on the homogeneity of the radiation field and on the precision of the radiation dosimetry and the recording instrumentation.
1.3 The test may be destructive either for further tests or for purposes other than this test if the integrated circuit being tested absorbs a total radiation dose exceeding some predetermined level. Because this level depends both on the kind of integrated circuit and on the application, a specific value must be agreed upon by the parties to the test (6.8).
1.4 Setup, calibration, and test circuit evaluation procedures are included in this test method.
1.5 Procedures for lot qualification and sampling are not included in this test method.
1.6 Because of the variability of the response of different device types, the initial dose rate for any specific test is not given in this test method but must be agreed upon by the parties to the test.
1.7 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard.
1.8 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SIGNIFICANCE AND USE
There are many kinds of linear integrated circuits. Any given linear integrated circuit may be used in a variety of ways and under various operating conditions within the limits of performance specified by the manufacturer. The procedures of this practice provide a standardized way to measure the dose-rate response of a linear integrated circuit, under operating conditions similar to those of the intended application, when the circuit is exposed to pulsed ionizing radiation.
Knowledge of the responses of linear integrated circuits to radiation pulses is essential for the design, production, and maintenance of electronic systems that are required to operate in the presence of pulsed radiation environments.
SCOPE
1.1 This practice covers the measurement of the response of linear integrated circuits, under given operating conditions, to pulsed ionizing radiation. The response may be either transient or more lasting, such as latchup. The radiation source is either a flash X-ray machine (FXR) or an electron linear accelerator (LINAC).  
1.2 The precision of the measurement depends on the homogeneity of the radiation field and on the precision of the radiation dosimetry and the recording instrumentation.
1.3 The test may be considered to be destructive either for further tests or for other purposes if the total radiation ionizing dose exceeds some predetermined level or if the part should latch up. Because this level depends both on the kind of integrated circuit and on the application, a specific value must be agreed upon by the parties to the test. (See 6.10.)
1.4 Setup, calibration, and test circuit evaluation procedures are included in this practice.
1.5 Procedures for lot qualification and sampling are not included in this practice.
1.6 Because response varies with different device types, the dose rate range for any specific test is not given in this practice but must be agreed upon by the parties to the test.
1.7 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard.
1.8 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SIGNIFICANCE AND USE
The electrical properties of gate and field oxides are altered by ionizing radiation. The method for determining the dose delivered by the source irradiation is discussed in Practices E666, E668, E1249, and Guide E1894. The time dependent and dose rate effects of the ionizing radiation can be determined by comparing pre- and post-irradiation voltage shifts, ΔVot and ΔVit. This test method provides a means for evaluation of the ionizing radiation response of MOSFETs and isolation parasitic MOSFETs.
The measured voltage shifts, ΔVot and ΔVit, can provide a measure of the effectiveness of processing variations on the ionizing radiation response.
This technique can be used to monitor the total-dose response of a process technology.
SCOPE
1.1 This test method covers the use of the subthreshold charge separation technique for analysis of ionizing radiation degradation of a gate dielectric in a metal-oxide-semiconductor-field-effect transistor (MOSFET) and an isolation dielectric in a parasitic MOSFET. , , The subthreshold technique is used to separate the ionizing radiation-induced inversion voltage shift, ΔVINV into voltage shifts due to oxide trapped charge, ΔVot and interface traps, ΔVit. This technique uses the pre- and post-irradiation drain to source current versus gate voltage characteristics in the MOSFET subthreshold region.
1.2 Procedures are given for measuring the MOSFET subthreshold current-voltage characteristics and for the calculation of results.
1.3 The application of this test method requires the MOSFET to have a substrate (body) contact.  
1.4 Both pre- and post-irradiation MOSFET subthreshold source or drain curves must follow an exponential dependence on gate voltage for a minimum of two decades of current.
1.5 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard.
1.6 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SIGNIFICANCE AND USE
Solid-state electronic devices subjected to stresses from excessive current pulses sometimes fail because a portion of the metallization fuses or vaporizes (suffers burnout). Burnout susceptibility can vary significantly from component to component on a given wafer, regardless of design. This practice provides a procedure for establishing the limits of pulse current overstress within which the metallization of a given device should survive.
This practice can be used as a destructive test in a lot-sampling program to determine the boundaries of the safe operating region having desired survival probabilities and statistical confidence levels when appropriate sample quantities and statistical analyses are used.
Note 2—The practice may be extended to infer the survivability of untested metallization adjacent to the specimen metallization on a semiconductor die or wafer if care is taken that appropriate similarities exist in the design and fabrication variables.
SCOPE
1.1 This practice covers procedures for determining operating regions that are safe from metallization burnout induced by current pulses of less than 1-s duration.
Note 1—In this practice, “metallization” refers to metallic layers on semiconductor components such as interconnect patterns on integrated circuits. The principles of the practice may, however, be extended to nearly any current-carrying path. The term “burnout” refers to either fusing or vaporization.  
1.2 This practice is based on the application of unipolar rectangular current test pulses. An extrapolation technique is specified for mapping safe operating regions in the pulse-amplitude versus pulse-duration plane. A procedure is provided in Appendix X2 to relate safe operating regions established from rectangular pulse data to safe operating regions for arbitrary pulse shapes.
1.3 This practice is not intended to apply to metallization damage mechanisms other than fusing or vaporization induced by current pulses and, in particular, is not intended to apply to long-term mechanisms, such as metal migration.
1.4 This practice is not intended to determine the nature of any defect causing failure.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SIGNIFICANCE AND USE
Digital logic circuits are used in system applications where they are exposed to pulses of radiation. It is important to know the minimum radiation level at which transient failures can be induced, since this affects system operation.
SCOPE
1.1 This guide is to assist experimenters in measuring the transient radiation upset threshold of silicon digital integrated circuits exposed to pulses of ionizing radiation greater than 103 Gy (Si)/s.
1.2 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SIGNIFICANCE AND USE
Many modern integrated circuits, power transistors, and other devices experience SEP when exposed to cosmic rays in interplanetary space, in satellite orbits or during a short passage through trapped radiation belts. It is essential to be able to predict the SEP rate for a specific environment in order to establish proper techniques to counter the effects of such upsets in proposed systems. As the technology moves toward higher density ICs, the problem is likely to become even more acute.
This guide is intended to assist experimenters in performing ground tests to yield data enabling SEP predictions to be made.
SCOPE
1.1 This guide defines the requirements and procedures for testing integrated circuits and other devices for the effects of single event phenomena (SEP) induced by irradiation with heavy ions having an atomic number Z  2. This description specifically excludes the effects of neutrons, protons, and other lighter particles that may induce SEP via another mechanism. SEP includes any manifestation of upset induced by a single ion strike, including soft errors (one or more simultaneous reversible bit flips), hard errors (irreversible bit flips), latchup (permanent high conducting state), transients induced in combinatorial devices which may introduce a soft error in nearby circuits, power field effect transistor (FET) burn-out and gate rupture. This test may be considered to be destructive because it often involves the removal of device lids prior to irradiation. Bit flips are usually associated with digital devices and latchup is usually confined to bulk complementary metal oxide semiconductor, (CMOS) devices, but heavy ion induced SEP is also observed in combinatorial logic programmable read only memory, (PROMs), and certain linear devices that may respond to a heavy ion induced charge transient. Power transitors may be tested by the procedure called out in Method 1080 of MIL STD 750.
1.2 The procedures described here can be used to simulate and predict SEP arising from the natural space environment, including galactic cosmic rays, planetary trapped ions and solar flares. The techniques do not, however, simulate heavy ion beam effects proposed for military programs. The end product of the test is a plot of the SEP cross section (the number of upsets per unit fluence) as a function of ion LET (linear energy transfer, or ionization deposited along the ion's path through the semiconductor). This data can be combined with the system's heavy ion environment to estimate a system upset rate.
1.3 Although protons can cause SEP, they are not included in this guide. A separate guide addressing proton induced SEP is being considered.
1.4 The values stated in International System of Units (SI) are to be regarded as standard. No other units of measurement are included in this guide.
This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SIGNIFICANCE AND USE
Electronic circuits used in space, military, and nuclear power systems may be exposed to various levels of ionizing radiation. It is essential for the design and fabrication of such circuits that test methods be available that can determine the vulnerability or hardness (measure of nonvulnerability) of components to be used in such systems.
Some manufacturers currently are selling semiconductor parts with guaranteed hardness ratings. Use of this guide provides a basis for standardized qualification and acceptance testing.
SCOPE
1.1 This guide presents background and guidelines for establishing an appropriate sequence of tests and data analysis procedures for determining the ionizing radiation (total dose) hardness of microelectronic devices for dose rates below 300 rd(SiO2)/s. These tests and analysis will be appropriate to assist in the determination of the ability of the devices under test to meet specific hardness requirements or to evaluate the parts for use in a range of radiation environments.
1.2 The methods and guidelines presented will be applicable to characterization, qualification, and lot acceptance of silicon-based MOS and bipolar discrete devices and integrated circuits. They will be appropriate for treatment of the effects of electron and photon irradiation.
1.3 This guide provides a framework for choosing a test sequence based on general characteristics of the parts to be tested and the radiation hardness requirements or goals for these parts.
1.4 This guide provides for tradeoffs between minimizing the conservative nature of the testing method and minimizing the required testing effort.
1.5 Determination of an effective and economical hardness test typically will require several kinds of decisions. A partial enumeration of the decisions that typically must be made is as follows:
1.5.1 Determination of the Need to Perform Device CharacterizationFor some cases it may be more appropriate to adopt some kind of worst case testing scheme that does not require device characterization. For other cases it may be most effective to determine the effect of dose-rate on the radiation sensitivity of a device. As necessary, the appropriate level of detail of such a characterization also must be determined.
1.5.2 Determination of an Effective Strategy for Minimizing the Effects of Irradiation Dose Rate on the Test ResultThe results of radiation testing on some types of devices are relatively insensitive to the dose rate of the radiation applied in the test. In contrast, many MOS devices and some bipolar devices have a significant sensitivity to dose rate. Several different strategies for managing the dose rate sensitivity of test results will be discussed.
1.5.3 Choice of an Effective Test MethodologyThe selection of effective test methodologies will be discussed.
1.6 Low Dose RequirementsHardness testing of MOS and bipolar microelectronic devices for the purpose of qualification or lot acceptance is not necessary when the required hardness is 100 rd(SiO2) or lower.
1.7 SourcesThis guide will cover effects due to device testing using irradiation from photon sources, such as 60Co irradiators,  137Cs irradiators, and low energy (approximately 10 keV) X-ray sources. Other sources of test radiation such as linacs, Van de Graaff sources, Dymnamitrons, SEMs, and flash X-ray sources occasionally are used but are outside the scope of this guide.
1.8 Displacement damage effects are outside the scope of this guide, as well.
1.9 The values stated in SI units are to be regarded as the standard.

SIGNIFICANCE AND USE
Semiconductor devices are permanently damaged by reactor spectrum neutrons. The effect of such damage on the performance of an electronic component can be determined by measuring the component electrical characteristics before and after exposure to fast neutrons in the neutron fluence range of interest. The resulting data can be utilized in the design of electronic circuits that are tolerant of the degradation exhibited by that component.
This guide provides a method by which the exposure of silicon and gallium arsenide semiconductor devices to neutron irradiation may be performed in a manner that is repeatable and which will allow comparison to be made of data taken at different facilities.
For semiconductors other than silicon and gallium arsenide, this guide provides a method that can improve consistency in the measurements and assurance that data from various facilities can be compared on the same equivalence fluence scale when the applicable validated 1-MeV damage functions are codified in National standards. In the absence of a validated 1-MeV damage function, the non-ionizing energy loss (NIEL) as a function incident neutron energy, normalized to the NIEL at 1 MeV, may be used as an approximation. See Practice E 722 for a description of the method.
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1.1 This guide strictly applies only to the exposure of unbiased silicon (SI) or gallium arsenide (GaAs) semiconductor components (integrated circuits, transistors, and diodes) to neutron radiation from a nuclear reactor source to determine the permanent damage in the components. Validated 1-MeV damage functions codified in National Standards are not currently available for other semiconductor materials.
1.2 Elements of this guide with the deviations noted may also be applicable to the exposure of semiconductors comprised of other materials except that validated 1-MeV damage functions codified in National standards are not currently available.
1.3 Only the conditions of exposure are addressed in this guide. The effects of radiation on the test sample should be determined using appropriate electrical test methods.
1.4 This guide addresses those issues and concerns pertaining to irradiations with reactor spectrum neutrons.
1.5 System and subsystem exposures and test methods are not included in this guide.
1.6 This guide is applicable to irradiations conducted with the reactor operating in either the pulsed or steady-state mode. The range of interest for neutron fluence in displacement damage semiconductor testing range from approximately 109  to 1016  n/cm 2.
1.7 This guide does not address neutron-induced single or multiple neutron event effects or transient annealing.
1.8 This guide provides an alternative to Test Method 1017.3, Neutron Displacement Testing, a component of MIL-STD-883 and MIL-STD-750. The Department of Defense has restricted use of these MIL-STDs to programs existing in 1995 and earlier.
This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SIGNIFICANCE AND USE
Electronic circuits used in many space, military and nuclear power systems may be exposed to various levels of ionizing radiation dose. It is essential for the design and fabrication of such circuits that test methods be available that can determine the vulnerability or hardness (measure of nonvulnerability) of components to be used in such systems.
Manufacturers are currently selling semiconductor parts with guaranteed hardness ratings, and the military specification system is being expanded to cover hardness specification for parts. Therefore test methods and guides are required to standardize qualification testing.  
Use of low energy (≈10 keV) X-ray sources has been examined as an alternative to cobalt-60 for the ionizing radiation effects testing of microelectronic devices (3, 4, 5, 6). The goal of this guide is to provide background information and guidance for such use where appropriate.
Note 3—Cobalt-60The most commonly used source of ionizing radiation for ionizing radiation (“total dose”) testing is cobalt-60. Gamma rays with energies of 1.17 and 1.33 MeV are the primary ionizing radiation emitted by cobalt-60. In exposures using cobalt-60 sources, test specimens must be enclosed in a lead-aluminum container to minimize dose-enhancement effects caused by low-energy scattered radiation (unless it has been demonstrated that these effects are negligible). For this lead-aluminum container, a minimum of 1.5 mm of lead surrounding an inner shield of 0.7 to 1.0 mm of aluminum is required. (See 8.2.2.2 and Practice E1249.)
The X-ray tester has proven to be a useful ionizing radiation effects testing tool because:
It offers a relatively high dose rate, in comparison to most cobalt-60 sources, thus offering reduced testing time.
The radiation is of sufficiently low energy that it can be readily collimated. As a result, it is possible to irradiate a single device on a wafer.
Radiation safety issues are more easily managed with an X-ray irradiator than w...
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1.1 This guide covers recommended procedures for the use of X-ray testers (that is, sources with a photon spectrum having ≈10 keV mean photon energy and ≈50 keV maximum energy) in testing semiconductor discrete devices and integrated circuits for effects from ionizing radiation.  
1.2 The X-ray tester may be appropriate for investigating the susceptibility of wafer level or delidded microelectronic devices to ionizing radiation effects. It is not appropriate for investigating other radiation-induced effects such as single-event effects (SEE) or effects due to displacement damage.
1.3 This guide focuses on radiation effects in metal oxide silicon (MOS) circuit elements, either designed (as in MOS transistors) or parasitic (as in parasitic MOS elements in bipolar transistors).
1.4 Information is given about appropriate comparison of ionizing radiation hardness results obtained with an X-ray tester to those results obtained with cobalt-60 gamma irradiation. Several differences in radiation-induced effects caused by differences in the photon energies of the X-ray and cobalt-60 gamma sources are evaluated. Quantitative estimates of the magnitude of these differences in effects, and other factors that should be considered in setting up test protocols, are presented.
1.5 If a 10-keV X-ray tester is to be used for qualification testing or lot acceptance testing, it is recommended that such tests be supported by cross checking with cobalt-60 gamma irradiations.
1.6 Comparisons of ionizing radiation hardness results obtained with an X-ray tester with results obtained with a linac, with protons, etc. are outside the scope of this guide.
1.7 Current understanding of the differences between the physical effects caused by X-ray and cobalt-60 gamma irradiations is used to provide an estimate of the ratio (number-of-holes-cobalt-60)/(number-of-holes-X-ray). Several cases are defined where the differences in the effects caused...

SCOPE
1.1 This guide covers recommended procedures for the use of X-ray testers (that is, sources with a photon spectrum having [approximate]10 keV mean photon energy and [approximate]50 keV maximum energy) in testing semiconductor discrete devices and integrated circuits for effects from ionizing radiation.
1.2 The X-ray tester may be appropriate for investigating the susceptibility of wafer level or delidded microelectronic devices to ionizing radiation effects. It is not appropriate for investigating other radiation-induced effects such as single-event effects (SEE) or effects due to displacement damage.
1.3 This guide focuses on radiation effects in metal oxide silicon (MOS) circuit elements, either designed (as in MOS transistors) or parasitic (as in parasitic MOS elements in bipolar transistors).
1.4 Information is given about appropriate comparison of ionizing radiation hardness results obtained with an X-ray tester to those results obtained with cobalt-60 gamma irradiation. Several differences in radiation-induced effects caused by differences in the photon energies of the X-ray and cobalt-60 gamma sources are evaluated. Quantitative estimates of the magnitude of these differences in effects, and other factors that should be considered in setting up test protocols, are presented.
1.5 If a 10-keV X-ray tester is to be used for qualification testing or lot acceptance testing, it is recommended that such tests be supported by cross checking with cobalt-60 gamma irradiations.
1.6 Comparisons of ionizing radiation hardness results obtained with an X-ray tester with results obtained with a linac, with protons, etc. are outside the scope of this guide.
1.7 Current understanding of the differences between the physical effects caused by X-ray and cobalt-60 gamma irradiations is used to provide an estimate of the ratio (number-of-holes-cobalt-60/(number-of-holes-X-ray). Several cases are defined where the differences in the effects caused by X rays and cobalt-60 gammas are expected to be small. Other cases where the differences could potentially be as great as a factor of four are described.
1.8 It should be recognized that neither X-ray testers nor cobalt-60 gamma sources will provide, in general, an accurate simulation of a specified system radiation environment. The use of either test source will require extrapolation to the effects to be expected from the specified radiation environment. In this guide, we discuss the differences between X-ray tester and cobalt-60 gamma effects. This discussion should be useful as background to the problem of extrapolation to effects expected from a different radiation environment. However, the process of extrapolation to the expected real environment is treated elsewhere (1, 2).  
1.9 The time scale of an X-ray irradiation and measurement may be much different than the irradiation time in the expected device application. Information on time-dependent effects is given.
1.10 Possible lateral spreading of the collimated X-ray beam beyond the desired irradiated region on a wafer is also discussed.
1.11 Information is given about recommended experimental methodology, dosimetry, and data interpretation.
1.12 Radiation testing of semiconductor devices may produce severe degradation of the electrical parameters of irradiated devices and should therefore be considered a destructive test.
1.13 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SIGNIFICANCE AND USE
The steady-state photocurrent of a simple p-n junction diode is a directly measurable quantity that can be directly related to device response over a wide range of ionizing radiation. For more complex devices the junction photocurrent may not be directly related to device response.
Zener Diode— In this device, the effect of the photocurrent on the Zener voltage rather than the photocurrent itself is usually most important. The device is most appropriately tested while biased in the Zener region. In testing Zener diodes or precision voltage regulators, extra precaution must be taken to make certain the photocurrent generated in the device during irradiations does not cause the voltage across the device to change during the test.
Bipolar Transistor—As device geometries dictate that photocurrent from the base-collector junction be much greater than current from the base-emitter junction, measurements are usually made only on the collector-base junction with emitter open; however, sometimes, to obtain data for computer-aided circuit analysis, the emitter-base junction photocurrent is also measured.
Junction Field-Effect Device—A proper photocurrent measurement requires that the source be shorted (dc) to the drain during measurement of the gate-channel photocurrent. In tetrode-connected devices, the two gate-channel junctions should be monitored separately.
Insulated Gate Field-Effect Device—In this type of device, the true photocurrent is between the substrate and the channel, source, and drain regions. A current which can generate voltage that will turn on the device may be measured by the technique used here, but it is due to induced conductivity in the gate insulator and thus is not a junction photocurrent.
SCOPE
1.1 This test method covers the measurement of steady-state primary photocurrent, Ipp, generated in semiconductor devices when these devices are exposd to ionizing radiation. These procedures are intended for the measurement of photocurrents greater than 10-9 A-s/Gy(Si or Ge), in cases for which the relaxation time of the device being measured is less than 25% of the pulse width of the ionizing source. The validity of these procedures for ionizing dose rates as great as 108Gy(Si or Ge)/s has been established. The procedures may be used for measurements at dose rates as great as 1010Gy(Si or Ge)/s; however, extra care must be taken. Above 108Gy/s the package response may dominate the device response for technologies such as complementary metal-oxide semiconductor, (CMOS)/silicon-on sapphire (SOS). Additional precautions are also required when measuring photocurrents of 10-9 A-s/Gy(Si or Ge) or lower.
1.2 Setup, calibration, and test circuit evaluation procedures are also included in this test method.
1.3 Because of the variability between device types and in the requirements of different applications, the dose rate range over which any specific test is to be conducted is not given in this test method but must be specified separately.
1.4 The values state in International System of Units (SI) are to be regarded as the standard. No other units of measurement are included in this standard.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SCOPE
1.1 This guide presents background and guidelines for establishing an appropriate sequence of tests and data analysis procedures for determining the ionizing radiation (total dose) hardness of microelectronic devices for dose rates below 300 rd(SiO2)/s. These tests and analysis will be appropriate to assist in the determination of the ability of the devices under test to meet specific hardness requirements or to evaluate the parts for use in a range of radiation environments.
1.2 The methods and guidelines presented will be applicable to characterization, qualification, and lot acceptance of silicon-based MOS and bipolar discrete devices and integrated circuits. They will be appropriate for treatment of the effects of electron and photon irradiation.
1.3 This guide provides a framework for choosing a test sequence based on general characteristics of the parts to be tested and the radiation hardness requirements or goals for these parts.
1.4 This guide provides for tradeoffs between minimizing the conservative nature of the testing method and minimizing the required testing effort.
1.5 Determination of an effective and economical hardness test typically will require several kinds of decisions. A partial enumeration of the decisions that typically must be made is as follows:
1.5.1 Determination of the Need to Perform Device CharacterizationFor some cases it may be more appropriate to adopt some kind of worst case testing scheme that does not require device characterization. For other cases it may be most effective to determine the effect of dose-rate on the radiation sensitivity of a device. As necessary, the appropriate level of detail of such a characterization also must be determined.
1.5.2 Determination of an Effective Strategy for Minimizing the Effects of Irradiation Dose Rate on the Test ResultThe results of radiation testing on some types of devices are relatively insensitive to the dose rate of the radiation applied in the test. In contrast, many MOS devices and some bipolar devices have a significant sensitivity to dose rate. Several different strategies for managing the dose rate sensitivity of test results will be discussed.
1.5.3 Choice of an Effective Test MethodologyThe selection of effective test methodologies will be discussed.
1.6 Low Dose RequirementsHardness testing of MOS and bipolar microelectronic devices for the purpose of qualification or lot acceptance is not necessary when the required hardness is 100 rd(SiO2) or lower.
1.7 SourcesThis guide will cover effects due to device testing using irradiation from photon sources, such as 60Co irradiators,  137Cs irradiators, and low energy (approximately 10 keV) X-ray sources. Other sources of test radiation such as linacs, Van de Graaff sources, Dymnamitrons, SEMs, and flash X-ray sources occasionally are used but are outside the scope of this guide.
1.8 Displacement damage effects are outside the scope of this guide, as well.
1.9 The values stated in SI units are to be regarded as the standard.

SIGNIFICANCE AND USE
Digital logic circuits are used in system applications where they are exposed to pulses of radiation. It is important to know the minimum radiation level at which transient failures can be induced, since this affects system operation.
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1.1 This guide is to assist experimenters in measuring the transient radiation upset threshold of silicon digital integrated circuits exposed to pulses of ionizing radiation greater than 103 Gy (Si)/s.
1.2 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

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1.1 This guide defines the requirements and procedures for testing integrated circuits and other devices for the effects of single event phenomena (SEP) induced by irradiation with heavy ions having an atomic number Z  >2. This description specifically excludes the effects of neutrons, protons, and other lighter particles that may induce SEP via another mechanism. SEP includes any manifestation of upset induced by a single ion strike, including soft errors (one or more simultaneous reversible bit flips), hard errors (irreversible bit flips), latchup (permanent high conducting state), transients induced in combinatorial devices which may introduce a soft error in nearby circuits, power field effect transistor (FET) burn-out and gate rupture. This test may be considered to be destructive because it often involves the removal of device lids prior to irradiation. Bit flips are usually associated with digital devices and latchup is usually confined to bulk complementary metal oxide semiconductor, (CMOS) devices, but heavy ion induced SEP is also observed in combinatorial logic programmable read only memory, (PROMs), and certain linear devices that may respond to a heavy ion induced charge transient. Power transitors may be tested by the procedure called out in Method 1080 of MIL STD 750.
1.2 The procedures described here can be used to simulate and predict SEP arising from the natural space environment, including galactic cosmic rays, planetary trapped ions and solar flares. The techniques do not, however, simulate heavy ion beam effects proposed for military programs. The end product of the test is a plot of the SEP cross section (the number of upsets per unit fluence) as a function of ion LET (linear energy transfer, or ionization deposited along the ion's path through the semiconductor). This data can be combined with the system's heavy ion environment to estimate a system upset rate.
1.3 Although protons can cause SEP, they are not included in this guide. A separate guide addressing proton induced SEP is being considered.
1.4 The values stated in International System of Units (SI) are to be regarded as standard. No other units of measurement are included in this guide.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

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1.1 This guide covers the use of overtesting in order to reduce the required number of parts that must be tested to meet a given quality acceptance standard. Overtesting is testing a sample number of parts at a stress higher than their specification stress in order to reduce the amount of necessary data taking. This guide discusses when and how overtesting may be applied to forming probabilistic estimates for the survival of electronic piece parts subjected to radiation stress. Some knowledge of the probability distribution governing the stress-to-failure of the parts is necessary though exact knowledge may be replaced by over-conservative estimates of this distribution.

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1.1 This test method covers the measurement of common-emitter d-c current gain (forward, hFE, or inverted, hFEI) of bipolar transistors, for which the collector-emitter leakage current, ICEO, is less than 10% of the collector current, IC, at which the measurement is to be made, and for which the shunt leakage current in the base circuit is less than 10% of the base current required.  
1.2 This test method is suitable for measurement of common-emitter d-c current gain at a single given value of test transistor collector current or over a given range of collector currents (for example, over the range of the transistor to be tested).  
1.2.1 The nominal ranges of collector current over which the three test circuits are intended to be used are as follows:  
1.2.1.1 Circuit 1, less than 100 [mu]A,  
1.2.1.2 Circuit 2, from 100 [mu]A to 100 mA, and  
1.2.1.3 Circuit 3, greater than 100 mA.  
1.3 This test method incorporates tests to determine if the power dissipated in the transistor is low enough that the temperature of the junction is approximately the same as the ambient temperature.  
1.4 The values stated in International System of Units (SI) are to be regarded as standard. No other units of measurement are included in this standard.
1.5 This standard does not purport to address the safety problems, if any, associated with its use. It is the responsibility of whoever uses this standard to consult and establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SIGNIFICANCE AND USE
Overtesting should be done when (a) testing by variables is impractical because of time and cost considerations or because the probability distribution of stress to failure cannot be estimated with sufficient accuracy, and (b) an unrealistically large number of parts would have to be tested at the specification stress for the necessary confidence and survival probability.
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1.1 This guide covers the use of overtesting in order to reduce the required number of parts that must be tested to meet a given quality acceptance standard. Overtesting is testing a sample number of parts at a stress higher than their specification stress in order to reduce the amount of necessary data taking. This guide discusses when and how overtesting may be applied to forming probabilistic estimates for the survival of electronic piece parts subjected to radiation stress. Some knowledge of the probability distribution governing the stress-to-failure of the parts is necessary though exact knowledge may be replaced by over-conservative estimates of this distribution.

SCOPE
1.1 This guide covers recommended procedures for the use of X-ray testers (that is, sources with a photon spectrum having [approximate]10 keV mean photon energy and [approximate]50 keV maximum energy) in testing semiconductor discrete devices and integrated circuits for effects from ionizing radiation.
1.2 The X-ray tester may be appropriate for investigating the susceptibility of wafer level or delidded microelectronic devices to ionizing radiation effects. It is not appropriate for investigating other radiation-induced effects such as single-event effects (SEE) or effects due to displacement damage.
1.3 This guide focuses on radiation effects in metal oxide silicon (MOS) circuit elements, either designed (as in MOS transistors) or parasitic (as in parasitic MOS elements in bipolar transistors).
1.4 Information is given about appropriate comparison of ionizing radiation hardness results obtained with an X-ray tester to those results obtained with cobalt-60 gamma irradiation. Several differences in radiation-induced effects caused by differences in the photon energies of the X-ray and cobalt-60 gamma sources are evaluated. Quantitative estimates of the magnitude of these differences in effects, and other factors that should be considered in setting up test protocols, are presented.
1.5 If a 10-keV X-ray tester is to be used for qualification testing or lot acceptance testing, it is recommended that such tests be supported by cross checking with cobalt-60 gamma irradiations.
1.6 Comparisons of ionizing radiation hardness results obtained with an X-ray tester with results obtained with a linac, with protons, etc. are outside the scope of this guide.
1.7 Current understanding of the differences between the physical effects caused by X-ray and cobalt-60 gamma irradiations is used to provide an estimate of the ratio (number-of-holes-cobalt-60/(number-of-holes-X-ray). Several cases are defined where the differences in the effects caused by X rays and cobalt-60 gammas are expected to be small. Other cases where the differences could potentially be as great as a factor of four are described.
1.8 It should be recognized that neither X-ray testers nor cobalt-60 gamma sources will provide, in general, an accurate simulation of a specified system radiation environment. The use of either test source will require extrapolation to the effects to be expected from the specified radiation environment. In this guide, we discuss the differences between X-ray tester and cobalt-60 gamma effects. This discussion should be useful as background to the problem of extrapolation to effects expected from a different radiation environment. However, the process of extrapolation to the expected real environment is treated elsewhere (1, 2).  
1.9 The time scale of an X-ray irradiation and measurement may be much different than the irradiation time in the expected device application. Information on time-dependent effects is given.
1.10 Possible lateral spreading of the collimated X-ray beam beyond the desired irradiated region on a wafer is also discussed.
1.11 Information is given about recommended experimental methodology, dosimetry, and data interpretation.
1.12 Radiation testing of semiconductor devices may produce severe degradation of the electrical parameters of irradiated devices and should therefore be considered a destructive test.
1.13 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

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1.1 This test method covers the measurement of steady-state primary photocurrent, Ipp, generated in semiconductor devices when these devices are exposd to ionizing radiation. These procedures are intended for the measurement of photocurrents greater than 10-9 A-s/Gy(Si or Ge), in cases for which the relaxation time of the device being measured is less than 25% of the pulse width of the ionizing source. The validity of these procedures for ionizing dose rates as great as 108Gy(Si or Ge)/s has been established. The procedures may be used for measurements at dose rates as great as 1010Gy(Si or Ge)/s; however, extra care must be taken. Above 108Gy/s the package response may dominate the device response for technologies such as complementary metal-oxide semiconductor, (CMOS)/silicon-on sapphire (SOS). Additional precautions are also required when measuring photocurrents of 10-9 A-s/Gy(Si or Ge) or lower.
1.2 Setup, calibration, and test circuit evaluation procedures are also included in this test method.
1.3 Because of the variability between device types and in the requirements of different applications, the dose rate range over which any specific test is to be conducted is not given in this test method but must be specified separately.
1.4 The values state in International System of Units (SI) are to be regarded as the standard. No other units of measurement are included in this standard.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

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1.1 This practice applies to the exposure of unbiased silicon (Si) or gallium arsenide (GaAs) semiconductor components to neutron radiation from a nuclear reactor source. Only the conditions of exposure are addressed in this practice. The effects of radiation on the test sample should be determined using appropriate electrical test methods.
1.2 System and subsystem exposures and test methods are not included in this practice.
1.3 This practice is applicable to irradiations conducted with the reactor operating in either the pulsed or steady-state mode. The practical limits for neutron fluence ([phi]eq,1MeV,Si or [phi]eq,1MeV,GaAs) in semiconductor testing range from approximately 10  to 10 16  n/cm .
1.4 This practice addresses those issues and concerns pertaining to irradiations with neutrons of energies greater than 10 keV.
1.5 This standard does not purport to address all of the safety problems, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SCOPE
1.1 This practice applies to the exposure of unbiased silicon (Si) or gallium arsenide (GaAs) semiconductor components to neutron radiation from a nuclear reactor source. Only the conditions of exposure are addressed in this practice. The effects of radiation on the test sample should be determined using appropriate electrical test methods.
1.2 System and subsystem exposures and test methods are not included in this practice.
1.3 This practice is applicable to irradiations conducted with the reactor operating in either the pulsed or steady-state mode. The practical limits for neutron fluence ([phi]eq,1MeV,Si or [phi]eq,1MeV,GaAs) in semiconductor testing range from approximately 10  to 10 16  n/cm .
1.4 This practice addresses those issues and concerns pertaining to irradiations with neutrons of energies greater than 10 keV.
1.5 This standard does not purport to address all of the safety problems, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SIGNIFICANCE AND USE
The use of FXR radiation sources for the determination of high dose-rate burnout in semiconductor devices is addressed in this guide. The goal of this guide is to provide a systematic approach to testing for burnout.
The different type of failure modes that are possible are defined and discussed in this guide. Specifically, failure can be defined by a change in device parameters, or by a catastrophic failure of the device.
This guide can be used to determine the survivability of a device, that is, that the device survives a predetermined level; or the guide can be used to determine the survival dose-rate capability of the device. However, since this latter test is destructive, the minimum dose-rate level for failure must be determined statistically.
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1.1 This guide defines the detailed requirements for testing microcircuits for short pulse high dose-rate ionization-induced failure. Large flash x-ray (FXR) machines operated in the photon mode, or FXR e-beam facilities are required because of the high dose-rate levels that are necessary to cause burnout. Two modes of test are possible (1) survival test, and (2) A failure level test.  
1.2 The values stated in International System of Units (SI) are to be regarded as standard. No other units of measurement are included in this standard.

SIGNIFICANCE AND USE
The electrical properties of gate and field oxides are altered by ionizing radiation. The time dependent and dose rate effects of the ionizing radiation can be determined by comparing pre- and post-irradiation voltage shifts, ΔVot andΔ Vit. This test method provides a means for evaluation of the ionizing radiation response of MOSFETs and isolation parasitic MOSFETs.
The measured voltage shifts, ΔVot andΔ Vit, can provide a measure of the effectiveness of processing variations on the ionizing radiation response.
This technique can be used to monitor the total-dose response of a process technology.
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1.1 This test method covers the use of the subthreshold charge separation technique for analysis of ionizing radiation degradation of a gate dielectric in a metal-oxide-semiconducter-field-effect transistor (MOSFET) and an isolation dielectic in a parasitic MOSFET. The subthreshold technique is used to separate the ionizing radiation-induced inversion voltage shift, V INV into voltage shifts due to oxide trapped charge, Vot and interface traps, Vit. This technique uses the pre- and post-irradiation drain to source current versus gate voltage characteristics in the MOSFET subthreshold region.
1.2 Procedures are given for measuring the MOSFET subthreshold current-voltage characteristics and for the calculation of results.
1.3 The application of this test method requires the MOSFET to have a substrate (body) contact.
1.4 Both pre- and post-irradiation MOSFET subthreshold source or drain curves must follow an exponential dependence on gate voltage for a minimum of two decades of current.
1.5 The values given in SI units are to be regarded as standard. No other units of measurement are included in this test method.
1.6 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SCOPE
1.1 This test method covers the use of the subthreshold charge separation technique for analysis of ionizing radiation degradation of a gate dielectric in a metal-oxide-semiconducter-field-effect transistor (MOSFET) and an isolation dielectic in a parasitic MOSFET.      The subthreshold technique is used to separate the ionizing radiation-induced inversion voltage shift, [delta]VINV into voltage shifts due to oxide trapped charge, [delta]Vot and interface traps, [delta]Vit. This technique uses the pre- and post-irradiation drain to source current versus gate voltage characteristics in the MOSFET subthreshold region.
1.2 Procedures are given for measuring the MOSFET subthreshold current-voltage characteristics and for the calculation of results.
1.3 The application of this test method requires the MOSFET to have a substrate (body) contact. MOSFETs on silicon-on-insulator (SOI) technology must have body ties.
1.4 Both pre- and post-irradiation MOSFET subthreshold source or drain curves must follow an exponential dependence on gate voltage for a minimum of two decades of current.
1.5 This standard does not purport to address all of the safety problems, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SCOPE
1.1 This guide defines the detailed requirements for testing microcircuits for short pulse high dose-rate ionization-induced failure. Large flash x-ray (FXR) machines operated in the photon mode, or FXR e-beam facilities are required because of the high dose-rate levels that are necessary to cause burnout. Two modes of test are possible (1) survival test, and (2) A failure level test.  
1.2 The values stated in International System of Units (SI) are to be regarded as standard. No other units of measurement are included in this standard.

SCOPE
1.1 This guide presents background and guidelines for establishing an appropriate sequence of tests and data analysis procedures for determining the ionizing radiation (total dose) harness of microelectronic devices for dose rates below 300 rd(SiO2)/s. These tests and analysis will be appropriate to assist in the determination of the ability of the devices under test to meet specific hardness requirements or to evaluate the parts for use in a range of radiation environments.
1.2 The methods and guidelines presented will be applicable to characterization, qualification, and lot acceptance of silicon-based MOS and bipolar discrete devices and integrated circuits. They will be appropriate for treatment of the effects of electron and photon irradiation.
1.3 This guide provides a framework for choosing a test sequence based on general characteristics of the parts to be tested and the radiation hardness requirements or goals for these parts.
1.4 This guide provides for tradeoffs between minimizing the conservative nature of the testing method and minimizing the required testing effort.
1.5 Determination of an effective and economical hardness test typically will require several kinds of decisions. A partial enumeration of the decisions that typically must be made is as follows:
1.5.1 Determination of the Need to Perform Device Characterization-For some cases it may be more appropriate to adopt some kind of worst case testing scheme that does not require device characterization. For other cases it may be most effective to determine the effect of dose-rate on the radiation sensitivity of a device. As necessary, the appropriate level of detail of such a characterization also must be determined.
1.5.2 Determination of an Effective Strategy for Minimizing the Effects of Irradiation Dose Rate on the Test Result-The results of radiation testing on some types of devices are relatively insensitive to the dose rate of the radiation applied in the test. In constrast, many MOS devices and some bipolar devices have a significant sensitivity to dose rate. Several different strategies for managing the dose rate sensitivity of test results will be discussed.
1.5.3 Choice of an Effective Test Methodology-The selection of effective test methodologies will be discussed.
1.6 Low Dose Requirements-Hardness testing of MOS and bipolar microelectronic devices for the purpose of qualification or lot acceptance is not neceassary when the required hardness is 100 rd(SiO2) or lower.
1.7 Sources-This guide will cover effects due to device testing using irradiation from photon sources, such as 60Co y irradiators, 137Cs y irradiators, and low energy (approximately 10 keV) X-ray sources. Other sources of test radiation such as linacs, Van de Graaff sources, Dymnamitrons, SEM's and flash X-ray sources occasionally are used but are outside the scope of this guide.
1.8 Displacement damage effects are outside the scope of this guide, as well.
1.9 The values stated in SI units are to be regarded as the standard.

SCOPE
1.1 This test method covers the measurement of the threshold level of radiation dose rate that causes upset in digital integrated circuits under static operating conditions. The radiation source is either a flash X-ray machine (FXR) or an electron linear accelerator (LINAC).
1.2 The precision of the measurement depends on the homogeneity of the radiation field and on the precision of the radiation dosimetry and the recording instrumentation.
1.3 The test may be destructive either for further tests or for purposes other than this test if the integrated circuit being tested absorbs a total radiation dose exceeding some predetermined level. Because this level depends both on the kind of integrated circuit and on the application, a specific value must be agreed upon by the parties to the test (6.8).
1.4 Setup, calibration, and test circuit evaluation procedures are included in this test method.
1.5 Procedures for lot qualification and sampling are not included in this test method.
1.6 Because of the variability of the response of different device types, the initial dose rate for any specific test is not given in this test method but must be agreed upon by the parties to the test.
1.7 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SCOPE
1.1 This test method covers the measurement of the threshold level of radiation dose rate that causes upset in digital integrated circuits under static operating conditions. The radiation source is either a flash X-ray machine (FXR) or an electron linear accelerator (LINAC).  
1.2 The precision of the measurement depends on the homogeneity of the radiation field and on the precision of the radiation dosimetry and the recording instrumentation.  
1.3 The test may be destructive either for further tests or for purposes other than this test if the integrated circuit being tested absorbs a total radiation dose exceeding some predetermined level. Because this level depends both on the kind of integrated circuit and on the application, a specific value must be agreed upon by the parties to the test (6.9).  
1.4 Setup, calibration, and test circuit evaluation procedures are included in this test method.  
1.5 Procedures for lot qualification and sampling are not included in this test method.  
1.6 Because of the variability of the response of different device types, the initial dose rate for any specific test is not given in this test method but must be agreed upon by the parties to the test.  
1.7 This standard does not purport to address all of the safety problems, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use. For more specific hazard statements, see 7.7.2.

SIGNIFICANCE AND USE
Electronic circuits used in many space, military, and nuclear power systems may be exposed to various levels and time profiles of neutron radiation. It is essential for the design and fabrication of such circuits that test methods be available that can determine the vulnerability or hardness (measure of nonvulnerability) of components to be used in them. A determination of hardness is often necessary for the short term (≈100 μs) as well as long term (permanent damage) following exposure. See Practice E722.
SCOPE
1.1 This guide defines the requirements and procedures for testing silicon discrete semiconductor devices and integrated circuits for rapid-annealing effects from displacement damage resulting from neutron radiation. This test will produce degradation of the electrical properties of the irradiated devices and should be considered a destructive test. Rapid annealing of displacement damage is usually associated with bipolar technologies.  
1.1.1 Heavy ion beams can also be used to characterize displacement damage annealing (1) , but ion beams have significant complications in the interpretation of the resulting device behavior due to the associated ionizing dose. The use of pulsed ion beams as a source of displacement damage is not within the scope of this standard.
1.2 The values stated in SI units are to be regarded as standard. No other units of measurement are included in this standard.
1.3 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to consult and establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SIGNIFICANCE AND USE
Electronic circuits used in many space, military, and nuclear power systems may be exposed to various levels and time profiles of neutron radiation. It is essential for the design and fabrication of such circuits that test methods be available that can determine the vulnerability or hardness (measure of nonvulnerability) of components to be used in them. A determination of hardness is often necessary for the short term (≈100 μs) as well as long term (permanent damage) following exposure.
SCOPE
1.1 This guide defines the requirements and procedures for testing silicon discrete semiconductor devices and integrated circuits for rapid-annealing effects from displacement damage resulting from neutron radiation. This test will produce degradation of the electrical properties of the irradiated devices and should be considered a destructive test. Rapid annealing of displacement damage is usually associated with bipolar technologies.
1.2 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to consult and establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SCOPE
1.1 This test method covers the measurement of MOSFET (Note 1) drain leakage current.
Note 1-MOS is an acronym for metal-oxide semiconductor; FET is an acronym for field-effect transistor.
1.2 This test method is applicable to all enhancement-mode and depletion-mode MOSFETs. This test method specifies positive voltage and current, conventions specifically applicable to n-channel MOSFETs. The substitution of negative voltage and negative current makes the method directly applicable to p-channel MOSFETs.
1.3 The d-c test method is applicable for the range of drain voltages greater than 0 V but less than the drain breakdown voltage.
1.4 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SCOPE
1.1 This practice covers the measurement of the response of linear integrated circuits, under given operating conditions, to pulsed ionizing radiation. The response may be either transient or more lasting, such as latchup. The radiation source is either a flash X-ray machine (FXR) or an electron linear accelerator (LINAC).
1.2 The precision of the measurement depends on the homogeneity of the radiation field and on the precision of the radiation dosimetry and the recording instrumentation.
1.3 The test may be considered to be destructive either for further tests or for other purposes if the total radiation dose exceeds some predetermined level or if the part should latch up. Because this level depends both on the kind of integrated circuit and on the application, a specific value must be agreed upon by the parties to the test. (See 6.10.)
1.4 Setup, calibration, and test circuit evaluation procedures are included in this practice.
1.5 Procedures for lot qualification and sampling are not included in this practice.
1.6 Because response varies with different device types, the dose rate range for any specific test is not given in this practice but must be agreed upon by the parties to the test.
1.7 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SCOPE
1.1 This practice covers the measurement of the response of linear integrated circuits, under given operating conditions, to pulsed ionizing radiation. The response may be either transient or more lasting, such as latchup. The radiation source is either a flash X-ray machine (FXR) or an electron linear accelerator (LINAC).
1.2 The precision of the measurement depends on the homogeneity of the radiation field and on the precision of the radiation dosimetry and the recording instrumentation.
1.3 The test may be considered to be destructive either for further tests or for other purposes if the total radiation dose exceeds some predetermined level or if the part should latch up. Because this level depends both on the kind of integrated circuit and on the application, a specific value must be agreed upon by the parties to the test. (See 6.10)
1.4 Setup, calibration, and test circuit evaluation procedures are included in this practice.
1.5 Procedures for lot qualifications and sampling are not included in this practice.
1.6 Because response varies with different device types, the dose rate range for any specific test is not given in this practice but must be agreed upon by the parties to the test.
1.7 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SCOPE
1.1 This test method is designed for determining the average electrical width of a narrow thin-film metallization line.
1.2 This test method is intended for measuring thin metallization lines such as are used in microelectronic circuits where the width of the lines may range from micrometres to tenths of micrometres.  
1.3 The test structure used in this test method may be measured while still part of a wafer, or part therefrom, or as part of a test chip bonded to a package and electrically accessible by means of package terminals.
1.4 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SCOPE
1.1 This guide covers recommended design features for test structures used in accelerated stress tests, as described in Test Method F 1260, to characterize the failure distribution of interconnect metallizations that fail due to electromigration.
1.2 The guide is restricted to structures with a straight test line on a flat surface that are used to detect failures due to an open-circuit or a percent-increase in resistance of the test line.
1.3 This guide is not intended for testing metal lines whose widths are approximately equal to or less than the estimated mean size of the metal grains in the metallization line.  
1.4 This guide is not intended for test structures used to detect random defects in a metallization line.  
1.5 Metallizations tested and characterized are those that are used in microelectronic circuits and devices.

SCOPE
1.1 This test method is designed to characterize the failure distribution of interconnect metallizations such as are used in microelectronic circuits and devices that fail due to electromigration under specified d-c current-density and temperature stress. This test method is intended to be used only when the failure distribution can be described by a log-Normal distribution.
1.2 This test method is intended for use as a referee method between laboratories and for comparing metallization alloys and metallizations prepared in different ways. It is not intended for qualifying vendors or for determining the use-life of a metallization.
1.3 The test method is an accelerated stress test of four-terminal structures (see Guide F 1259M) where the failure criterion is either an open circuit in the test line or a prescribed percent increase in the resistance of the test structure.
1.4 This test method allows the test structures of a test chip to be stressed while still part of the wafer (or a portion thereof) or while bonded to a package and electrically accessible by means of package terminals.
1.5 This test method is not designed to characterize the metallization for failure modes involving short circuits between adjacent metallization lines or between two levels of metallization.
1.6 This test method is not intended for the case where the stress test is terminated before all parts have failed.
1.7 This test method is primarily designed to analyze complete data. An option is provided for analyzing censored data (that is, when the stress test is halted before all parts under test have failed).  
1.8 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SCOPE
1.1 This guide defines the requirements and procedures for testing silicon discrete semiconductor devices and integrated circuits for rapid-annealing effects from displacement damage resulting from neutron radiation. This test will produce degradation of the electrical properties of the irradiated devices and should be considered a destructive test. Rapid annealing of displacement damage is usually associated with bipolar technologies.  
1.2 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SCOPE
1.1 This guide is to assist experimenters in measuring the transient radiation upset threshold of silicon digital integrated circuits exposed to pulses of ionizing radiation greater than 103 Gy (Si)/s.
1.2 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SCOPE
1.1 This practice covers procedures for determining operating regions that are safe from metallization burnout induced by current pulses of less than 1-s duration.
Note 1—In this practice, "metallization" refers to metallic layers on semiconductor components such as interconnect patterns on integrated circuits. The principles of the practice may, however, be extended to nearly any current-carrying path. The term "burnout" refers to either fusing or vaporization.
1.2 This practice is based on the application of unipolar rectangular current test pulses. An extrapolation technique is specified for mapping safe operating regions in the pulse-amplitude versus pulse-duration plane. A procedure is provided in to relate safe operating regions established from rectangular pulse data to safe operating regions for arbitrary pulse shapes.
1.3 This practice is not intended to apply to metallization damage mechanisms other than fusing or vaporization induced by current pulses and, in particular, is not intended to apply to long-term mechanisms, such as metal migration.
1.4 This practice is not intended to determine the nature of any defect causing failure.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SCOPE
1.1 This practice covers procedures for determining operating regions that are safe from metallization burnout induced by current pulses of less than 1-s duration.
Note 1—In this practice, "metallization" refers to metallic layers on semiconductor components such as interconnect patterns on integrated circuits. The principles of the practice may, however, be extended to nearly any current-carrying path. The term "burnout" refers to either fusing or vaporization.
1.2 This practice is based on the application of unipolar rectangular current test pulses. An extrapolation technique is specified for mapping safe operating regions in the pulse-amplitude versus pulse-duration plane. A procedure is provided in Appendix X2 to relate safe operating regions established from rectangular pulse data to safe operating regions for arbitrary pulse shapes.
1.3 This practice is not intended to apply to metallization damage mechanisms other than fusing or vaporization induced by current pulses and, in particular, is not intended to apply to long-term mechanisms, such as metal migration.
1.4 This practice is not intended to determine the nature of any defect causing failure.
1.5 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

SCOPE
1.1 This test method covers the measurement of the unsaturated sink current of transistor-transistor logic (TTL) devices under specified conditions.
1.2 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.