ASTM F1260M-96

Standard Test Method for Estimating Electromigration Median Time-To-Failure and Sigma of Integrated Circuit Metallizations [Metric]

SCOPE
1.1 This test method is designed to characterize the failure distribution of interconnect metallizations such as are used in microelectronic circuits and devices that fail due to electromigration under specified d-c current-density and temperature stress. This test method is intended to be used only when the failure distribution can be described by a log-Normal distribution.
1.2 This test method is intended for use as a referee method between laboratories and for comparing metallization alloys and metallizations prepared in different ways. It is not intended for qualifying vendors or for determining the use-life of a metallization.
1.3 The test method is an accelerated stress test of four-terminal structures (see Guide F 1259M) where the failure criterion is either an open circuit in the test line or a prescribed percent increase in the resistance of the test structure.
1.4 This test method allows the test structures of a test chip to be stressed while still part of the wafer (or a portion thereof) or while bonded to a package and electrically accessible by means of package terminals.
1.5 This test method is not designed to characterize the metallization for failure modes involving short circuits between adjacent metallization lines or between two levels of metallization.
1.6 This test method is not intended for the case where the stress test is terminated before all parts have failed.
1.7 This test method is primarily designed to analyze complete data. An option is provided for analyzing censored data (that is, when the stress test is halted before all parts under test have failed).  
1.8 This standard does not purport to address all of the safety concerns, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

General Information

• Status: Historical
• Publication Date: 31-Dec-1995
• ICS: 17.220.20 - Measurement of electrical and magnetic quantities
• ICS: 31.200 - Integrated circuits. Microelectronics
• Technical Committee: F01 - Electronics
• Drafting Committee: F01.11 - Nuclear and Space Radiation Effects

Relations

• Replaces: ASTM F1260-89 - Test Method for Estimating Electromigration Median Time-To-Failure and Sigma of Integrated Circuit Metallizations
• Effective Date: 01-Jan-1996
• Replaced By: ASTM F1260M-96(2003) - Standard Test Method for Estimating Electromigration Median Time-to-Failure and Sigma of Integrated Circuit Metallizations [Metric] (Withdrawn 2009)
• Effective Date: 10-Jun-1996

Standards Content (Sample)

NOTICE: This standard has either been superceded and replaced by a new version or discontinued.
Contact ASTM International (www.astm.org) for the latest information.
Designation: F 1260M – 96
METRIC
Standard Test Method
for Estimating Electromigration Median Time-To-Failure and
1
Sigma of Integrated Circuit Metallizations [Metric]
This standard is issued under the fixed designation F 1260M; the number immediately following the designation indicates the year of
original adoption or, in the case of revision, the year of last revision. A number in parentheses indicates the year of last reapproval. A
superscript epsilon (e) indicates an editorial change since the last revision or reapproval.
1. Scope 2. Referenced Documents
1.1 This test method is designed to characterize the failure 2.1 ASTM Standards:
distribution of interconnect metallizations such as are used in F 1259M Guide for Design of Flat, Straight-Line Test
microelectronic circuits and devices that fail due to electromi- Structures for Detecting Metallization Open-Circuit or
gration under specified d-c current density and temperature Resistance-Increase Failure due to Electromigration [Met-
2
stress. This test method is intended to be used only when the ric]
failure distribution can be described by a log-Normal distribu- F 1261M Test Method for Determining the Average Elec-
2
tion. trical Width of a Straight, Thin-Film Metal Line [Metric]
1.2 This test method is intended for use as a referee method 2.2 Other Standards:
between laboratories and for comparing metallization alloys EIA/JEDEC Standard 33-A— Standard Method for Mea-
and metallizations prepared in different ways. It is not intended suring and Using the Temperature Coefficient of Resis-
for qualifying vendors or for determining the use-life of a tance to Determine the Temperature of a Metallization
3
metallization. Line
1.3 The test method is an accelerated stress test of four- EIA/JEDEC Standard 37— Lognormal Analysis of Uncen-
terminal structures (see Guide F 1259M) where the failure sored Data, and of Singly Right-Censored Data Utilizing
3
criterion is either an open circuit in the test line or a prescribed the Persson and Rootzen Method
percent increase in the resistance of the test structure.
3. Terminology
1.4 This test method allows the test structures of a test chip
3.1 Definitions of Terms Specific to This Standard:
to be stressed while still part of the wafer (or a portion thereof)
or while bonded to a package and electrically accessible by 3.1.1 metallization—the thin-film metallic conductor used
as electrical interconnects in a microelectronic integrated
means of package terminals.
1.5 This test method is not designed to characterize the circuit.
3.1.2 test chip—an area on a wafer containing one or more
metallization for failure modes involving short circuits be-
tween adjacent metallization lines or between two levels of test structures that are stressed according to the test method
while either is still part of the wafer or after having been
metallization.
1.6 This test method is not intended for the case where the separated and packaged.
3.1.3 test line—a straight metallization line of designed
stress test is terminated before all parts have failed.
uniform width that is subjected to the current density and
1.7 This test method is primarily designed to analyze
complete data. An option is provided for analyzing censored temperature stresses prescribed in the test method.
3.1.4 test structure—a passive metallization structure, with
data (that is, when the stress test is halted before all parts under
test have failed). terminals to permit electrical access, that is fabricated on a
semiconductor wafer by the normal procedures used to manu-
1.8 This standard does not purport to address all of the
safety concerns, if any, associated with its use. It is the facture microelectronic integrated devices.
responsibility of the user of this standard to establish appro-
4. Summary of Test Method
priate safety and health practices and determine the applica-
4.1 This test method is used to obtain sample estimates of
bility of regulatory limitations prior to use.
the median-time-to-failure, t , and sigma that describe the
50
failure distribution of metallization test lines subjected to
1
This test method is under the jurisdiction of ASTM Committee F-1 on
Electronics and is the direct responsibility of Subcommittee F01.11 on Quality and
Hardness Assurance. 2
Annual Book of ASTM Standards, Vol 10.04.
Current edition approved June 10, 1996. Published August 1996. Originally 3
Available from Global Engineering, 15 Inverness Way, East Inglewood, CO
published as F 1260 – 89. Last previous edition F 1260 – 89.
80112-5776.
Copyright © ASTM, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959, United States.
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NOTICE: This standard has either been superceded and replaced by a new version or discontinued.
Contact ASTM International (www.astm.o
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