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ASTM F1152-02

(Test Method)

Standard Test Method for Dimensions of Notches on Silicon Wafers (Withdrawn 2003)

Standard Test Method for Dimensions of Notches on Silicon Wafers (Withdrawn 2003)

SCOPE
This standard was transferred to SEMI (www.semi.org) May 2003
1.1 This test method covers a nondestructive procedure to determine whether or not the dimensions of fiducial notches on silicon wafers fall within specified limits.
1.2 The values stated in SI units are to be regarded as the standard. The values given in parentheses are for information only.
1.3  This standard does not purport to address all of the safety problems, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory limitations prior to use.

General Information

Status
Withdrawn
Publication Date
09-Jan-2002
Withdrawal Date
11-Aug-2003
ICS
29.045 - Semiconducting materials
Technical Committee
F01 - Electronics
Current Stage
Ref Project

Relations

Replaces
ASTM F1152-93(2001) - Standard Test Method for Dimensions of Notches on Silicon Wafers
Effective Date
10-Jan-2002

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ASTM F1152-02 - Standard Test Method for Dimensions of Notches on Silicon Wafers (Withdrawn 2003)ASTM F1152-02 - Standard Test Method for Dimensions of Notches on Silicon Wafers (Withdrawn 2003)
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ASTM F1152-02 - Standard Test Method for Dimensions of Notches on Silicon Wafers (Withdrawn 2003)
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Standards Content (Sample)

NOTICE: This standard has either been superceded and replaced by a new version or discontinued.
Contact ASTM International (www.astm.org) for the latest information.
Designation: F 1152 – 02
Standard Test Method for
1
Dimensions of Notches on Silicon Wafers
This standard is issued under the fixed designation F 1152; the number immediately following the designation indicates the year of
original adoption or, in the case of revision, the year of last revision. A number in parentheses indicates the year of last reapproval. A
superscript epsilon (e) indicates an editorial change since the last revision or reapproval.
1. Scope 3.4 The image of the notch sides are compared with a series
of angles on the notch angle template and the angle that makes
1.1 This test method covers a nondestructive procedure to
the best fit is chosen as the value of the notch angle.
determine whether or not the dimensions of fiducial notches on
3.5 No test is provided for the blend radius at the apex of the
silicon wafers fall within specified limits.
notch.
1.2 The values stated in SI units are to be regarded as the
standard. The values given in parentheses are for information
4. Significance and Use
only.
4.1 Wafers must be accurately aligned in various processing
1.3 This standard does not purport to address all of the
equipment during integrated circuit manufacture.
safety concerns, if any, associated with its use. It is the
4.2 A notch ground into the edge of the wafer at a specified
responsibility of the user of this standard to establish appro-
orientation provides a positive method for such alignment. The
priate safety and health practices and determine the applica-
accuracy of the critical dimensions of the notch controls the
bility of regulatory limitations prior to use.
possible accuracy of the alignment.
2. Referenced Documents 4.3 This test method is specifically directed to the notch
dimensions specified in SEMI Specifications M 1, but with
2.1 ANSI Standard:
suitable modifications, the principles of this test method may
ANSI/ASQC Z1.4–1993 Sampling Procedures and Tables
2
be applied to any desired notch dimensions.
for Inspection by Attributes
4.4 This test method may be used for process control,
2.2 SEMI Standard:
3
quality control, and incoming or outgoing inspection.
M 1 Specifications for Monocrystalline Silicon Wafers
4.5 Until an index of precision is determined based on an
3. Summary of Test Method
interlaboratory evaluation, this test method is not recom-
mended for use in decisions between purchasers and suppliers.
3.1 The wafer is aligned in position on an optical compara-
tor and the image of the notch is compared with a series of
5. Interferences
templates projected on the screen of the comparator.
5.1 Any foreign material or rough spots on the notch edge in
3.2 First, the wafer is aligned so that the sides of the image
the light path may present a distorted image which can result in
of the notch contact the image of the alignment pin used to fix
the determination of incorrect dimensions.
the position of the wafer in use. In this case, the image of the
5.2 Alignment of the notch position with respect to the
notch bottom must lie on or below the designated line on the
center of the wafer is important in achieving an accurate
notch form/depth template and the image of the wafer edge
determination of the notch characteristics.
must lie on or above another designated line on the template.
5.3 Wear of grinding tools and process variations may result
3.3 The wafer is then aligned so that the image of the wafer
in notch edges which are not exactly straight and a nonunique
edge coincides with the wafer periphery line on the template.
radius at the apex of the notch. Under these conditions, great
In this case the image of the notch bottom must lie between
care must be taken to align the image of the notch correctly
maximum and minimum lines on the template.
against the appropriate portions of the template.
1 6. Apparatus
This test method is under the jurisdiction of ASTM Committee F01 on
Electronics and is the direct responsibility of Subcommittee F01.06 on Silicon
6.1 Optical Comparator, capable of 20 and 503 magnifi-
Materials and Process Control.
cation with a viewing screen large enough to display an area 5
Current edition approved Jan. 10, 2002. Published March 2002. Originally
by5mmat203 or2by2mmat503.
published as F 1152 – 88. Last previous edition F 1152 – 93.
2
Available from American National Standards Institute, 1819 L Street, N.W.,
6.2 Fixture, for holding the wafer to be tested. The fixture
Washington, DC 20036.
must provide means for positioning the wafer such that the
3
Available from the Semiconductor Equipment and Materials Institute, 805
plane of the surface of the wafer is perpendicular to the
Middlefield Rd., Mountain View, CA 94043.
Copyright © ASTM International, 100 Barr Harbor Drive, PO Box C700, West Conshohocken, PA 19428-2959, United States.
1

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