EN 16602-60-12:2014

Space product assurance - Design, selection, procurement and use of die form monolithic microwave integrated circuits (MMICs)

This Standard applies to all types of MMIC (monolithic microwave integrated circuit) based on III V compound materials for RF applications (i.e. frequency range ≥ 1 GHz). The requirements for the procurement of components in die form are defined.
It is not within the scope of this Standard to address packaged MMICs and discrete microwave components, these are dealt with in the relevant ESCC specification (ESCC 9010 and ESCC 5010).
This standard may be tailored for the specific characteristic and constraints of a space project in conformance with ECSS-S-ST-00.

Raumfahrtproduktsicherung - Design, Auswahl, Beschaffung und Nutzung von MMIC

Assurance produit des projets spatiaux - Conception, sélection, approvisionnement et utilisation de circuits intégrés monolithique hyperfréquence de forme die

La présente Norme s'applique à tous les types de MMIC (circuit intégré monolithique hyperfréquence) basés sur des matériaux composites de type III V pour les applications RF (par exemple, plage de fréquences ≥ 1 GHz). Elle définit les exigences en matière d'approvisionnement de composants de forme die.
Les MMIC conditionnés en boîtiers et les composants hyperfréquence discrets, qui sont traités dans les spécifications ESCC correspondantes (ESCC 9010 et ESCC 5010) n'entrent pas dans le champ d'application de la présente Norme.
La présente norme peut être adaptée aux caractéristiques et contraintes spécifiques d'un projet spatial conformément à l'ECSS-S-ST-00.

Zagotavljanje varnih proizvodov v vesoljski tehniki - Snovanje, izbiranje, nabava in uporaba monolitnih mikrovalovnih integriranih vezij (MMIC) v obliki čipov

Ta standard se uporablja za vse tipe MMIC (monolitnih mikrovalovnih integriranih vezij) na podlagi sestavljenih materialov III V za radiofrekvenčne uporabe (tj. frekvenčno območje ≥ 1 GHz). Opredeljene so zahteve za naročanje komponent v obliki čipov.  Področje uporabe tega standarda ne zajema pakiranih MMIC in diskretnih mikrovalovnih komponent, ki so obravnavani v ustrezni specifikaciji ESCC (ESCC 9010 in ESCC 5010). Ta standard se lahko prilagodi posameznim lastnostim in omejitvam vesoljskega projekta v skladu s standardom ECSS-S-ST-00.

General Information

• Status: Published
• Publication Date: 23-Sep-2014
• Withdrawal Date: 30-Mar-2015
• ICS: 49.140 - Space systems and operations
• Technical Committee: CEN/CLC/TC 5 - Space
• Drafting Committee: CEN/CLC/TC 5 - Space
• Current Stage: 9060 - Closure of 2 Year Review Enquiry - Review Enquiry
• Start Date: 03-Mar-2020
• Completion Date: 03-Mar-2020
• Mandate: M/496 - Mandate addressed to CEN, CENELEC and ETSI to develop standardisation regarding space industry (Phase 3 of the process)
• Ref Project: SIST EN 16602-60-12:2015 - Space product assurance - Design, selection, procurement and use of die form monolithic microwave integrated circuits (MMICs)

Overview - EN 16602-60-12:2014 (Space product assurance, MMIC die form)

EN 16602-60-12:2014 is the CEN European Standard for the design, selection, procurement and use of die form monolithic microwave integrated circuits (MMICs) for space applications. It applies to MMICs based on III‑V compound materials for RF use at frequencies ≥ 1 GHz and defines quality, design and procurement requirements for components delivered in die form. Packaged MMICs and discrete microwave parts are excluded (see ESCC 9010 / ESCC 5010). The standard originates from ECSS-Q-ST-60-12C and may be tailored per ECSS-S-ST-00 project rules.

Key topics and technical requirements

• Scope & applicability: Die-form MMICs for space RF systems (III‑V material technologies, ≥1 GHz).
• Design requirements: MMIC electrical specifications, thermal analysis, parasitic and transient simulation, design trade-offs, derating and robustness, layout optimization and DRC/ERC.
• Design reviews & deliverables: Architecture and schematic reviews, simulation and stability analyses, design documentation, MMIC summary design sheet and compliance matrix.
• Selection & responsibilities: Criteria for process selection (foundry vs catalogue), roles for customer and supplier, validation of process, design and application.
• Procurement & acceptance: Wafer screening, Wafer Acceptance Test (WAT), lot acceptance testing (LAT) flows, dies incoming testing (visual inspection, electrical characterization), packaging and deliverables.
• Test flows & failure handling: Defined test sequences (including user LAT sequences A–D), failure criteria, lot-failure rules and provisions for destructive physical analysis.
• Quality & normative references: Links to ECSS and ESCC documents, MIL‑STD‑883 referenced test methods; quality management and preservation standards cited.

Practical applications

• Ensures reliable selection and procurement of MMIC dies for spacecraft RF subsystems (transceivers, amplifiers, mixers, switches) where high reliability and traceability are required.
• Guides MMIC design teams on space-specific design verification, derating and robustness analyses.
• Defines acceptance testing and supplier control procedures for procurement engineers and QA managers procuring die-form MMICs for flight hardware.
• Useful for project tailoring when integrating MMICs into spacecraft in conformance with ECSS processes.

Who should use this standard

• Space systems engineers and RF/MMIC designers
• Procurement specialists and supplier quality/assurance teams
• Foundries and MMIC manufacturers producing die-form components for space
• Project managers implementing ECSS/space product assurance requirements

Related standards

• ECSS-Q-ST-60 series (space product assurance - EEE components)
• ECSS-Q-ST-60-05 (hybrids/process identification)
• ESCC 9010 / ESCC 5010 (packaged MMICs and discrete microwave components)
• MIL‑STD‑883 (microelectronics test methods)

Keywords: EN 16602-60-12:2014, MMIC die form, space product assurance, III‑V MMIC, wafer acceptance test, user LAT, MMIC procurement, RF components.

Standards Content (Sample)

SLOVENSKI STANDARD
01-januar-2015
=DJRWDYOMDQMHYDUQLKSURL]YRGRYYYHVROMVNLWHKQLNL6QRYDQMHL]ELUDQMHQDEDYDLQ
XSRUDEDPRQROLWQLKPLNURYDORYQLKLQWHJULUDQLKYH]LM00,&YREOLNLþLSRY
Space product assurance - Design, selection, procurement and use of die form
monolithic microwave integrated circuits (MMICs)
Raumfahrtproduktsicherung - Design, Auswahl, Beschaffung und Nutzung von MMIC
Assurance produit des projets spatiaux - Conception, sélection, approvisionnement et
utilisation de circuits intégrés monolithique hyperfréquence de forme die
Ta slovenski standard je istoveten z: EN 16602-60-12:2014
ICS:
31.200 Integrirana vezja, Integrated circuits.
mikroelektronika Microelectronics
49.140 Vesoljski sistemi in operacije Space systems and
operations
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

EUROPEAN STANDARD
EN 16602-60-12
NORME EUROPÉENNE
EUROPÄISCHE NORM
September 2014
ICS 49.140
English version
Space product assurance - Design, selection, procurement and
use of die form monolithic microwave integrated circuits
(MMICs)
Assurance produit des projets spatiaux - Conception, Raumfahrtproduktsicherung - Design, Auswahl,
sélection, approvisionnement et utilisation de circuits Beschaffung und Nutzung von MMIC
intégrés monolithique hyperfréquence de forme die
This European Standard was approved by CEN on 13 March 2014.

CEN and CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving
this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning
such national standards may be obtained on application to the CEN-CENELEC Management Centre or to any CEN and CENELEC
member.
This European Standard exists in three official versions (English, French, German). A version in any other language made by translation
under the responsibility of a CEN and CENELEC member into its own language and notified to the CEN-CENELEC Management Centre
has the same status as the official versions.

CEN and CENELEC members are the national standards bodies and national electrotechnical committees of Austria, Belgium, Bulgaria,
Croatia, Cyprus, Czech Republic, Denmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France, Germany, Greece,
Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Romania, Slovakia,
Slovenia, Spain, Sweden, Switzerland, Turkey and United Kingdom.

CEN-CENELEC Management Centre:
Avenue Marnix 17, B-1000 Brussels
© 2014 CEN/CENELEC All rights of exploitation in any form and by any means reserved Ref. No. EN 16602-60-12:2014 E
worldwide for CEN national Members and for CENELEC
Members.
Table of contents
Foreword . 6
Introduction . 7
1 Scope . 8
2 Normative references . 9
3 Terms, definitions and abbreviated terms . 10
3.1 Terms from other standards . 10
3.2 Terms specific to the present document . 10
3.3 Abbreviated terms. 12
4 General requirements. 14
4.1 Overview . 14
4.2 Flight model MMIC dies lots procurement . 14
4.3 Minimum quality requirements . 14
5 Selection . 15
5.1 General . 15
5.1.1 Overview . 15
5.1.2 Requirements . 15
5.2 Process selection. 16
5.3 Models, and design tools . 16
6 Responsibilities . 17
7 MMIC design . 18
7.1 Principles of MMIC design . 18
7.1.1 Overview . 18
7.1.2 General . 18
7.1.3 Number of design iterations . 18
7.1.4 Design trade-offs . 19
7.2 Design tasks . 19
7.2.1 Electrical design specification . 19
7.2.2 Design variations . 19
7.2.3 Parasitic effects . 19
7.2.4 Transient simulation . 20
7.2.5 Thermal analysis . 20
7.2.6 Sensitivity to temperature, process variation and supply voltages . 20
7.2.7 Design testability . 21
7.2.8 Design stability analysis . 21
7.2.9 Maximum rating and robustness . 21
7.2.10 Layout optimization . 22
7.2.11 DRC or ERC . 22
7.3 Design reviews . 23
7.3.1 General . 23
7.3.2 MMIC architecture . 23
7.3.3 Schematic . 23
7.3.4 Simulation results . 23
7.3.5 Sensitivity and stability analysis . 24
7.3.6 Derating . 24
7.3.7 Layout . 24
7.3.8 Tests matrix . 24
7.3.9 Assembly . 24
7.3.10 Compliance matrix . 25
7.3.11 MMIC detail specification . 25
7.3.12 Development plan . 25
7.3.13 Design documentation . 25
7.3.14 MMIC summary design sheet . 25
8 Application approval . 26
8.1 General . 26
8.2 Test flow and test procedures . 26
9 Procurement and LAT specification . 28
10 Procurement . 29
10.1 General . 29
10.1.1 Overview . 29
10.1.2 Methodology . 29
10.2 Wafer screening and WAT . 29
10.2.1 General . 29
10.2.2 Wafer screening and WAT flows . 29
10.2.3 Wafer manufacturing and control . 30
10.2.4 Wafer acceptance test . 31
10.2.5 Packaging . 32
10.2.6 Deliverables . 32
10.3 Dies incoming testing . 33
10.3.1 General . 33
10.3.2 Assembly test . 33
10.3.3 Visual inspection . 34
10.3.4 Electrical characterization . 34
10.4 User LAT procurement sequences . 35
10.4.1 General . 35
10.4.2 Sequence A: process, design and application validated . 38
10.4.3 Sequence B: process validated and new design or new application . 38
10.4.4 Sequence C: process, design and application not validated . 39
10.4.5 Sequence D: application approval testing . 40
10.4.6 Destructive physical analysis after user LAT . 40
10.5 Failure criteria and lot failure . 41
Annex A (normative) MMIC electrical design specification - DRD . 42
Annex B (normative) Compliance matrix for custom MMIC design - DRD . 43
Annex C (normative) Design package document - DRD . 44
Annex D (normative) MMIC summary design sheet - DRD . 46
Annex E (normative) MMIC procurement specification - DRD . 47
Annex F (normative) MMIC lot acceptance specification for user LAT -
DRD . 48
Annex G (normative) MMIC visual inspection summary sheet - DRD . 50
Annex H (informative) References . 51
Bibliography . 52

Figures
Figure 10-1: Wafer screening and WAT . 30
Figure 10-2: Dies or die incoming testing . 34
Figure 10-3: Acceptance flow for flight model die lots . 35
Figure 10-4: User LAT flow . 37

Tables
Table 6-1: Customer and supplier responsibilities for the “foundry” and “catalogue”
modes . 17
Table 8-1: CTA tests and procedures for testing in sequence D . 27

Foreword
This document (EN 16602-60-12:2014) has been prepared by Technical
Committee CEN/CLC/TC 5 “Space”, the secretariat of which is held by DIN.
This standard (EN 16602-60-12:2014) originates from ECSS-Q-ST-60-12C.
This European Standard shall be given the status of a national standard, either
by publication of an identical text or by endorsement, at the latest by March
2015, and conflicting national standards shall be withdrawn at the latest by
March 2015.
Attention is drawn to the possibility that some of the elements of this document
may be the subject of patent rights. CEN [and/or CENELEC] shall not be held
responsible for identifying any or all such patent rights.
This document has been prepared under a mandate given to CEN by the
European Commission and the European Free Trade Association.
This document has been developed to cover specifically space systems and has
therefore precedence over any EN covering the same scope but with a wider
domain of applicability (e.g. : aerospace).
According to the CEN-CENELEC Internal Regulations, the national standards
organizations of the following countries are bound to implement this European
Standard: Austria, Belgium, Bulgaria, Croatia, Cyprus, Czech Republic,
Denmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France,
Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania,
Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Romania,
Slovakia, Slovenia, Spain, Sweden, Switzerland, Turkey and the United
Kingdom.
Introduction
This Standard covers the design, selection, procurement and use of III-V
monolithic microwave integrated circuits (MMICs) for space equipment.
It defines the design activity for the technical (methodology, phases to be
followed) and quality (quality assurance, design review) aspects, and, the
selection and procurement rules for these components taking into account
whether or not the processes have been validated.
Scope
This Standard applies to all types of MMIC (monolithic microwave integrated
circuit) based on III-V compound materials for RF applications (i.e. frequency
range ≥ 1 GHz). The requirements for the procurement of components in die
form are defined.
It is not within the scope of this Standard to address packaged MMICs and
discrete microwave components, these are dealt with in the relevant ESCC
specification (ESCC 9010 and ESCC 5010).
This standard may be tailored for the specific characteristic and constraints of a
space project in conformance with ECSS-S-ST-00.

Normative references
The following normative documents contain provisions which, through
reference in this text, constitute provisions of this ECSS Standard. For dated
references, subsequent amendments to, or revisions of, any of these
publications do not apply. However, parties to agreements based on this ECSS
Standard are encouraged to investigate the possibility of applying the most
recent editions of the normative documents indicated below. For undated
references the latest edition of the publication referred to applies.

EN reference Reference in text Title
EN 16601-00-01 ECSS-S-ST-00-01 ECSS system— Glossary of terms
EN 16602-30-11 ECSS-Q-ST-30-11 Space product assurance — Derating -- EEE
components
EN 16602-60 ECSS-Q-ST-60 Space product assurance - Electrical, electronic and
electromechanical (EEE) components
EN 16602-60-05 ECSS-Q-ST-60-05 Space product assurance — Generic requirements for
hybrids
MIL-STD-883 Tests methods and procedures for microelectronics
ESCC 20600 Preservation, packaging and despatch of ESCC
electronic components
ESCC 24600 Minimum quality management system requirements
ESCC 2049010 Internal visual inspection of monolithic microwave
devices
ESCC 2439010 Requirements for capability approval of MMICs
ESCC 9010 Generic specification for MMICs
Terms, definitions and abbreviated terms
3.1 Terms from other standards
For the purpose of this document, the terms and definitions given in
ECSS-S-ST-00-01 apply.
For the purpose of this document, the following term from ECSS-Q-ST-60-05
applies:
process identification document
3.2 Terms specific to the present document
3.2.1 batch lot
wafers from the same basic raw materials processed as a single set in the
manufacturing sequence (diffusion, metallization and passivation process) in a
limited and controlled period of time
NOTE A unique identifier or code is assigned to a batch
lot and to each wafer for processing traceability
purposes.
3.2.2 design rules check
control procedure for verifying that design rules have been satisfied
NOTE 1 Design rules checks are generally issued by the
supplier.
NOTE 2 DRC is performed using software.
3.2.3 designer
organization responsible for the design of the MMICs
3.2.4 die lot
set of all dies coming from a single wafer lot
3.2.5 electrical rule check
control procedure for verifying that the electrical rules have been satisfied
NOTE Electrical rules are generally issued by the
manufacturer.
3.2.6 evaluated process
mature technology that has been successfully submitted to a set of electrical and
environmental testing to demonstrate performance and reliability limits
NOTE 1 ECSS-Q-ST-60-01 contains a list of evaluated
processes.
NOTE 2 The ESCC 2269010 specification defines the
requirements for the evaluation.
3.2.7 manufacturer
foundry responsible for the manufacturing of the MMICs
3.2.8 process control monitor
test vehicle used by the supplier to assess the stability of the manufacturing
process by means of controls conducted during a wafer production cycle
NOTE The PCM is repeated a number of times
(depending on the manufacturers) on each wafer
lot. The measurements taken during the PCM are
used to accept or reject the wafer according to the
relevant DC and RF criteria defined in the design
manual.
3.2.9 production lot
device types manufactured from the same basic raw materials on the same
production line, processed under the same manufacturing techniques and
controls using the same type of equipment
NOTE A production lot may be composed of one or many
batch lots.
3.2.10 qualified process
process that has been successfully submitted to a formal qualification testing
NOTE The ESCC 20100 specification defines the
requirements for the qualification.
3.2.11 reticule
group of circuit layouts (MMIC, TCV, DEC, PCM) defined by design at the
mask level, for duplication over the entire wafer during the MMIC
manufacturing
3.2.12 statistical process control
tool to control the quality and the stability of the technological process
NOTE SPC is implemented by measuring key parameters
during the different manufacturing steps and their
analysis using appropriate methods.
3.2.13 tile
See reticule
3.2.14 user
entity responsible for the integration of the MMICs at upper level
NOTE Example: MMICs are integrated by users into, for
example, modules, hybrids, piece of equipment.
3.2.15 validated design
design that is successfully submitted to application approval testing and an
MMIC user LAT test
3.2.16 validated process
process that is evaluated or qualified
3.2.17 wafer lot
wafers manufactured from one or more batch lots
NOTE Depending on the maturity of the process a wafer
lot is defined as follows:
• Case 1 (non-evaluated or qualified process): a
wafer lot is a single wafer.
• Case 2 (evaluated or qualified process and new
MMIC design): a wafer lot is one batch lot.
• Case 3 (mature process and recurrent MMIC
design): a wafer lot is considered to be a
production lot of 4 batches manufactured
within a 3 month period.
3.3 Abbreviated terms
For the purpose of this standard, the abbreviated terms of ECSS-S-ST-00-01 and
the following apply:
Abbreviation Meaning
acceptance quality level
AQL
circuit type approval
CTA
dynamic evaluation circuit
DEC
design rules check
DRC
electrical rule check
ERC
high-temperature reverse bias
HTRB
lot acceptance test
LAT
low-temperature reverse bias
LTRB
monolithic microwave integrated circuit
MMIC
part approval document
PAD
process control monitor
PCM
process identification document
PID
residual gas analysis
RGA
scanning acoustic microscopy
SAM
scanning electron microscope
SEM
single event upset
SEU
statistical process control
SPC
technological characterization vehicle
TCV
wafer acceptance testing
WAT
General requirements
4.1 Overview
This Clause defines the requirements for die MMIC procurement. It completes
the user LAT requirements for MMIC die lot procurement as defined in
ECSS-Q-ST-60-05.
The responsibilities of the participants (e.g. designer, manufacturer or end-user)
are given from the prototype phase to the delivery of the dies for flight model
hybrid manufacturing.
4.2 Flight model MMIC dies lots procurement
a. The following steps involved in procuring MMICs for Space applications
shall be followed:
1. Process selection, in conformance with clause 5.
2. Allocation of responsibilities, in conformance with clause 6.
3. MMIC design, in conformance with clause 7.
4. Application approval, in conformance with clause 8
5. Procurement and LAT specifications, in conformance with
clause 9.
6. Die form procurement sequences, in conformance with clause 10.
b. The requirements for the qualification and procurement of MMIC
packaged devices given in ESCC 9010 shall apply.
4.3 Minimum quality requirements
a. The requirements for processing, production control and clean room
conditions defined in ESCC 24600 shall apply.
b. The manufacturer shall implement and maintain a product quality
programme, to ensure that reliability and quality is maintained
throughout all the phases of manufacturing and testing in conformance
with the requirements in ECSS-Q-ST-60.
Selection
5.1 General
5.1.1 Overview
During the selection of the manufacturing process by the entity in charge of the
procurement, components are assessed for their conformance to the
requirements on reliability, application and environmental resistance as defined
for the project.
5.1.2 Requirements
a. The selection of a foundry shall take into account the maturity of the
technology, the validation status and the qualification domain as defined
in ESCC 2439010.
b. The MMIC design shall be analysed and validated in terms of application
domain compared to the qualification domain and space application
requirements.
NOTE The qualification domain is documented in terms
of the following boundaries with respect to any
potential failure mode identified on the process:
• The physical design and procedures that are
closely related to the manufacturing process (no
major process change identified since the
evaluation testing).
• The electrical design in term of extreme limits
(thermal, DC and RF parameters).
• Function (e.g. oscillator, gain block), and appli-
cation (e.g. small signal, pulsed, high drive).
• The performances, the reliability figures, and
the environmental resistance.
5.2 Process selection
a. The selection of the foundry, and the manufacturing process, shall be
justified by the supplier, and approved by the customer.
b. The agreement shall be based on the specific application for which the
MMIC is designed and on further considerations such as:
1. The maturity of the process.
NOTE E.g. large volume production or experimental
technology.
2. The adequacy of the application to the electrical foundry manual,
considering, as a minimum, the following items:
(a) Equivalent circuits based on measurement results for all
passive elements, including lumped and distributed
components, in a format compatible for use with standard
circuit simulators.
NOTE E.g. transmission lines and discontinuities.
(b) Small signal (at various bias points) and large signal models
of active components based on measurement results, in a
format compatible for use with standard circuit simulators.
NOTE Example of such components are transistors, but
also Schottky and varactor diodes.
(c) Availability of standard components
NOTE E.g. lange couplers.
(d) Layout libraries, in a format compatible for use with
standard circuit simulators.
(e) Thermal, reliability, process variation design parameters.
(f) Space evaluation or qualification status including the results
of reliability evaluations performed by the foundry.
c. A foundry manual for each process used, shall be delivered to the
customer (provided the current issue is not already available) prior to the
design phase.
d. The MMIC specifications (satisfying the overall equipment requirements)
shall be established within the technical limits of the MMIC process used,
and be finalised following an iterative process.
5.3 Models, and design tools
a. Only approved models (fully experimentally verified and included in the
foundry manual) and design tools shall be used to design all the passive
and active (linear and non-linear) elements.
b. Any non-standard models and design tools shall be justified, and
approved by the customer.
Responsibilities
There are two modes for developing and procuring MMICs:
• “Foundry” mode: the customer designs the MMIC and is entirely
responsible for the design, and the supplier (or manufacturer) only
guarantees the technology.
• “Catalogue” mode: the supplier designs the MMIC and is entirely
responsible for both the design and the technology, except for issues
related to incompatibility between the MMIC and the environment in the
customer application.
Table 6-1 summarizes the responsibilities of the supplier and the customer.
Table 6-1: Customer and supplier responsibilities for the “foundry” and
“catalogue” modes
Responsibility
Description Reference supplier customer
Process selection clause 5 X X
Design model validated and design tasks clause 7.2 X
conducted
Design reviews clause 7.3 X X
Procurement specification
- for MMIC chip procurement under clause 7.3.14 X
manufacturer and customer shared
responsibility
- for LAT under customer responsibility), clause 9 X
Application approval clauses 8and 10.4.5 X
Procurement activity including: clause 10
- wafer screening and WAT clause 10.2.4 X
- dies incoming control clause 10.3 X
- LAT clauses 10.4.2, 10.4.3 X
and 10.4.4
- DPA clause 10.4.6 X
- Failure analysis clause 10.5 X

MMIC design
7.1 Principles of MMIC design
7.1.1 Overview
In this Clause the steps in the design phases and the responsibilities of the
designer in the development of the prototype MMICs are defined.
This Clause does not apply to catalogue MMICs already designed for which the
supplier guarantees the microwave performances.
7.1.2 General
a. The synergies between the specific application for which the MMIC is
designed and other application areas shall be investigated for possible
utilization.
NOTE Example of other application areas are:
commercial, professional, and military
applications.
b. If the supplier is developing, or has already developed, for another
application, an MMIC having a similar functionality to that required by
the customer, this MMIC may be considered as a starting point for the
new design.
7.1.3 Number of design iterations
a. The decision to proceed with a second design and manufacturing
iteration (redesign) shall be made, for each MMIC, based on the
conformance of the electrical design specification and the electrical
measurements of the first iteration.
b. Additional iterations shall be carried out until sufficient margins can be
demonstrated.
NOTE A design iteration consists of circuit development,
simulation, fabrication and measurement.
7.1.4 Design trade-offs
a. A design trade-off shall be performed including, as a minimum, the
following:
1. circuit principles and heritage circuit topology and dependability;
2. gain and compression distribution inside the circuit;
3. overall electrical performance;
4. testability;
5. radiation;
6. assembly;
7. integration;
8. cost effectiveness of the packaging.
7.2 Design tasks
7.2.1 Electrical design specification
a. Prior to any design, the customer shall develop an electrical design
specification of the electrical performances for the application in
conformance with Annex A.
7.2.2 Design variations
a. Several design variations for circuit architecture shall be implemented
when the critical characteristics of the circuit are such that multiple
variations on a design iteration maximise the probability of first-pass
success.
b. The differences between the variations should be such that the
probability of success of at least one of the variations is maximized.
c. Test structures of the most sensitive and critical passive and active circuit
elements or sub-parts may be included in the design iteration to increase
the diagnostic capabilities.
7.2.3 Parasitic effects
a. Parasitic effects shall be considered in all the designs and simulated with
appropriate (e.g. electromagnetic) design tools.
NOTE Examples include the effect of transmission line
discontinuities (especially for unusual geometry
and for those elements having a very critical
influence on overall performance), on-die
coupling, interconnections (e.g. bonding wires,
external capacitors, impedance of interconnected
circuits), assembly, and packaging.
b. The simulation specified in requirement 7.2.3a may be complemented
with experimental data from circuits having a similar layout and
characteristics.
c. If the confidence in a selected structure or component simulation is not
sufficient, measures shall be taken to avoid this structure in the design,
whenever possible, or the design modified to reduce the criticality of this
structure.
7.2.4 Transient simulation
a. Transient simulations shall be made when circuits operate in pulse
conditions.
b. Simulated results shall be derived for parameters such as, turn on and off
times, variations versus pulse length and pulse repetition frequency.
c. Requirements 7.2.4a and 7.2.4b shall also be applied to oscillators for
determining, for example, the build up time.
7.2.5 Thermal analysis
a. The maximum channel (or junction) temperature shall be computed for
the maximum equipment base-plate temperature (operating temperature
range).
b. Measures shall be taken to minimise the temperature by selecting the
appropriate size or combination of active devices, their location on the
die, and the mounting techniques
NOTE E.g. eutectic attachment versus epoxy attachment.
c. The effects and characteristics of the packages on the circuits shall be
analysed.
NOTE E.g. power dissipation.
7.2.6 Sensitivity to temperature, process variation
and supply voltages
a. The sensitivity to temperature, process variation and supply voltages
shall be simulated using foundry data or measured data from test
components.
b. Yield analysis and estimates based on the design book data shall be
carried out to ensure that the circuit operates as specified in the
wafer-acceptance criteria (both RF and DC parameters), and that it can
withstand uncertainties such as, the accuracy of electrical model
parameters and variations.
NOTE This includes the choice of, for example, optimum
topologies, components, sizes, design centring,
worst-case analysis, yield analysis and yield
estimate.
c. The analysis shall be carried out for all parameters subjected to process
variations and include, whenever possible, correlations between the
different elements that cause variations.
d. When delivered by the foundry, SPC data should be used.
7.2.7 Design testability
a. Ground-source-ground pads with the standard pitch defined in the
design book, shall be included for all RF ports.
b. For specific cases, alternative pad arrangements (e.g. G-S or S+ S- pads)
may be used after justification is provided (for example, a significant area
reduction effect on the die).
c. DC pads should be positioned orthogonally to the RF pads.
d. For critical cases and at higher frequencies, an on-wafer calibration
standard can be inserted in the tile.
NOTE E.g. to remove uncertainties related to substrate
thickness variation.
7.2.8 Design stability analysis
a. Design stability analysis shall be carried out from the DC to the
maximum frequency of the active devices used.
b. The analysis specified in requirement 7.2.8a (e.g. using µ factor or both K
and B1 factors) shall be complemented by an internal multi-loop analysis
to exclude any possibility of oscillations of the odd-mode type.
c. For a cascaded structure, as a minimum, the stability of each block shall
be checked individually.
d. The analysis specified in requirement 7.2.8a shall also include the effect
of feedback paths caused by the following:
1. the biasing elements (on and off-die);
2. the final packaging;
3. the effects of process variations, temperature, and slight changes of
biasing conditions.
e. Circuit stability during on-wafer characterization shall be addressed.
7.2.9 Maximum rating and robustness
a. The designer shall apply and verify the maximum rating specified by the
manufacturer.
b. The designer shall apply the additional derating in conformance to
ECSS-Q-ST-30-11 or an equivalent customer specification as long as the
customer specification does not relax ECSS-Q-ST-30-11 requirements.
c. The maximum current densities and maximum voltages shall be
evaluated in the whole circuit both at DC and RF operating conditions.
NOTE E.g. multi-carrier signal.
d. The maximum level of stress under RF conditions in any device shall be
limited to conditions equivalent to those for which the process reliability
evaluation is carried out.
NOTE Example of these RF conditions are gain
compression, and effects of multi-carrier loading.
e. The circuit topology shall take into account the circuit reliability while
maintaining acceptable electrical characteristics.
NOTE Example of reliability conditions to take into
account are the use of L-parallel, C-series matching
networks at input to reduce sensitivity to static
discharge, and choice of transmission line size.
f. The effect of radiation shall be included (if applicable to the process
used).
g. Any new MMIC design shall be analysed with respect to the process
reliability figures compatible with the future application.
h. If the results of the analysis of the design and the application are out of
the qualified domain, the customer (or the supplier) shall define a quality
or reliability test plan for documenting the shortcomings.
7.2.10 Layout optimization
a. The die area shall be optimised to improve yield and reduce cost, without
compromising on the functional performance of the die and testability.
b. A hierarchical design should be used.
c. The circuit layout shall be delivered in GDSII format.
d. The number of available die sites per tile shall be specified, and the
layout of the complete tile shall be delivered (except PCM die).
e. The location and function of any connecting pads shall be specified and
numbered.
f. Testability considerations shall be taken into account.
g. Assembly drawing shall be complete and include all other components
additional to the MMIC.
NOTE E.g. filtering capacitors.
h. The packaging drawing (if applicable) shall be included.
7.2.11 DRC or ERC
a. The successful output of the design rules checking (DRC) performed at
the foundry shall be demonstrated to show conformance with the
foundry layout rules (e.g. no errors detected).
b. The successful output of the electrical rules checking (ERC) performed at
the foundry (if performed) shall be demonstrated to show conformance
with the foundry electrical rules
NOTE E.g. no errors detected.
c. For all the points not covered by requirements 7.2.11a and 7.2.11b, the
supplier shall demonstrate that the design is made within a domain for
which the selected process is fully proven.
NOTE E.g. frequency range of applicability of models,
biasing ranges.
7.3 Design reviews
7.3.1 General
a. Design and layout review meetings shall be held between the supplier
and customer.
b. The supplier shall manage the participation of persons involved in the
design and manufacturing.
c. When the design is completed, the designer shall send the file to the
manufacturer for assembly of the final reticule and performance of the
DRC.
d. The design review shall be organized by the supplier at the manufacturer
facilities with persons involved in the design and manufacturing to
assess whether the circuits are ready for manufacturing.
e. In the design review meeting, the requirements in clauses 7.3.2 to 7.3.14
shall be addressed in the given order.
7.3.2 MMIC architecture
a. The designer shall provide a description of the function(s) and their
features.
b. The manufacturer shall verify that the characteristics are realistic with
regard to the domain of the process.
7.3.3 Schematic
a. The designer shall present the electrical scheme of the circuits.
7.3.4 Simulation results
a. The designer shall state the software or hardware type used for the
design.
b. The designer shall provide the simulation results demonstrating that the
circuit belongs to the functionality domain specified and that the MMIC
was designed using, for example, models and cells, specified in the
design manual.
c. Any discrepancy or modification in, for example, the models and cells,
shall be clearly identified, and justification and documentation supplied.
d. The designer shall demonstrate that the electrical models used in the
simulations are valid for the specified application domain, including the
worst case analyses.
7.3.5 Sensitivity and stability analysis
a. The designer shall provide the results of the sensitivity analysis.
b. Variations in the manufacturing process shall be taken into account in the
design.
c. Variations in the environment shall be taken into account by the supplier
who shall manage the impact.
NOTE For example to forward the sensitivity and
stability data to the user.
7.3.6 Derating
a. The designer shall provide the derating for each passive or active
element, calculated from the manufacturer maximum rating.
b. The derating analysis shall be performed for the worst case of use
scenario and conform to the requirements of the ECSS-Q-ST-30-11.
7.3.7 Layout
a. The manufacturer shall provide the DRC and ERC results.
b. If no software is available, the ERC shall be made “manually” on a
large-scale drawing with the following:
1. highlight the connection nodes;
2. surround the basic cells;
3. mark the DC and RF paths;
4. measurement of the track dimensions and compare them to the
design rules (current density).
c. For the manual ERC, the designer shall provide, for the review and for
each circuit, a schematic of the electrical connections.
7.3.8 Tests matrix
a. The testing matrix, to be performed by the manufacturer at wafer level or
at individual die level, shall be provided by the designer.
b. The manufacturer shall ensure that he has adequate test facilities to
perform the tests.
7.3.9 Assembly
a. The designer shall specify the mounting technique for assembling the
MMICs.
b. The supplier shall verify that the MMIC process is compatible with the
intended mounting technique.
7.3.10 Compliance matrix
a. The supplier shall issue a compliance matrix for custom MMIC designs
(check-list) in conformance with Annex B, based on manufacturer and
designer data.
b. The compliance matrix for custom MMIC design shall be available for
customer review.
7.3.11 MMIC detail specification
a. The designer shall provide the preliminary MMIC detail specification of
the circuit based on ESCC format (or equivalent).
7.3.12 Development plan
a. The development plan of the circuit(s) defining the planning of
manufactu
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