EN 16603-20-40:2023
(Main)Space engineering - ASIC, FPGA and IP Core engineering
Space engineering - ASIC, FPGA and IP Core engineering
This activity w ill be the parallel development of EN 16603-20-40 and ECSS-E-ST-20-40C.
The scope shall cover the areas of existing ASIC and FPGA engineering chapter 5 of ECSS-Q-ST-60-02C, but w ith w ider breadth and greater depth, covering engineering requirements of end-to-end development flow s, from specification of requirements to validation of prototypes, of the follow ing monolithic devices for its use in space:
• ASICs (distinguishing digital, analogue and mixed-signal development flow s)
• FPGAs (distinguishing three technology families: SRAM, FLASH and anti-fuse technologies)
• ASIC and FPGA System-on-Chip embedding processor cores w hich have external “softw are programme” dependencies to be addressed during the SoC development, resulting in SW-HW co-design requirements.
Raumfahrttechnik - ASIC, FPGA und IP-Kern Entwicklung
Ingénierie spatiale - Ingénierie des ASIC, FPGA et noyaux de PI
Vesoljska tehnika - Inženiring ASIC, FPGA in jedra IP
Ta standard določa izčrpen sklop zahtev za inženiring za uspešen razvoj digitalnih, analognih in mešanih analogno-digitalnih prilagojeno oblikovanih integriranih vezij, kot so aplikacijsko specifična vezja (ASIC), terensko programirljiva logična vezja (FPGA) in jedra intelektualne lastnine (jedra IP), v nadaljevanju poimenovani z enim in splošnim
izrazom NAPRAVA.
Mikroelektronski sistemi, ki jih sestavlja več kot en čip NAPRAVE, vendar so med seboj povezani in združeni kot ena NAPRAVA, se ne štejejo kot ena monolitna NAPRAVA. Vendar pa se standard ECSS-ST-20-40 uporablja za (a) razvoj vsakega posameznega monolitnega čipa, (b) tudi za njihovo integracijo v eno NAPRAVO z več čipi, pri čemer so ti čipi jedra intelektualne lastnine.
Ta standard se lahko prilagodi posameznim lastnostim in omejitvam vesoljskega projekta v skladu s standardom ECSS-S-ST-00. Predhodno prilagajanje na podlagi dejanske vrste NAPRAVE in kritične kategorije NAPRAVE je obravnavno v točki 5.1.2.
Ta standard ne zajema zahtev za izbiro, nadzor, nabavo in uporabo NAPRAV za vesoljske projekte ali zahtev za kvalifikacijo po standardu ESCC za NAPRAVE, saj so te zahteve zajete v standardu o električnih, elektronskih in elektromehanskih komponentah ECSS-Q-ST-60C oziroma splošni specifikaciji št. 9000 sistema ESCC.
Vseeno pa ta standard obravnava možnost, da se za NAPRAVO izvede kvalifikacija po sistemu ECSS potem, ko je stranka NAPRAVO sprejela kot NAPRAVO s kvalifikacijo po sistemu ECSS, s tem pa so podrobna specifikacija NAPRAVE po sistemu ESCC in načrt in poročilo o preskusu sevanja NAPRAVE izbirni pričakovani rezultati.
General Information
Standards Content (Sample)
SLOVENSKI STANDARD
01-februar-2024
Vesoljska tehnika - Inženiring ASIC, FPGA in jedra IP
Space engineering - ASIC, FPGA and IP Core engineering
Raumfahrttechnik - ASIC und FPGA Technik
Ingénierie spatiale - Ingénierie des ASIC, FPGA et noyaux de PI
Ta slovenski standard je istoveten z: EN 16603-20-40:2023
ICS:
49.140 Vesoljski sistemi in operacije Space systems and
operations
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.
EUROPEAN STANDARD EN 16603-20-40
NORME EUROPÉENNE
EUROPÄISCHE NORM
December 2023
ICS 49.140
English version
Space engineering - ASIC, FPGA and IP Core engineering
Ingénierie spatiale - Ingénierie des ASIC, FPGA et Raumfahrttechnik - Entwicklung von ASICs, FPGAs und
noyaux de PI IP-Kernen
This European Standard was approved by CEN on 3 December 2023.
CEN and CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for
giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical
references concerning such national standards may be obtained on application to the CEN-CENELEC Management Centre or to
any CEN and CENELEC member.
This European Standard exists in three official versions (English, French, German). A version in any other language made by
translation under the responsibility of a CEN and CENELEC member into its own language and notified to the CEN-CENELEC
Management Centre has the same status as the official versions.
CEN and CENELEC members are the national standards bodies and national electrotechnical committees of Austria, Belgium,
Bulgaria, Croatia, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy,
Latvia, Lithuania, Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Republic of North Macedonia, Romania, Serbia,
Slovakia, Slovenia, Spain, Sweden, Switzerland, Türkiye and United Kingdom.
CEN-CENELEC Management Centre:
Rue de la Science 23, B-1040 Brussels
© 2023 CEN/CENELEC All rights of exploitation in any form and by any means
Ref. No. EN 16603-20-40:2023 E
reserved worldwide for CEN national Members and for
CENELEC Members.
Table of contents
European Foreword .6
Introduction .7
1 Scope .8
2 Normative references .9
3 Terms, definitions and abbreviated terms . 10
3.1 Terms from other standards .10
3.2 Terms specific to the present standard .10
3.3 Abbreviated terms .17
3.4 Conventions .19
3.4.1 Names of DEVICE development phases and reviews . 19
3.4.2 Companies involved in the DEVICE development . 20
3.4.3 Types of DEVICEs and requirements tailoring tag notation . 20
3.5 Nomenclature .21
4 Principles . 22
4.1 DEVICE development .22
4.2 Verification methods .22
5 DEVICE engineering . 23
5.1 General requirements .23
5.1.1 Overview .23
5.1.2 Tailoring according to DEVICE type and DEVICE criticality . 23
5.1.3 DEVICE engineering development flow . 23
5.1.4 Phase Reviews .25
5.1.5 DEVICE Verification Control Document . 25
5.2 DEVICE Definition Phase .27
5.2.1 Overview .27
5.2.2 DEVICE Requirements Specification .27
5.2.3 DEVICE Development Plan .27
5.2.4 Preliminary Verification and Validation Plans . 28
5.2.5 Preliminary DEVICE Support and Maintenance Plan . 28
5.2.6 Feasibility and Risk Assessment .28
5.2.7 DEVICE Definition Phase Review .29
5.3 DEVICE Architecture Definition Phase .29
5.3.1 Overview .29
5.3.2 Architecture Definition .29
5.3.3 Updated DEVICE Verification and Validation Plans . 30
5.3.4 DEVICE Architecture Definition Phase Review. 30
5.4 DEVICE Design and Verification Phase .30
5.4.1 Overview .30
5.4.2 DEVICE Verification Plan .31
5.4.3 DEVICE Design and Verification .31
5.4.4 DEVICE Database .32
5.4.5 Preliminary DEVICE Data Sheet .33
5.4.6 DEVICE Design and Verification Phase Review . 33
5.5 DEVICE Detailed Design Phase .34
5.5.1 Overview .34
5.5.2 Netlist Generation .34
5.5.3 Netlist verification .36
5.5.4 DEVICE Data Sheet update .36
5.5.5 DEVICE Database update .36
5.5.6 DEVICE Detailed Design Phase Review . 37
5.6 DEVICE Layout Phase . 37
5.6.1 Overview .37
5.6.2 Layout generation .37
5.6.3 Layout verification .39
5.6.4 DEVICE Validation Plan .39
5.6.5 DEVICE Database update .39
5.6.6 DEVICE Data Sheet update .39
5.6.7 Preliminary ESCC Detail Specification . 39
5.6.8 DEVICE Layout Phase Review . 40
5.7 DEVICE Implementation Phase .40
5.7.1 Overview .40
5.7.2 Production and test .41
5.7.3 DEVICE Database update .41
5.7.4 DEVICE Validation Plan completion .42
5.7.5 DEVICE Implementation Phase Review . 42
5.8 DEVICE Validation, Qualification and Acceptance Phase . 42
5.8.1 Overview .42
5.8.2 DEVICE validation .43
5.8.3 DEVICE Support and Maintenance .43
5.8.4 Experience Summary Report .43
5.8.5 Final versions of application and procurement documents . 44
5.8.6 DEVICE Validation, Qualification and Acceptance Phase Review . 44
6 Pre-tailoring according to DEVICE criticality and type . 46
6.1 DEVICE criticality categories .46
6.2 Pre-tailoring Matrix .49
Annex A (normative) DEVICE Requirements Specification (DRS) - DRD . 93
Annex B (normative) DEVICE Development Plan (DDP) - DRD. 98
Annex C (normative) DEVICE Verification Plan (DVeP) - DRD . 101
Annex D (normative) DEVICE Validation Plan (DVaP) - DRD . 106
Annex E (normative) DEVICE Support and Maintenance Plan (DSMP) -
DRD . 108
Annex F (normative) DEVICE Feasibility and Risk Assessment Report
(DFRAR) - DRD. 110
Annex G (normative) DEVICE Architecture Definition Report (DADR) - DRD. 114
Annex H (normative) DEVICE Data Sheet (DDS) - DRD . 117
Annex I (normative) Experience Summary Report - DRD . 119
Annex J (informative) Generic Development Flow Variations . 120
Annex K (informative) DEVICE Development Expected Outputs . 126
Annex L (informative) Equivalence of phase and milestone terminology of
ECSS-M-ST-10 and ECSS-E-ST-20-40 . 134
Bibliography . 139
Figures
Figure 5-1: DEVICE development flow (generic case) .26
: Example of DEVICE development flow with intermediate additional reviews . 121
: Example of DEVICE development flow variation with two DEVICE modules
developed and reviewed in parallel . 122
: Example of DEVICE development flow variation where three phases have
been merged .124
: Example of DEVICE development flow where three phases are iterated . 125
Tables
Table 6-1: DEVICE criticality categories .47
Table 6-2: Pre-tailoring Matrix .50
Table K-1 : Summary of expected outputs of engineering flow . 126
Table K-2 : ECSS-E-ST-20-40 and ECSS-Q-ST-60-03 list of expected document
outputs .128
Table L-1 : Equivalence of phase and milestone terminology of ECSS-M-ST-10 and
ECSS-E-ST-20-40 . 135
European Foreword
This document (EN 16603-20-40:2023) has been prepared by Technical
Committee CEN-CENELEC/TC 5 “Space”, the secretariat of which is held by
DIN.
This standard (EN 16603-20-40:2023) originates from ECSS-E-ST-20-40C.
This European Standard shall be given the status of a national standard, either by
publication of an identical text or by endorsement, at the latest by June 2024, and
conflicting national standards shall be withdrawn at the latest by June 2024.
Attention is drawn to the possibility that some of the elements of this document
may be the subject of patent rights. CEN [and/or CENELEC] shall not be held
responsible for identifying a
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