Space engineering - ASIC, FPGA and IP Core engineering

This activity w ill be the parallel development of EN 16603-20-40 and ECSS-E-ST-20-40C.
The scope shall cover the areas of existing ASIC and FPGA engineering chapter 5 of ECSS-Q-ST-60-02C, but w ith w ider breadth and greater depth, covering engineering requirements of end-to-end development flow s, from specification of requirements to validation of prototypes, of the follow ing monolithic devices for its use in space:
• ASICs (distinguishing digital, analogue and mixed-signal development flow s)
• FPGAs (distinguishing three technology families: SRAM, FLASH and anti-fuse technologies)
• ASIC and FPGA System-on-Chip embedding processor cores w hich have external “softw are programme” dependencies to be addressed during the SoC development, resulting in SW-HW co-design requirements.

Raumfahrttechnik - ASIC, FPGA und IP-Kern Entwicklung

Ingénierie spatiale - Ingénierie des ASIC, FPGA et noyaux de PI

Vesoljska tehnika - Inženiring ASIC, FPGA in jedra IP

General Information

Publication Date
Technical Committee
Current Stage
6060 - Definitive text made available (DAV) - Publishing
Start Date
Due Date
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Standards Content (Sample)

SIST EN 16603-20-40:2024
Vesoljska tehnika - Inženiring ASIC, FPGA in jedra IP
Space engineering - ASIC, FPGA and IP Core engineering
Raumfahrttechnik - ASIC und FPGA Technik
Ingénierie spatiale - Ingénierie des ASIC, FPGA et noyaux de PI
Ta slovenski standard je istoveten z: EN 16603-20-40:2023
49.140 Vesoljski sistemi in operacije Space systems and
SIST EN 16603-20-40:2024 en,fr,de
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

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SIST EN 16603-20-40:2024

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SIST EN 16603-20-40:2024



December 2023
ICS 49.140

English version

Space engineering - ASIC, FPGA and IP Core engineering
Ingénierie spatiale - Ingénierie des ASIC, FPGA et Raumfahrttechnik - Entwicklung von ASICs, FPGAs und
noyaux de PI IP-Kernen
This European Standard was approved by CEN on 3 December 2023.

CEN and CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for
giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical
references concerning such national standards may be obtained on application to the CEN-CENELEC Management Centre or to
any CEN and CENELEC member.

This European Standard exists in three official versions (English, French, German). A version in any other language made by
translation under the responsibility of a CEN and CENELEC member into its own language and notified to the CEN-CENELEC
Management Centre has the same status as the official versions.

CEN and CENELEC members are the national standards bodies and national electrotechnical committees of Austria, Belgium,
Bulgaria, Croatia, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy,
Latvia, Lithuania, Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Republic of North Macedonia, Romania, Serbia,
Slovakia, Slovenia, Spain, Sweden, Switzerland, Türkiye and United Kingdom.

CEN-CENELEC Management Centre:
Rue de la Science 23, B-1040 Brussels
© 2023 CEN/CENELEC All rights of exploitation in any form and by any means
Ref. No. EN 16603-20-40:2023 E
reserved worldwide for CEN national Members and for
CENELEC Members.

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SIST EN 16603-20-40:2024
EN 16603-20-40:2023 (E)
Table of contents
European Foreword .6
Introduction .7
1 Scope .8
2 Normative references .9
3 Terms, definitions and abbreviated terms . 10
3.1 Terms from other standards .10
3.2 Terms specific to the present standard .10
3.3 Abbreviated terms .17
3.4 Conventions .19
3.4.1 Names of DEVICE development phases and reviews . 19
3.4.2 Companies involved in the DEVICE development . 20
3.4.3 Types of DEVICEs and requirements tailoring tag notation . 20
3.5 Nomenclature .21
4 Principles . 22
4.1 DEVICE development .22
4.2 Verification methods .22
5 DEVICE engineering . 23
5.1 General requirements .23
5.1.1 Overview .23
5.1.2 Tailoring according to DEVICE type and DEVICE criticality .

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