EN IEC 63378-6:2026

Thermal standardization on semiconductor packages - Part 6: Thermal resistance and capacitance model for transient temperature prediction at junction and measurement points

IEC 63378-6:2026 specifies a thermal resistance and capacitance model for semiconductor packages. This model is named the digital transformation using thermal resistance and capacitance (DXRC) model. It predicts transient temperature at junction and measurement points. This document applies to semiconductor packages such as TO-252, TO-263, and HSOP. It supports single chip packages dissipated heat from single package surface.

Thermische Normung an Halbleitergehäusen - Teil 6: Wärmewiderstandsmodell für die Vorhersage der vorübergehenden Temperatur an Sperrschicht- und Messpunkten

Normalisation thermique des boîtiers de semiconducteurs - Partie 6: Modèle de résistance thermique et de capacité pour la prédiction de la température transitoire aux points de jonction et de mesure

L’IEC 63378-6:2026 spécifie un modèle de résistance thermique et de capacité pour les boîtiers de semiconducteurs. Ce modèle est appelé transformation numérique utilisant le modèle de résistance et de capacité thermiques (DXRC, Digital transformation using thermal resistance and capacitance). Il prédit la température transitoire aux points de jonction et de mesure. Le présent document s’applique aux boîtiers de semiconducteurs tels que TO-252, TO-263 et HSOP. Il prend en charge les boîtiers monopuces dissipant la chaleur d’une seule surface du boîtier.

Standardizacija toplotnih lastnosti pri polprevodniških ohišjih - 6. del: Model toplotne upornosti in kapacitivnosti za napoved prehodne temperature na spojih in merilnih točkah (IEC 63378-6:2026)

IEC 63378-6:2026 določa model toplotne upornosti in kapacitivnosti za polprevodniške ohišja. Ta model je imenovan model digitalne transformacije z uporabo toplotne upornosti in kapacitivnosti (DXRC). Napoveduje prehodno temperaturo na spoju in merilnih točkah.
Ta dokument se uporablja za polprevodniška ohišja, kot so TO-252, TO-263 in HSOP. Podpira enojna čip ohišja, ki odvajajo toploto z ene površine ohišja.

General Information

• Status: Published
• Publication Date: 19-Mar-2026
• ICS: 31.080.01 - Semiconductor devices in general
• Technical Committee: CLC/TC 47X - Semiconductor devices and trusted chips
• Current Stage: 6060 - Document made available - Publishing
• Start Date: 20-Mar-2026
• Due Date: 13-Feb-2026
• Completion Date: 20-Mar-2026
• Ref Project: SIST EN IEC 63378-6:2026 - Thermal standardization on semiconductor packages - Part 6: Thermal resistance and capacitance model for transient temperature prediction at junction and measurement points (IEC 63378-6:2026)

Overview

EN IEC 63378-6:2026 - "Thermal standardization on semiconductor packages - Part 6: Thermal resistance and capacitance model for transient temperature prediction at junction and measurement points" - establishes a standardized methodology for assessing and modeling the thermal performance of semiconductor packages. Developed by CLC and based on international consensus through the IEC and CENELEC, this standard defines a digital transformation using thermal resistance and capacitance (DXRC) model. Its primary purpose is to facilitate accurate transient temperature prediction, specifically targeting the junction and various measurement points of single-chip semiconductor packages such as TO-252, TO-263, and HSOP.

With the increasing complexity and thermal demands of modern electronics, understanding and predicting heat flow within semiconductor packages is vital to device reliability and performance. This standard provides critical guidance for manufacturers, designers, and testing laboratories to achieve reliable, repeatable, and comparable thermal assessments across the industry.

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Key Topics

• DXRC Model Definition

  • Specification of a compact, digital thermal model based on resistance and capacitance (RC) elements.
  • Structural layout involving a Near Junction Area (NJA-RC) and Measurement Points Area (MPA-RC).
  • Guidance on calculating and optimizing RC values for accurate temperature prediction.

• Transient Temperature Prediction

  • Procedures and requirements for modeling transient heat dissipation from the semiconductor junction to measurement points under various operational conditions.
  • Enables prediction of temperature rise at critical locations over time.

• Thermal Measurement Points

  • Identification and modeling of key external and internal package points for measurement, supporting more detailed system-level thermal analysis.

• Support for Common Package Types

  • Applicability to widely-used single-chip semiconductor packages, including TO-252, TO-263, and HSOP.

• Model Validation and Optimization

  • Coverage of methods for validating the DXRC model’s accuracy, including example workflows for model optimization and error minimization.

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Applications

Implementing EN IEC 63378-6:2026 offers tangible benefits throughout the semiconductor development process, including design, simulation, testing, and system integration:

• Thermal Design and Simulation

  • Enables electronics engineers to create more accurate thermal simulations, supporting design choices that enhance device reliability and longevity.
  • Reduces development time and cost by providing a standardized basis for compact thermal models used in CFD and other simulation tools.

• Product Validation and Reliability

  • Facilitates consistent thermal performance measurement and reporting required for quality assurance and compliance.
  • Enhances the ability to predict failure mechanisms related to heat, supporting robust product designs.

• Component Comparison

  • Offers a uniform metric for comparing the thermal characteristics of various package types and implementations, aiding procurement and qualification decisions.

• Industry Communication

  • Promotes common understanding and language for specifying thermal parameters between manufacturers, customers, and certification bodies.

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Related Standards

Understanding and applying EN IEC 63378-6:2026 is enhanced by reference to related guidance and standards:

• IEC 63378 Series
  • Other parts of the IEC 63378 series provide model creation methods (using datasheets and measurement data) and extended techniques for thermal analysis of semiconductor packages.
• IEC 60050-521: International Electrotechnical Vocabulary – Terms and definitions relevant to thermal resistance and thermal capacitance.
• JESD51 Series (from JEDEC): Test methods and definitions for thermal characterization of semiconductor devices.
• ISO/IEC Directives: Frameworks governing the drafting and development of international standards, ensuring harmonization and broad applicability.

---

Adopting EN IEC 63378-6:2026 helps the electronics industry achieve consistent, high-quality thermal modeling and measurement, ultimately leading to more reliable and safer semiconductor products. This standard is essential for organizations seeking efficient digital transformation in thermal management of electronic devices.

Standards Content (Sample)

SLOVENSKI STANDARD
01-maj-2026
Standardizacija toplotnih lastnosti pri polprevodniških ohišjih - 6. del: Model
toplotne upornosti in kapacitivnosti za napoved prehodne temperature na spojih
in merilnih točkah (IEC 63378-6:2026)
Thermal standardization on semiconductor packages - Part 6: Thermal resistance and
capacitance model for transient temperature prediction at junction and measurement
points (IEC 63378-6:2026)
Thermische Normung an Halbleitergehäusen - Teil 6: Wärmewiderstandsmodell für die
Vorhersage der vorübergehenden Temperatur an Sperrschicht- und Messpunkten (IEC
63378-6:2026)
Normalisation thermique des boîtiers de semiconducteurs - Partie 6: Modèle de
résistance thermique et de capacité pour la prédiction de la température transitoire aux
points de jonction et de mesure (IEC 63378-6:2026)
Ta slovenski standard je istoveten z: EN IEC 63378-6:2026
ICS:
31.080.01 Polprevodniški elementi Semiconductor devices in
(naprave) na splošno general
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

EUROPEAN STANDARD EN IEC 63378-6

NORME EUROPÉENNE
EUROPÄISCHE NORM March 2026
ICS 31.080.01
English Version
Thermal standardization on semiconductor packages - Part 6:
Thermal resistance and capacitance model for transient
temperature prediction at junction and measurement points
(IEC 63378-6:2026)
Normalisation thermique des boîtiers de semiconducteurs - Thermische Normung an Halbleitergehäusen - Teil 6:
Partie 6: Modèle de résistance thermique et de capacité Wärmewiderstandsmodell für die Vorhersage der
pour la prédiction de la température transitoire aux points vorübergehenden Temperatur an Sperrschicht- und
de jonction et de mesure Messpunkten
(IEC 63378-6:2026) (IEC 63378-6:2026)
This European Standard was approved by CENELEC on 2026-03-11. CENELEC members are bound to comply with the CEN/CENELEC
Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration.
Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the CEN-CENELEC
Management Centre or to any CENELEC member.
This European Standard exists in three official versions (English, French, German). A version in any other language made by translation
under the responsibility of a CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the
same status as the official versions.
CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, the Czech Republic,
Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the
Netherlands, Norway, Poland, Portugal, Republic of North Macedonia, Romania, Serbia, Slovakia, Slovenia, Spain, Sweden, Switzerland,
Türkiye and the United Kingdom.

European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung
CEN-CENELEC Management Centre: Rue de la Science 23, B-1040 Brussels
© 2026 CENELEC All rights of exploitation in any form and by any means reserved worldwide for CENELEC Members.
Ref. No. EN IEC 63378-6:2026 E

European foreword
The text of document 47D/991/CDV, future edition 1 of IEC 63378-6, prepared by SC 47D
"Semiconductor devices packaging" of IEC/TC 47 "Semiconductor devices" was submitted to the IEC-
CENELEC parallel vote and approved by CENELEC as EN IEC 63378-6:2026.
The following dates are fixed:
• latest date by which the document has to be implemented at national (dop) 2027-03-31
level by publication of an identical national standard or by endorsement
• latest date by which the national standards conflicting with the (dow) 2029-03-31
document have to be withdrawn
Attention is drawn to the possibility that some of the elements of this document may be the subject of
patent rights. CENELEC shall not be held responsible for identifying any or all such patent rights.
Any feedback and questions on this document should be directed to the users’ national committee. A
complete listing of these bodies can be found on the CENELEC website.
Endorsement notice
The text of the International Standard IEC 63378-6:2026 was approved by CENELEC as a European
Standard without any modification.

IEC 63378-6 ®
Edition 1.0 2026-02
INTERNATIONAL
STANDARD
Thermal standardization on semiconductor packages -
Part 6: Thermal resistance and capacitance model for transient temperature
prediction at junction and measurement points
ICS 31.080.01  ISBN 978-2-8327-1001-2

IEC 63378-6:2026-02(en)
IEC 63378-6:2026 © IEC 2026
CONTENTS
FOREWORD . 3
INTRODUCTION . 5
1 Scope . 6
2 Normative references . 6
3 Terms and definitions . 6
4 Definition of DXRC. 6
4.1 General . 6
4.2 Thermal resistance and capacitance (RC) topology of DXRC . 7
4.2.1 Thermal RC topology of DXRC . 7
4.2.2 Outline of DXRC . 8
4.2.3 RC values on NJA-RC . 8
4.2.4 RC values on MPA-RC . 8
Annex A (informative) Accuracy verification of DXRC model for TO-252 . 10
A.1 General . 10
A.2 CFD model. 10
A.3 Calculation of thermal RC values. 12
A.4 MPA-RC and DXRC model outline . 13
A.5 Optimization of RC values in MPA-RC . 13
A.6 Result. 15
Annex B (informative) Accuracy verification of DXRC model for TO-263 . 16
B.1 General . 16
B.2 CFD model. 16
B.3 Calculation of thermal RC values. 18
B.4 MPA-RC and DXRC model outline . 19
B.5 Optimization of RC values in MPA-RC . 19
B.6 Result. 20
Annex C (informative) Accuracy verification of DXRC model for HSOP . 21
C.1 General . 21
C.2 CFD model. 21
C.3 Calculation of thermal RC values. 23
C.4 MPA-RC and DXRC model outline . 24
C.5 Optimization of RC values in MPA-RC . 24
C.6 Result. 25
Annex D (informative) The effect of PCB layers . 26
D.1 General . 26
D.2 Verification method . 26
D.3 Result. 26
Bibliography . 28

Figure 1 – Thermal RC topology of DXRC . 7
Figure 2 – Outline of DXRC . 8
Figure A.1 – CFD model for TO-252 . 10
Figure A.2 – Size of TO-252 package . 11
Figure A.3 – Structure function . 12
IEC 63378-6:2026 © IEC 2026
Figure A.4 – Result of verification . 15
Figure B.1 – CFD model for TO-263 . 16
Figure B.2 – Size of TO-263 package . 17
Figure B.3 – Structure function . 18
Figure B.4 – Result of verification . 20
Figure C.1 – CFD model for HSOP . 21
Figure C.2 – Size of HSOP package . 22
Figure C.3 – Structure function . 23
Figure C.4 – Result of verification . 25
Figure D.1 – Comparisons of temperature rise between the detailed model and the
DXRC model . 27

Table A.1 – Material attributes . 11
Table A.2 – Thermal resistances in NJA-RC . 12
Table A.3 – Thermal capacitances in NJA-RC . 13
Table A.4 – Input variables . 14
Table A.5 – Optimized RC values . 14
Table B.1 – Material attributes . 17
Table B.2 – Thermal resistances in NJA-RC . 18
Table B.3 – Thermal capacitances in NJA-RC . 19
Table B.4 – Optimized RC values . 20
Table C.1 – Material Attributes . 22
Table C.2 – Thermal resistances in NJA-RC . 23
Table C.3 – Thermal capacitances in NJA-RC . 24
Table C.4 – Optimized RC values . 25
Table D.1 – Combination of the coverages of copper layers . 26

IEC 63378-6:2026 © IEC 2026
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
Thermal standardization on semiconductor packages -
Part 6: Thermal resistance and capacitance model for transient
temperature prediction at junction and measurement points

FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international
co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and
in addition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports,
Publicly Available Specifications (PAS) and Guides (hereafter referred to as “IEC Publication(s)”). Their
preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with
may participate in this preparatory work. International, governmental and non-governmental organizations liaising
with the IEC also participate in this preparation. IEC collaborates closely with the International Organization for
Standardization (ISO) in accordance with conditions determined by agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence between
any IEC Publication and the corresponding national or regional publication shall be clearly indicated in the latter.
5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity
assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any
services carried out by independent certification bodies.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and
expenses arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC
Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) IEC draws attention to the possibility that the implementation of this document may involve the use of (a)
patent(s). IEC takes no position concerning the evidence, validity or applicability of any claimed patent rights in
respect thereof. As of the date of publication of this document, IEC had not received notice of (a) patent(s), which
may be required to implement this document. However, implementers are cautioned that this may not represent
the latest information, which may be obtained from the patent database available at https://patents.iec.ch. IEC
shall not be held responsible for identifying any or all such patent rights.
IEC 63378-6 has been prepared by subcommittee 47D: Semiconductor devices packaging, of
IEC Technical Committee 47: Semiconductor devices. It is an International Standard.
The text of this International Standard is based on the following documents:
Draft Report on voting
47D/991/CDV 47D/998/RVC
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this International Standard is English.
IEC 63378-6:2026 © IEC 2026
This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available
at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are
described in greater detail at www.iec.ch/publications.
A list of all parts in the IEC 63378 series, published under the general title Thermal
standardization on semiconductor packages, can be found on the IEC website.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under webstore.iec.ch in the data related to the
specific document. At this date, the document will be
– reconfirmed,
– withdrawn, or
– revised.
IEC 63378-6:2026 © IEC 2026
INTRODUCTION
The IEC 63378-6 series is composed of the following parts:
1,2
– IEC 63378-6-1 [1] defines the model creation method using a datasheet of semiconductor
devices.
– IEC 63378-6-2 defines the model creation method using measurement data of
semiconductor devices.
The IEC 63378-6 series includes subjects such as the definition of a new thermal compact
model for thermal transient analysis of semiconductor packages, model creation methods,
accuracy assessment of these models, etc.

___________
Numbers in square brackets refer to the Bibliography.
Under preparation. Stage at the time of publication: IEC APUB 63378-6-1:2026.
Under development.
IEC 63378-6:2026 © IEC 2026
1 Scope
This part of IEC 63378 specifies a thermal resistance and capacitance model for semiconductor
packages. This model is named the digital transformation using thermal resistance and
capacitance (DXRC) model. It predicts transient temperature at junction and measurement
points.
This document applies to semiconductor packages such as TO-252, TO-263, and HSOP. It
supports single chip packages dissipated heat from single package surface.
2 Normative references
There are no normative references in this document.
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminology databases for use in standardization at the following
addresses:
– IEC Electropedia: available at https://www.electropedia.org/
– ISO Online browsing platform: available at https://www.iso.org/obp
3.1
thermal resistance
quotient of the difference between the virtual temperature of the device and the temperature of
a stated external reference point, by the steady-state power dissipation in the device
[SOURCE: IEC 60050-521:2002 [3], 521-05-13]
3.2
thermal capacitance
ability of a material to store thermal energy, calculated by product of specific heat and density
3.3
thermal resistance from junction to case top
θ
JC
thermal resistance between a junction and a semiconductor package surface
3.4
thermal RC topology
thermal network consisting of several thermal resistances, capacitances, and nodes
4 Definition of DXRC
4.1 General
Compact thermal models (CTMs) are commonly used for computer fluid dynamics (CFD)
analysis in semiconductor and electronics industries. Using CTMs reduces calculation time and
memory usage. However, there are few methods for CTMs which can support transient analysis
and estimation of measurement points. DXRC is a method to create CTMs which supports
predicting the temperature at a junction and arbitrary measurement points.
IEC 63378-6:2026 © IEC 2026
4.2 Thermal resistance and capacitance (RC) topology of DXRC
4.2.1 Thermal RC topology of DXRC
Thermal RC topology of DXRC shall be defined as in Figure 1. It has two RC circuit areas
named Near Junction Area – RC (NJA-RC) and Measurement Points Area – RC (MPA-RC).
NJA-RC contains a junction node named T and other nodes linking from it named from T to
J 1
T . These nodes are completely inside nodes, thus they do not have any surfaces which
N
exchange heat with the external environment. Each node has one thermal capacitance and is
connected to a neighbouring node. Only T generates heat. The end node of NJA-RC is
J
via a thermal resistance. MPA-RC contains
connected to the top node of MPA-RC named T
CORE
three nodes named T , T and T which are describing measurement points and five nodes
C L S
named T , T , T , T and T which are connecting to external 3D models via CTM
BI BO LB SB TOP
surfaces. This topology is defined according to the heat flow paths from junction to package
surfaces. Note that this thermal RC topology contains only thermal property inside a package,
namely, the thermal property of PCB and other surrounding environments is not contained.

Key
T thermal node representing the junction in a thermal RC topology
J
T internal thermal node as a branch point, not representing any actual location
CORE
T internal thermal nodes between T and T , not representing any actual locations, a natural number
N J CORE
starting from the one closest to T for N
J
T thermal node representing an arbitrary position on the top surface of the package, with a surface based on
TOP
the top surface of the package, that exchanges heat with the surrounding environment
T internal thermal node representing at an arbitrary position on the bottom metal surface of the package
C
T thermal node with a surface based on the metal surface directly under the chip, which exchanges heat with
BI
the surrounding environment
T thermal node with a surface based on the bottom resin surface of the package, which exchanges heat with
BO
the surrounding environment
T internal thermal node representing an arbitrary position on the lead terminals
L
T thermal node with surfaces based on the bottom surface of the lead terminals, which exchange heat with
LB
the surrounding environment
T internal thermal node representing an arbitrary position on a metal heat spreader of the package
S
T thermal node with a surface based on the bottom surface of a part of a metal heat spreader, which
SB
exchanges heat with the surrounding environment
Figure 1 – Thermal RC topology of DXRC
IEC 63378-6:2026 © IEC 2026
4.2.2 Outline of DXRC
DXRC has T , T , T , T and T as surface nodes. These surfaces should be defined
BI BO LB SB TOP
according to outline of semiconductor packages. An example is shown in Figure 2.

Figure 2 – Outline of DXRC
4.2.3 RC values on NJA-RC
RC values contained in NJA-RC shall be calculated by a common method [1]. Measurement,
simulation, datasheet of semiconductor packages and any other rising temperature data of
junction may be used as input data. The thermal resistance range between T and T should
J N
be smaller than between T and T in order to add MPA-RC later.
J C
4.2.4 RC values on MPA-RC
RC values on MPA-RC shall be optimized to minimize the error defined by Equations (1) and
(2). Other methods such as curve fitting may be used if equivalent optimization is possible.
Additionally, any optimization algorithm may be used. The input data are temperature rises at
a junction and at least one measurement point. This temperature data is the same as input data
at 4.2.3.
T tT− t
() ()
input DXRC
eT_ t ×100
()
(1)
J
Tt
()
input
eT_ t T t− T t
() () ()
(2)
M input DXRC
where
e_T (t) and e_T (t) are errors at time t between the input data and the result of DXRC
J M
for T and measurement points respectively;
J
T (t) is the temperature of input data;
input
T (t) is the estimated temperature by DXRC;
DXRC
t in the m-th power of 10 is calculated by Equation (3).
=
=
IEC 63378-6:2026 © IEC 2026
1,5
n
 
mm+1 m
(3)
tn=10+ 10 −×10 (=1, 2,,1 0)
( )
 
 
where
m is the integer number.
Both data can be calculated using linear interpolation or other methods if the times of the data
do not correspond to the times defi
...