EN IEC 63378-3:2025

Thermal standardization on semiconductor packages - Part 3: Thermal circuit simulation models of discrete semiconductor packages for transient analysis

IEC 63378-3:2025 specifies the thermal circuit network model of discrete (TO‑243, TO‑252 and TO‑263) packages, which is used in the transient analysis of electronic devices to estimate precise junction temperatures without experimental verification. This model is intended to be made and provided by semiconductor suppliers and to be used by assembly makers of electronic devices.

Thermische Standardisierung von Halbleitergehäusen - Teil 3: Thermische Schaltungssimulationsmodelle von diskreten Halbleitergehäusen für die Transientenanalyse

Normalisation thermique des boîtiers de semiconducteurs - Partie 3: Modèles de simulation de circuits thermiques de boîtiers de semiconducteurs discrets pour analyse transitoire

L’IEC 63378-3:2025 spécifie le modèle de réseau de circuits thermiques des boîtiers discrets (TO‑243, TO‑252 et TO‑263), qui est utilisé dans l’analyse transitoire des dispositifs électroniques pour estimer avec précision les températures de jonction sans vérification expérimentale. Ce modèle est destiné à être fabriqué et fourni par les fournisseurs de semiconducteurs, et à être utilisé par les assembleurs de dispositifs électroniques.

Standardizacija toplotnih lastnosti pri polprevodniških ohišjih - 3. del: Simulacijski modeli toplotnih vezij diskretnih polprevodniških ohišij za prehodno analizo (IEC 63378-3:2025)

Ta del standarda IEC 63378 določa omrežni model toplotnih vezij diskretnih ohišij (TO-243, TO-252 in TO-263), ki se uporablja pri prehodni analizi elektronskih naprav za natančno oceno temperatur stikov brez poskusnega preverjanja.
Ta model naj bi izdelali in zagotovili dobavitelji polprevodnikov, uporabljali pa naj bi ga proizvajalci sestavov elektronskih naprav.

General Information

• Status: Published
• Publication Date: 19-Jun-2025
• ICS: 31.080.01 - Semiconductor devices in general
• Technical Committee: CLC/TC 47X - Semiconductor devices and trusted chips
• Drafting Committee: IEC/SC 47D - IEC_SC_47D
• Current Stage: 6060 - Document made available - Publishing
• Start Date: 20-Jun-2025
• Due Date: 28-Jun-2024
• Completion Date: 20-Jun-2025
• Ref Project: SIST EN IEC 63378-3:2025 - Thermal standardization on semiconductor packages - Part 3: Thermal circuit simulation models of discrete semiconductor packages for transient analysis (IEC 63378-3:2025)

Overview

EN IEC 63378-3:2025 – Thermal Standardization on Semiconductor Packages, Part 3 provides critical specifications for the thermal circuit network model of discrete semiconductor packages (such as TO-243, TO-252, and TO-263). This European Standard is developed under the auspices of CLC (CENELEC) and aims to create a unified approach for transient analysis of electronic devices, enabling highly accurate estimation of junction temperatures without the need for experimental testing. The model is primarily intended for semiconductor suppliers and electronic device assembly makers who require reliable methods for thermal simulation during product design and verification.

By standardizing simulation models, EN IEC 63378-3:2025 promotes consistency and enhances the predictive reliability of thermal assessments across the electronics industry.

Key Topics

Core areas covered within EN IEC 63378-3:2025 include:

• Thermal circuit network models: Definition and application of RC (resistor-capacitor) network models for discrete semiconductor packages used in transient (non-steady-state) thermal analysis.
• Package types addressed: Focuses on TO-243, TO-252, and TO-263 semiconductor packages, widely used in diverse applications.
• Model development procedure: Guidance on constructing, validating, and simulating detailed thermal models, including Delphi-type models and their transformation into transient models.
• Parameter derivation: Methods to determine essential parameters such as thermal resistance and thermal capacitance based on the physical and material properties of package components.
• Model validation: Use of comparative analysis between detailed models and simplified network models (e.g., the D2elphi model) to ensure simulation accuracy aligns with real-world conditions.
• Design of Experiments (DoE): Structured approaches to calculate and fit capacitance values for package subcomponents to ensure model precision.

Applications

EN IEC 63378-3:2025 delivers practical value for:

• Semiconductor manufacturers, who must provide standardized thermal models to their customers, ensuring compatibility and reliability for thermal simulations.
• Electronics assembly makers, who use these models to predict device thermal performance, assess cooling strategies, and adhere to thermal constraints without costly physical testing.
• Thermal engineers and designers, enabling early detection of potential overheating issues in power electronics or densely packed circuits, thus optimizing PCB layout and component selection.
• Automotive, industrial, and consumer electronics sectors, where safety and reliability under varying thermal loads are essential, and thermal management is a critical design element.
• Simulation software developers, integrating standardized thermal network models to ensure their tools provide accurate and consistent transient analysis in accordance with industry standards.

Related Standards

For comprehensive application and implementation, EN IEC 63378-3:2025 should be considered alongside the following related standards and guidelines:

• JEDEC JESD51-2A: Integrated Circuit Thermal Test Method Environment Conditions – Natural Convection (Still Air)
• JEDEC JESD15-4: DELPHI Compact Thermal Model Guideline
• IEC 60191-2: Mechanical standardization of semiconductor devices – Dimensions
• EN IEC 63378 series: Other parts of the IEC 63378 standard, supporting both steady-state and transient thermal analysis of semiconductor packages

By adopting EN IEC 63378-3:2025, organizations reinforce reliable, repeatable thermal assessment and align with best practices in the thermal management of discrete semiconductor devices.

Standards Content (Sample)

SLOVENSKI STANDARD
01-september-2025
Standardizacija toplotnih lastnosti pri polprevodniških ohišjih - 3. del: Simulacijski
modeli toplotnih vezij diskretnih polprevodniških ohišij za prehodno analizo (IEC
63378-3:2025)
Thermal standardization on semiconductor packages - Part 3: Thermal circuit simulation
models of discrete semiconductor packages for transient analysis (IEC 63378-3:2025)
Thermische Standardisierung von Halbleitergehäusen - Teil 3: Thermische
Schaltungssimulationsmodelle von diskreten Halbleitergehäusen für die
Transientenanalyse (IEC 63378-3:2025)
Normalisation thermique des boîtiers de semiconducteurs - Partie 3: Modèles de
simulation de circuits thermiques de boîtiers de semiconducteurs discrets pour analyse
transitoire (IEC 63378-3:2025)
Ta slovenski standard je istoveten z: EN IEC 63378-3:2025
ICS:
31.080.01 Polprevodniški elementi Semiconductor devices in
(naprave) na splošno general
2003-01.Slovenski inštitut za standardizacijo. Razmnoževanje celote ali delov tega standarda ni dovoljeno.

EUROPEAN STANDARD EN IEC 63378-3

NORME EUROPÉENNE
EUROPÄISCHE NORM June 2025
ICS 31.080.01
English Version
Thermal standardization on semiconductor packages - Part 3:
Thermal circuit simulation models of discrete semiconductor
packages for transient analysis
(IEC 63378-3:2025)
Normalisation thermique des boîtiers de semiconducteurs - Thermische Standardisierung von Halbleitergehäusen - Teil
Partie 3: Modèles de simulation de circuits thermiques de 3: Thermische Schaltungssimulationsmodelle von diskreten
boîtiers de semiconducteurs discrets pour analyse Halbleitergehäusen für die Transientenanalyse
transitoire (IEC 63378-3:2025)
(IEC 63378-3:2025)
This European Standard was approved by CENELEC on 2025-06-10. CENELEC members are bound to comply with the CEN/CENELEC
Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration.
Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the CEN-CENELEC
Management Centre or to any CENELEC member.
This European Standard exists in three official versions (English, French, German). A version in any other language made by translation
under the responsibility of a CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the
same status as the official versions.
CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, the Czech Republic,
Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the
Netherlands, Norway, Poland, Portugal, Republic of North Macedonia, Romania, Serbia, Slovakia, Slovenia, Spain, Sweden, Switzerland,
Türkiye and the United Kingdom.

European Committee for Electrotechnical Standardization
Comité Européen de Normalisation Electrotechnique
Europäisches Komitee für Elektrotechnische Normung
CEN-CENELEC Management Centre: Rue de la Science 23, B-1040 Brussels
© 2025 CENELEC All rights of exploitation in any form and by any means reserved worldwide for CENELEC Members.
Ref. No. EN IEC 63378-3:2025 E

European foreword
The text of document 47D/967/CDV, future edition 1 of IEC 63378-3, prepared by SC 47D
"Semiconductor devices packaging" of IEC/TC 47 "Semiconductor devices" was submitted to the IEC-
CENELEC parallel vote and approved by CENELEC as EN IEC 63378-3:2025.
The following dates are fixed:
• latest date by which the document has to be implemented at national (dop) 2026-06-30
level by publication of an identical national standard or by endorsement
• latest date by which the national standards conflicting with the (dow) 2028-06-30
document have to be withdrawn
Attention is drawn to the possibility that some of the elements of this document may be the subject of
patent rights. CENELEC shall not be held responsible for identifying any or all such patent rights.
Any feedback and questions on this document should be directed to the users’ national committee. A
complete listing of these bodies can be found on the CENELEC website.
Endorsement notice
The text of the International Standard IEC 63378-3:2025 was approved by CENELEC as a European
Standard without any modification.

IEC 63378-3 ®
Edition 1.0 2025-05
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
Thermal standardization on semiconductor packages –
Part 3: Thermal circuit simulation models of discrete semiconductor packages
for transient analysis
Normalisation thermique des boîtiers de semiconducteurs –
Partie 3: Modèles de simulation de circuits thermiques de boîtiers de
semiconducteurs discrets pour analyse transitoire
ICS 31.080.01  ISBN 978-2-8327-0399-1

IEC 63378-3:2025-05(en-fr)
– 2 – IEC 63378-3:2025 © IEC 2025
CONTENTS
FOREWORD . 3
1 Scope . 5
2 Normative references . 5
3 Terms and definitions . 5
4 Procedure of thermal circuit network model . 6
4.1 General . 6
4.2 Detailed model analysis . 6
4.3 Delphi model preparation . 9
4.4 Thermal circuit model topology . 9
4.5 Determination of thermal capacitance values . 10
Annex A (normative) Validation for TO-252 case . 13
A.1 General . 13
A.2 Simulation parameters . 13
A.3 Comparison of detailed thermal model versus D2elphi model . 13
Bibliography . 15

Figure 1 – Two-resistor model. 6
Figure 2 – Delphi model . 6
Figure 3 – Detailed model (example) . 7
Figure 4 – PCB model . 8
Figure 5 – Simulation volume . 8
Figure 6 – Topology . 10
Figure A.1 – Heatsink model . 13

Table 1 – Dimensions and material properties of detailed model (Example) . 7
Table 2 – Dimensions and material properties of PCB model . 8
Table 3 – Thermal capacitance of the portions (Example) . 10
Table 4 – Thermal capacitance assignment . 11
Table 5 – The combination of α, β, γ (example) . 11
Table A.1 – Comparison with detailed thermal model and D2elphi model . 14

IEC 63378-3:2025 © IEC 2025 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
THERMAL STANDARDIZATION ON SEMICONDUCTOR PACKAGES –

Part 3: Thermal circuit simulation models of discrete
semiconductor packages for transient analysis

FOREWORD
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IEC 63378-3 has been prepared by subcommittee 47D: Semiconductor devices packaging, of
IEC technical committee 47: Semiconductor devices. It is an International Standard.
The text of this International Standard is based on the following documents:
Draft Report on voting
47D/967/CDV 47D/979/RVC
Full information on the voting for its approval can be found in the report on voting indicated in
the above table.
The language used for the development of this International Standard is English.

– 4 – IEC 63378-3:2025 © IEC 2025
This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in
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