IEC 62878-2-5:2019
(Main)Device embedding assembly technology - Part 2-5: Guidelines - Implementation of a 3D data format for device embedded substrate
Device embedding assembly technology - Part 2-5: Guidelines - Implementation of a 3D data format for device embedded substrate
IEC 62878-2-5:2019 specifies requirements based on XML schema that represents a design data format for device embedded substrate, which is a board comprising embedded active and passive devices whose electrical connections are made by means of a via, electroplating, conductive paste or printing of conductive material.
This data format is to be used for simulation (e.g. stress, thermal, EMC), tooling, manufacturing, assembly, and inspection requirements. Furthermore, the data format is used for transferring information among printed board designers, printed board simulation engineer, manufacturers, and assemblers.
IEC 62878-2-5:2019 applies to substrates using organic material. It neither applies to the re-distribution layer (RDL) nor to the electronic modules defined as M-type business model in IEC 62421.
Technologie d’ensemble avec appareil(s) intégré(s) - Partie 2-5 : Lignes directrices - Mise en œuvre d’un format de données 3D pour un substrat avec appareil(s) intégré(s)
L’IEC 62878-2-5:2019 spécifie des exigences fondées sur le schéma XML qui représente un format de données de conception pour le substrat avec appareil(s) intégré(s), c’est-à-dire une carte avec appareil(s) intégré(s) actif(s) ou passif(s) dont les connexions électriques se font au moyen d’un trou de liaison, de galvanoplastie, de pâte conductrice ou d’impression du matériau conducteur.
Ce format de données doit être utilisé pour les exigences de simulation (par exemple, contrainte, thermique, compatibilité électromagnétique), d’outillage, de fabrication, d’assemblage et d’examen. De plus, le format de données est utilisé pour le transfert d’informations entre les concepteurs de cartes imprimées, les ingénieurs de simulation des cartes imprimées, les fabricants et les assembleurs.
La présente partie de l’IEC 62878 s’applique aux substrats utilisant des matériaux organiques. Elle ne s'applique ni à la couche de redistribution (RDL, re-distribution layer), ni aux modules électroniques définis comme un modèle commercial de type M dans l'IEC 62421.
General Information
Relations
Overview
IEC 62878-2-5:2019 - Device embedding assembly technology - Part 2-5 provides guidelines for implementing a 3D data format for device embedded substrate designs. The standard defines an XML schema-based design data format to describe boards that contain embedded active and passive devices whose electrical connections use vias, electroplating, conductive paste, or printed conductive materials. The data format supports simulation, tooling, manufacturing, assembly and inspection, and enables information exchange between printed board designers, simulation engineers, manufacturers and assemblers.
Scope highlights
- Applies to substrates using organic material.
- Intended for 3D representation of embedded-device substrates (including SiP interposers).
- Excludes redistribution layers (RDL) and M-type electronic modules defined in IEC 62421.
Key Topics and Technical Requirements
- XML schema data model: A structured XML-based representation for complete 3D design data and metadata.
- 3D expression and coordinates: Definitions for coordinate origins, position description and board-relative placement to enable accurate 3D modelling.
- Layer concept and stack-up: Formal description of layer maps, stack-up information and virtual layers for multi-layer embedded substrates.
- Device and package description: Structured data for embedded devices, SiP elements, lands, vias and terminal definitions.
- Net, artwork and port information: Net connectivity, artwork details, external/internal ports, and package-to-board relationships.
- Primitive geometry and shapes: Points, areas, lines, letter shapes, truncated pyramids and other geometric primitives for accurate physical modelling.
- File organization: Recommended one-file or two-file structures for packaging design data and layering.
- User expansion fields: Extension points for vendor-specific or project-specific metadata.
- Use cases supported: Stress, thermal and EMC simulation; tooling and manufacturing planning; assembly and inspection workflows.
Applications
- Exchanging design-to-manufacturing data for embedded-component PCBs and system-in-package (SiP) substrates.
- Feeding 3D simulation tools for mechanical stress, thermal and EMC analysis.
- Generating tooling files and assembly instructions for manufacturers and assemblers.
- Supporting inspection and quality workflows through precise 3D model and port/land definitions.
Who should use this standard
- PCB and substrate designers working with embedded active/passive devices
- EDA/CAD tool vendors implementing data exchange formats
- Simulation engineers (thermal, stress, EMC)
- Board manufacturers, assemblers and inspection teams
- Supply chain partners requiring standardized 3D design data exchange
Related Standards
- IEC 62421 - referenced in scope for M-type module definitions
- Other parts of the IEC 62878 series on device embedding assembly technology (see IEC for complete series)
Using IEC 62878-2-5:2019 helps organizations standardize 3D device-embedded substrate data, reduce ambiguity in design-to-manufacture handoffs, and improve interoperability across CAD/EDA, simulation and production toolchains.
Standards Content (Sample)
IEC 62878-2-5 ®
Edition 1.0 2019-09
INTERNATIONAL
STANDARD
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inside
Device embedding assembly technology –
Part 2-5: Guidelines – Implementation of a 3D data format for device embedded
substrate
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IEC 62878-2-5 ®
Edition 1.0 2019-09
INTERNATIONAL
STANDARD
colour
inside
Device embedding assembly technology –
Part 2-5: Guidelines – Implementation of a 3D data format for device embedded
substrate
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 31.180; 31.190 ISBN 978-2-8322-7399-9
– 2 – IEC 62878-2-5:2019 © IEC 2019
CONTENTS
FOREWORD . 5
1 Scope . 7
2 Normative references . 7
3 Terms and definitions . 7
4 Data definition . 10
4.1 Flow chart design of device embedded substrate . 10
4.2 Applicable range . 11
4.2.1 Product . 11
4.2.2 Process . 12
4.3 Features . 13
4.3.1 General . 13
4.3.2 Device embedded substrate structure . 13
4.3.3 SiP interposer structure . 14
4.3.4 Virtual layer description . 15
4.3.5 Terminal structure and embedded device structure including an SiP . 15
4.3.6 Total design data of an SiP and device embedded substrate . 15
4.4 Data description summary . 16
4.4.1 Type of data and structures . 16
4.4.2 File structure . 18
4.5 3D expression . 19
4.5.1 General . 19
4.5.2 Coordinates . 19
4.5.3 Position description . 20
4.5.4 Relation between coordinate origin and board position . 20
4.6 Layer concept . 21
4.7 Substrate data . 21
4.7.1 General . 21
4.7.2 Layer map information . 22
4.7.3 Device arrangement information . 23
4.7.4 Basic figures . 25
4.7.5 Net information . 31
4.7.6 Artwork information . 32
4.7.7 Package information . 32
4.7.8 External port information. 33
4.7.9 Internal port information . 33
4.7.10 User expansion information . 33
4.8 Defined data . 33
4.8.1 General . 33
4.8.2 Layer definition . 33
4.8.3 Land definition . 34
4.8.4 Via definition . 35
4.8.5 Device definition . 36
4.8.6 User expansion definition . 37
5 Data organization and data description based on XML schema . 38
5.1 General . 38
5.2 Data organization of Example 1 . 38
5.3 Data description of layer stack-up . 39
5.4 Data description of device . 43
5.5 Data organization of layer . 47
5.6 Data description of via . 50
5.7 Data description of land . 51
Bibliography . 53
Figure 1 – Flow chart of design of device embedded substrate . 11
Figure 2 – General structure of device embedded substrate . 12
Figure 3 – Example of device embedded substrate structure. 14
Figure 4 – Examples of SiPs . 14
Figure 5 – Example of virtual layer description . 15
Figure 6 – Terminal structure . 15
Figure 7 – Structure of SiP on a device embedded substrate . 16
Figure 8 – Data structure . 18
Figure 9 – One file structure (recommended) . 19
Figure 10 – Two file structure . 19
Figure 11 – Definition of coordinates . 20
Figure 12 – Position definition . 20
Figure 13 – Relation between coordinates and board position . 21
Figure 14 – Layer concept . 21
Figure 15 – Layer construction . 22
Figure 16 – Simplified layer construction . 23
Figure 17 – Layer definition of pad connection . 24
Figure 18 – Layer definition of via connection . 24
Figure 19 – Rotation direction on X, Y, and Z axes . 25
Figure 20 – Point . 26
Figure 21 – Area . 27
Figure 22 – Lines . 27
Figure 23 – Letters . 28
Figure 24 – Letter shape . 28
Figure 25 – Bonding wire information . 29
Figure 26 – Semi-sphere . 29
Figure 27 – Truncated pyramid . 30
Figure 28 – Via . 30
Figure 29 – Device definition . 31
Figure 30 – Group . 31
Figure 31 – Data structure of net information . 32
Figure 32 – Relation of layer definition data . 34
Figure 33 – Land definition . 35
Figure 34 – Relation between hole information and land information . 36
Figure 35 – Device with internal connection information . 37
Figure 36 – Device without internal connection information . 37
Figure 37 – Cross sectional view of Example 1 . 38
Figure 38 – Data organization of Example 1 . 38
– 4 – IEC 62878-2-5:2019 © IEC 2019
Figure 39 – Data descripion of Example 1 . 39
Figure 40 – Layer structure of Example 1 . 40
Figure 41 – Data description of layer stack-up . 42
Figure 42 – Configuration of device 1. 43
Figure 43 – Data description of device 1 . 44
Figure 44 – Configuration of device 2. 45
Figure 45 – Data description of device 2 . 46
Figure 46 – Layer view of Example 1 . 48
Figure 47 – Data description of layers . 50
Figure 48 – Type of vias . 51
Figure 49 – Data description of vias . 51
Figure 50 – Type of lands . 52
Figure 51 – Data description of lands . 52
Table 1 – Required information . 13
Table 2 – List of data . 17
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
DEVICE EMBEDDING ASSEMBLY TECHNOLOGY –
Part 2-5: Guidelines – Implementation of a 3D data format
for device embedded substrate
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international
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International Standard IEC 62878-2-5 has been prepared by IEC technical committee 91:
Electronics assembly technology.
This first edition cancels and replaces IEC PAS 62878-2-5 published in 2015. This edition
constitutes a technical revision.
This edition includes the following significant technical changes with respect to the previous
edition:
a) the title has been changed to "Implementation of a 3D data format for device embedded
substrate" from "Requirements of design date format for device embedded substrate";
b) the scope of this implementation has changed to not include SiPs.
– 6 – IEC 62878-2-5:2019 © IEC 2019
The text of this International Standard is based on the following documents:
CDV Report on voting
91/1557/CDV 91/1589/RVC
Full information on the voting for the approval of this International Standard can be found in the
report on voting indicated in the above table.
This document has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all parts in the IEC 62878 series, published under the general title Device embedding
assembly technology, can be found on the IEC website.
Future standards in this series will carry the new general title as cited above. Titles of existing
standards in this series will be updated at the time of the next edition.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to
the specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
A bilingual version of this publication may be issued at a later date.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct
understanding of its contents. Users should therefore print this document using a
colour printer.
DEVICE EMBEDDING ASSEMBLY TECHNOLOGY –
Part 2-5: Guidelines – Implementation of a 3D data format
for device embedded substrate
1 Scope
This part of IEC 62878 specifies requirements based on XML schema that represents a design
data format for device embedded substrate, which is a board comprising embedded active and
passive devices whose electrical connections are made by means of a via, electroplating,
conductive paste or printing of conductive material.
This data format is to be used for simulation (e.g. stress, thermal, EMC), tooling, manufacturing,
assembly, and inspection requirements. Furthermore, the data format is used for transferring
information among printed board designers, printed board simulation engineer, manufacturers,
and assemblers.
This part of IEC 62878 applies to substrates using organic material. It neither applies to the
re-distribution layer (RDL) nor to the electronic modules defined as M-type business model in
IEC 62421.
2 Normative references
There are no normative references in this document.
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminological databases for use in standardization at the following
addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
3.1
artwork information
information that shows a SiP not included in net and figure data in board (symbol mark, inside
of SiP, mould, spacer, remarks, etc.)
3.2
board information
total information of a device-embedded substrate, including embedded devices
3.3
chip stack
package of semiconductor chips stacked vertically
3.4
clearance
area around a through-hole where there is no conductor to prevent electrical connection
between a large conductor area, such as that of a power supply or a ground and a plated
through-hole
– 8 – IEC 62878-2-5:2019 © IEC 2019
3.5
computer-aided manufacturing
CAM
interactive use of computer systems, programs, and procedures in various phases of a
manufacturing process wherein the decision-making activity rests with the human operator and
a computer provides the data manipulation functions
3.6
computer-aided design
CAD
interactive use of computer systems, programs, and procedures in the design process wherein
the decision-making activity rests with the human operator and a computer provides the data
manipulation function
3.7
DXF
data format for AutoCAD
Note 1 to entry: AutoCAD is the trade name of a product supplied by Autodesk®. This information is given for the
convenience of users of this document and does not constitute an endorsement by IEC of the product named.
Equivalent products may be used if they can be shown to lead to the same results.
Note 2 to entry: It generally means a type of data format to draw figures using CAD board data.
3.8
design document
documentation of information necessary in circuit board design
3.9
device arrangement information
information that includes the position, the shape and attributes of the embedding device
included in the net information
3.10
device embedded substrate
substrate in which an active device(s) (semiconductor device) and/or passive device(s) (e.g.
resistor, capacitor) is formed using thick-film technology or by embedding it within the substrate
3.11
FLIP chip
FC
leadless monolithic circuit element structure that electrically and mechanically interconnects to
a printed board by conductive bumps
3.12
Gerber
type of data format that consists of aperture selection and operation commands and dimensions
in X- and Y-coordinates
Note 1 to entry: The data is generally used to direct a photo-plotter in generating photo-plotted artwork.
Note 2 to entry: Gerber is the trade name of a product supplied by Ucamco. This information is given for the
convenience of users of this document and does not constitute an endorsement by IEC of the product named.
Equivalent products may be used if they can be shown to lead to the same results.
3.13
interposer
material placed between two surfaces giving electrical insulation, redistribution of electrical
connections, mechanical strength and/or controlled mechanical and thermal separation
between the two surfaces
Note 1 to entry: An interposer may be used as a means for redistributing electrical connections and/or allowing for
different thermal expansions between adjacent surfaces.
3.14
land
pad
portion of a conductive pattern usually used for the connection and/or attachment of components
3.15
land definition
maintainance of a shape of specific land, pad, solder resist and others
3.16
layer definition
combination of physical information of shape and construction and logic information giving
design and production units
3.17
layer map
map showing the relation between devices and the board, the devices being arranged on the
board
3.18
library
database of design information, based on a design document, to be used in board CAD
3.19
logical layer
layer that can be arbitrarily formed in the event that it is difficult to physically express a layer in
a design
Note 1 to entry: It is possible to relate it to a physical layer.
Note 2 to entry: It is different from the layers in a multi-layer substrate.
3.20
micro-electro-mechanical system
MEMS
system integrating micro-machine, mechanical elements, sensor, actuator, and electronic circuit
into one module
3.21
net information
device pin construction and wiring pattern in this PAS
3.22
package information
shapes of board and devices when they have package shape patterns in this document
3.23
PoP
package on package
single or multiple package(s) mounted on a package of a single chip or multiple chips as single
package
3.24
physical layer
layer consisting of a physical layer construction and structure
– 10 – IEC 62878-2-5:2019 © IEC 2019
3.25
port information
information of figures and names of external terminals of a device or a substrate with terminals
3.26
structure
total structure of a device embedded substrate and/or surface device mounted to the substrate
3.27
SiP
system in a package
multi-chip package (MCP) that performs a system function
3.28
thermal land
heat energy may leak to outside of a land/through-hole when a device is soldered on a large
pattern such as power supply or ground. A cut is often made around such a soldering point to
prevent thermal dissipation
3.29
through silicon via
TSV
hole made in a silicon chip and filled with metal to electrically connect upper and lower side of
the chip for 3D stacking package
3.30
via definition
via that is used as an interlayer connection, but in which there is no intention to insert a
component lead or other reinforcing material
3.31
virtual layer
name of the layer connecting conductor layers when a device is embedded
Note 1 to entry: It corresponds to the connection point of a device terminal specified in IEC TS 62678-2-3.
3.32
wire bonding
WB
micro-bonding between a die and base material, lead frame, etc.
4 Data definition
4.1 Flow chart design of device embedded substrate
Figure 1 shows the design flow of a device embedded substrate. The design data can be
directly sent to a board manufacturing system using this format, or can be converted to CAM
data and then be used in production. The data contain 3D information of coordinates and
shapes of devices used. It is possible to check the status of device embedding in a board, and
also make it a common knowledge in production know-how of a production line.
This file format describes the detailed 3D information of the following electronic circuit boards,
including device embedded substrate and SiP (system in package), and makes it possible to
use necessary information from the stage of design to the fabrication of products.
Figure 1 – Flow chart of design of device embedded substrate
4.2 Applicable range
4.2.1 Product
It is possible to maintain the following design information of a device embedded substrate as
shown in Figure 2.
...
IEC 62878-2-5 ®
Edition 1.0 2019-09
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Device embedding assembly technology –
Part 2-5: Guidelines – Implementation of a 3D data format for device embedded
substrate
Technologie d’ensemble avec appareil(s) intégré(s) –
Partie 2-5: Lignes directrices – Mise en œuvre d’un format de données 3D
pour un substrat avec appareil(s) intégré(s)
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The International Electrotechnical Commission (IEC) is the leading global organization that prepares and publishes
International Standards for all electrical, electronic and related technologies.
About IEC publications
The technical content of IEC publications is kept under constant review by the IEC. Please make sure that you have the
latest edition, a corrigendum or an amendment might have been published.
IEC publications search - webstore.iec.ch/advsearchform Electropedia - www.electropedia.org
The advanced search enables to find IEC publications by a The world's leading online dictionary on electrotechnology,
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committee,…). It also gives information on projects, replaced and French, with equivalent terms in 16 additional languages.
and withdrawn publications. Also known as the International Electrotechnical Vocabulary
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IEC 62878-2-5 ®
Edition 1.0 2019-01
INTERNATIONAL
STANDARD
NORME
INTERNATIONALE
colour
inside
Device embedding assembly technology –
Part 2-5: Guidelines – Implementation of a 3D data format for device embedded
substrate
Technologie d’ensemble avec appareil(s) intégré(s) –
Partie 2-5: Lignes directrices – Mise en œuvre d’un format de données 3D
pour un substrat avec appareil(s) intégré(s)
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
COMMISSION
ELECTROTECHNIQUE
INTERNATIONALE
ICS 31.180; 31.190 ISBN 978-2-8322-7768-3
– 2 – IEC 62878-2-5:2019 © IEC 2019
CONTENTS
FOREWORD . 5
1 Scope . 7
2 Normative references . 7
3 Terms and definitions . 7
4 Data definition . 10
4.1 Flow chart design of device embedded substrate . 10
4.2 Applicable range . 11
4.2.1 Product . 11
4.2.2 Process . 12
4.3 Features . 13
4.3.1 General . 13
4.3.2 Device embedded substrate structure . 13
4.3.3 SiP interposer structure . 14
4.3.4 Virtual layer description . 15
4.3.5 Terminal structure and embedded device structure including an SiP . 15
4.3.6 Total design data of an SiP and device embedded substrate . 15
4.4 Data description summary . 16
4.4.1 Type of data and structures . 16
4.4.2 File structure . 18
4.5 3D expression . 19
4.5.1 General . 19
4.5.2 Coordinates . 19
4.5.3 Position description . 20
4.5.4 Relation between coordinate origin and board position . 20
4.6 Layer concept . 21
4.7 Substrate data . 21
4.7.1 General . 21
4.7.2 Layer map information . 22
4.7.3 Device arrangement information . 23
4.7.4 Basic figures . 25
4.7.5 Net information . 31
4.7.6 Artwork information . 32
4.7.7 Package information . 32
4.7.8 External port information. 33
4.7.9 Internal port information . 33
4.7.10 User expansion information . 33
4.8 Defined data . 33
4.8.1 General . 33
4.8.2 Layer definition . 33
4.8.3 Land definition . 34
4.8.4 Via definition . 35
4.8.5 Device definition . 36
4.8.6 User expansion definition . 37
5 Data organization and data description based on XML schema . 38
5.1 General . 38
5.2 Data organization of Example 1 . 38
5.3 Data description of layer stack-up . 39
5.4 Data description of device . 43
5.5 Data organization of layer . 47
5.6 Data description of via . 50
5.7 Data description of land . 51
Bibliography . 53
Figure 1 – Flow chart of design of device embedded substrate . 11
Figure 2 – General structure of device embedded substrate . 12
Figure 3 – Example of device embedded substrate structure. 14
Figure 4 – Examples of SiPs . 14
Figure 5 – Example of virtual layer description . 15
Figure 6 – Terminal structure . 15
Figure 7 – Structure of SiP on a device embedded substrate . 16
Figure 8 – Data structure . 18
Figure 9 – One file structure (recommended) . 19
Figure 10 – Two file structure . 19
Figure 11 – Definition of coordinates . 20
Figure 12 – Position definition . 20
Figure 13 – Relation between coordinates and board position . 21
Figure 14 – Layer concept . 21
Figure 15 – Layer construction . 22
Figure 16 – Simplified layer construction . 23
Figure 17 – Layer definition of pad connection . 24
Figure 18 – Layer definition of via connection . 24
Figure 19 – Rotation direction on X, Y, and Z axes . 25
Figure 20 – Point . 26
Figure 21 – Area . 27
Figure 22 – Lines . 27
Figure 23 – Letters . 28
Figure 24 – Letter shape . 28
Figure 25 – Bonding wire information . 29
Figure 26 – Semi-sphere . 29
Figure 27 – Truncated pyramid . 30
Figure 28 – Via . 30
Figure 29 – Device definition . 31
Figure 30 – Group . 31
Figure 31 – Data structure of net information . 32
Figure 32 – Relation of layer definition data . 34
Figure 33 – Land definition . 35
Figure 34 – Relation between hole information and land information . 36
Figure 35 – Device with internal connection information . 37
Figure 36 – Device without internal connection information . 37
Figure 37 – Cross sectional view of Example 1 . 38
Figure 38 – Data organization of Example 1 . 38
– 4 – IEC 62878-2-5:2019 © IEC 2019
Figure 39 – Data descripion of Example 1 . 39
Figure 40 – Layer structure of Example 1 . 40
Figure 41 – Data description of layer stack-up . 42
Figure 42 – Configuration of device 1. 43
Figure 43 – Data description of device 1 . 44
Figure 44 – Configuration of device 2. 45
Figure 45 – Data description of device 2 . 46
Figure 46 – Layer view of Example 1 . 48
Figure 47 – Data description of layers . 50
Figure 48 – Type of vias . 51
Figure 49 – Data description of vias . 51
Figure 50 – Type of lands . 52
Figure 51 – Data description of lands . 52
Table 1 – Required information . 13
Table 2 – List of data . 17
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
DEVICE EMBEDDING ASSEMBLY TECHNOLOGY –
Part 2-5: Guidelines – Implementation of a 3D data format
for device embedded substrate
FOREWORD
1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising
all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international
co-operation on all questions concerning standardization in the electrical and electronic fields. To this end and in
addition to other activities, IEC publishes International Standards, Technical Specifications, Technical Reports,
Publicly Available Specifications (PAS) and Guides (hereafter referred to as "IEC Publication(s)"). Their
preparation is entrusted to technical committees; any IEC National Committee interested in the subject dealt with
may participate in this preparatory work. International, governmental and non-governmental organizations liaising
with the IEC also participate in this preparation. IEC collaborates closely with the International Organization for
Standardization (ISO) in accordance with conditions determined by agreement between the two organizations.
2) The formal decisions or agreements of IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all
interested IEC National Committees.
3) IEC Publications have the form of recommendations for international use and are accepted by IEC National
Committees in that sense. While all reasonable efforts are made to ensure that the technical content of IEC
Publications is accurate, IEC cannot be held responsible for the way in which they are used or for any
misinterpretation by any end user.
4) In order to promote international uniformity, IEC National Committees undertake to apply IEC Publications
transparently to the maximum extent possible in their national and regional publications. Any divergence between
any IEC Publication and the corresponding national or regional publication shall be clearly indicated in the latter.
5) IEC itself does not provide any attestation of conformity. Independent certification bodies provide conformity
assessment services and, in some areas, access to IEC marks of conformity. IEC is not responsible for any
services carried out by independent certification bodies.
6) All users should ensure that they have the latest edition of this publication.
7) No liability shall attach to IEC or its directors, employees, servants or agents including individual experts and
members of its technical committees and IEC National Committees for any personal injury, property damage or
other damage of any nature whatsoever, whether direct or indirect, or for costs (including legal fees) and expenses
arising out of the publication, use of, or reliance upon, this IEC Publication or any other IEC Publications.
8) Attention is drawn to the Normative references cited in this publication. Use of the referenced publications is
indispensable for the correct application of this publication.
9) Attention is drawn to the possibility that some of the elements of this IEC Publication may be the subject of patent
rights. IEC shall not be held responsible for identifying any or all such patent rights.
International Standard IEC 62878-2-5 has been prepared by IEC technical committee 91:
Electronics assembly technology.
This bilingual version (2020-01) corresponds to the monolingual English version, published in
2019-09.
This first edition cancels and replaces IEC PAS 62878-2-5 published in 2015. This edition
constitutes a technical revision.
This edition includes the following significant technical changes with respect to the previous
edition:
a) the title has been changed to "Implementation of a 3D data format for device embedded
substrate" from "Requirements of design date format for device embedded substrate";
b) the scope of this implementation has changed to not include SiPs.
– 6 – IEC 62878-2-5:2019 © IEC 2019
The text of this International Standard is based on the following documents:
CDV Report on voting
91/1557/CDV 91/1589/RVC
Full information on the voting for the approval of this International Standard can be found in the
report on voting indicated in the above table.
The French version of this standard has not been voted upon.
This document has been drafted in accordance with the ISO/IEC Directives, Part 2.
A list of all parts in the IEC 62878 series, published under the general title Device embedding
assembly technology, can be found on the IEC website.
Future standards in this series will carry the new general title as cited above. Titles of existing
standards in this series will be updated at the time of the next edition.
The committee has decided that the contents of this document will remain unchanged until the
stability date indicated on the IEC website under "http://webstore.iec.ch" in the data related to
the specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.
IMPORTANT – The 'colour inside' logo on the cover page of this publication indicates
that it contains colours which are considered to be useful for the correct
understanding of its contents. Users should therefore print this document using a
colour printer.
DEVICE EMBEDDING ASSEMBLY TECHNOLOGY –
Part 2-5: Guidelines – Implementation of a 3D data format
for device embedded substrate
1 Scope
This part of IEC 62878 specifies requirements based on XML schema that represents a design
data format for device embedded substrate, which is a board comprising embedded active and
passive devices whose electrical connections are made by means of a via, electroplating,
conductive paste or printing of conductive material.
This data format is to be used for simulation (e.g. stress, thermal, EMC), tooling, manufacturing,
assembly, and inspection requirements. Furthermore, the data format is used for transferring
information among printed board designers, printed board simulation engineer, manufacturers,
and assemblers.
This part of IEC 62878 applies to substrates using organic material. It neither applies to the
re-distribution layer (RDL) nor to the electronic modules defined as M-type business model in
IEC 62421.
2 Normative references
There are no normative references in this document.
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
ISO and IEC maintain terminological databases for use in standardization at the following
addresses:
• IEC Electropedia: available at http://www.electropedia.org/
• ISO Online browsing platform: available at http://www.iso.org/obp
3.1
artwork information
information that shows a SiP not included in net and figure data in board (symbol mark, inside
of SiP, mould, spacer, remarks, etc.)
3.2
board information
total information of a device-embedded substrate, including embedded devices
3.3
chip stack
package of semiconductor chips stacked vertically
3.4
clearance
area around a through-hole where there is no conductor to prevent electrical connection
between a large conductor area, such as that of a power supply or a ground and a plated
through-hole
– 8 – IEC 62878-2-5:2019 © IEC 2019
3.5
computer-aided manufacturing
CAM
interactive use of computer systems, programs, and procedures in various phases of a
manufacturing process wherein the decision-making activity rests with the human operator and
a computer provides the data manipulation functions
3.6
computer-aided design
CAD
interactive use of computer systems, programs, and procedures in the design process wherein
the decision-making activity rests with the human operator and a computer provides the data
manipulation function
3.7
DXF
data format for AutoCAD
Note 1 to entry: AutoCAD is the trade name of a product supplied by Autodesk®. This information is given for the
convenience of users of this document and does not constitute an endorsement by IEC of the product named.
Equivalent products may be used if they can be shown to lead to the same results.
Note 2 to entry: It generally means a type of data format to draw figures using CAD board data.
3.8
design document
documentation of information necessary in circuit board design
3.9
device arrangement information
information that includes the position, the shape and attributes of the embedding device
included in the net information
3.10
device embedded substrate
substrate in which an active device(s) (semiconductor device) and/or passive device(s) (e.g.
resistor, capacitor) is formed using thick-film technology or by embedding it within the substrate
3.11
FLIP chip
FC
leadless monolithic circuit element structure that electrically and mechanically interconnects to
a printed board by conductive bumps
3.12
Gerber
type of data format that consists of aperture selection and operation commands and dimensions
in X- and Y-coordinates
Note 1 to entry: The data is generally used to direct a photo-plotter in generating photo-plotted artwork.
Note 2 to entry: Gerber is the trade name of a product supplied by Ucamco. This information is given for the
convenience of users of this document and does not constitute an endorsement by IEC of the product named.
Equivalent products may be used if they can be shown to lead to the same results.
3.13
interposer
material placed between two surfaces giving electrical insulation, redistribution of electrical
connections, mechanical strength and/or controlled mechanical and thermal separation
between the two surfaces
Note 1 to entry: An interposer may be used as a means for redistributing electrical connections and/or allowing for
different thermal expansions between adjacent surfaces.
3.14
land
pad
portion of a conductive pattern usually used for the connection and/or attachment of components
3.15
land definition
maintainance of a shape of specific land, pad, solder resist and others
3.16
layer definition
combination of physical information of shape and construction and logic information giving
design and production units
3.17
layer map
map showing the relation between devices and the board, the devices being arranged on the
board
3.18
library
database of design information, based on a design document, to be used in board CAD
3.19
logical layer
layer that can be arbitrarily formed in the event that it is difficult to physically express a layer in
a design
Note 1 to entry: It is possible to relate it to a physical layer.
Note 2 to entry: It is different from the layers in a multi-layer substrate.
3.20
micro-electro-mechanical system
MEMS
system integrating micro-machine, mechanical elements, sensor, actuator, and electronic circuit
into one module
3.21
net information
device pin construction and wiring pattern in this PAS
3.22
package information
shapes of board and devices when they have package shape patterns in this document
3.23
PoP
package on package
single or multiple package(s) mounted on a package of a single chip or multiple chips as single
package
3.24
physical layer
layer consisting of a physical layer construction and structure
– 10 – IEC 62878-2-5:2019 © IEC 2019
3.25
port information
information of figures and names of external terminals of a device or a substrate with terminals
3.26
structure
total structure of a device embedded substrate and/or surface device mounted to the substrate
3.27
SiP
system in a package
multi-chip package (MCP) that performs a system function
3.28
thermal land
heat energy may leak to outside of a land/through-hole when a device is soldered on a large
pattern such as power supply or ground. A cut is often made around such a soldering point to
prevent thermal dissipation
3.29
through silicon via
TSV
hole made in a silicon chip and filled with metal to electrically connect upper and lower side of
the chip for 3D stacking package
3.30
via definition
via that is used as an interlayer connection, but in which there is no intention to insert a
component lead or other reinforcing material
3.31
virtual layer
name of the layer connecting conductor layers when a device is embedded
Note 1 to entry: It corresponds to the connection point of a device terminal specified in IEC TS 62678-2-3.
3.32
wire bonding
WB
micro-bonding between a die and base material, lead frame, etc.
4 Data definition
4.1 Flow chart design of device embedded substrate
Figure 1 shows the design flow of a device embedded substrate. The design data can be
directly sent to a board manufacturing system using this format, or can be converted to CAM
data and then be used in production. The data contain 3D information of coordinates and
shapes of devices used. It is possible to check the status of device embedding in a board, and
also make it a common knowledge in production know-how of a production line.
This file format describes the detailed 3D information of the following electronic circuit boards,
including device embedded substrate and SiP (system in package), and makes it possible to
use necessary information from the stage of design to the fabrication of products.
Figure 1 – Flow chart of design of device embedded substrate
4.2 Applicable range
4.2.1 Product
It is possible to maintain the following design information of a device embedded substrate as
shown in Figure 2.
– 12 – IEC 62878-2-5:2019 © IEC 2019
A Embedded active device E Inner pattern
B Surface mounted active device F Surface pattern
C Surface mounted passive device G Solder resist
D Layer connecting via
Figure 2 – General structure of device embedded substrate
4.2.2 Process
The format describes maintained and available information of each stage in production as
described in Table 1:
1) design,
2) simulation,
3) substrate fabrication,
4) device embedding,
5) test.
Table 1 – Required information
Process Holding data Available data
Design Circuit Limited condition
Components Net list
Shape of the board
Board structure
Design/Production rule (for check)
Simulation Circuit Electrical properties
Characteristics of components Thermal properties
Board properties (materials) Mechanical properties
Board structure Electronic properties
Art work Additional information in production
Substrate fabrication Art work Equipment
Drilling Additional information in production
Symbol marks
Panel format
Device embedding Component shape Equipment
Embedding position Relative positions of component
Interconnection terminals Component list
Symbol marks
Test Art work Electrical test equipment
Component shape Video image inspection
Component position
Terminal information
Marks
4.3 Features
4.3.1 General
The data format has the following characteristics:
1) can contain the structure of the device embedded substrate specified in IEC TS 62678-2-3;
2) can contain information of SiP in general (chip stack, PoP TSV, wire bonding, FLIP chip,
interposer, etc.);
3) holds design data of terminal positions of embedding device in a virtual layer specified in
IEC TS 62678-2-3;
4) information on the internal structure of devices such as SiP, which cannot be described as a
structure of a device embedded substrate and of a terminal structure as 3D design data;
5) seamless keeping of design data of devices having different levels, such as SiPs, and of
embedding substrate.
4.3.2 Device embedded substrate structure
It is possible to keep and illustrate the 3D structure of the device embedded substrate as shown
in Figure 3. It is also possible to check its 3D structure.
– 14 – IEC 62878-2-5:2019 © IEC 2019
A Embedded active device D Pad connection
B Embedded passive device E Space without board material
C Via connection
Figure 3 – Example of device embedded substrate structure
4.3.3 SiP interposer structure
It is possible to keep and illustrate the 3D structure of the SiP substrate as shown in Figure 4. It
is also possible to check the structures of FLIP chip and wire bonding mounting.
A Interposer D Wiring in the Interposer
B Flip-chip connection E Package
C Wire bonding connection F Solder ball
Figure 4 – Examples of SiPs
4.3.4 Virtual layer description
It is possible to keep the design data of the terminal position of a via connection not on a
conductor layer, but as in a virtual layer. It can be maintained in the structure shown in Figure 5.
A Surface conductor layer C Inner conductor
B Virtual layer (connection position) D Insulation layer
Figure 5 – Example of virtual layer description
4.3.5 Terminal structure and embedded device structure including an SiP
It is possible to keep the design data of the terminal position of an SiP as shown in Figure 6.
A Bonding wire D Interposer
B Chip stack E Solder ball
C Package shape
Figure 6 – Terminal structure
4.3.6 Total design data of an SiP and device embedded substrate
It is possible to keep the design data of an SiP and the device embedded substrate being made
on different layers as shown in Figure 7.
– 16 – IEC 62878-2-5:2019 © IEC 2019
A Substrate C Surface mounted passive device
B SiP D The same net
Figure 7 – Structure of SiP on a device embedded substrate
4.4 Data description summary
4.4.1 Type of data and structures
1) Type of data
There are the following data:
– substrate data,
– definition data.
Details of these data are shown in Table 2.
Table 2 – List of data
Type Details
Type name Content Name Content
Board data Basic structure elements Board information Total data of board including embedding
of board data devices
Layer map Layer combination information of
information embedding devices and layers
Device arrangement Position of devices and embedding layers
information
Basic figure Available figure elements in board data
information
There are ten (10) types of figures
1 Point
2 Area
3 Line
4 Text
5 Bonding wire
6 Semi-sphere
7 Rectangular prismoid
8 Via
9 Device
10 Group
Net information Device pin construction and wiring patterns
Artwork information Figure pattern other than wiring pattern
Package information Package figure information
External terminal Figures and names of external terminals
information
Internal terminal Figures and names of internal terminals
information
User expandable Arbitrarily expandable data of the format
information user "Definition" = "Value" can be arbitrarily
defined
Definition Definition of information Layer definition Shapes of layer construction, conductor
data that can be repeatedly layer(s) and insulation layer(s) – including
used. It may be referred scooped part such as a cavity
to from board data.
Land definition Shape of land (pad)
Via definition Diameter of via (pad stack) and land shape
in each layer
Device definition Pin and package shape of embedding device
Basic pattern Usable pattern elements in the defined data
information types of figures are the same as in board
data
User expandable Arbitrarily expandable data of the format
information user "Definition" = "Value" can be arbitrarily
defined
2) Data structure
The data structure of this format is based on the board data shown in Figure 8. Repeatedly
used data information is formalized and it is possible to identify definition data. The data
expandable by users can be added to the board data and definition data.
– 18 – IEC 62878-2-5:2019 © IEC 2019
Figure 8 – Data structure
4.4.2 File structure
File structure is either of the following two methods.
1) Each definition data and board data are stored in one file as shown Figure 9
(recommended).
2) Definition data are stored in a separate file as shown in Figure 10.
Figure 9 – One file structure (recommended)
Figure 10 – Two file structure
4.5 3D expression
4.5.1 General
The format is expressed in 3D coordinates. 3D coordinate expression is a space expressed by
three diagonal axes, X, Y and Z.
4.5.2 Coordinates
The coordinates of this format are shown in Figure 11 and have the following definitions.
1) Rotation of an axis is anticlockwise.
2) Selection of unit length may be selected from mm, µm and nm.
3) Directions of axes are horizontal direction for x-axis, side direction for y-axis and vertical
(height/thickness) direction for z-axis.
– 20 – IEC 62878-2-5:2019 © IEC 2019
Figure 11 – Definition of coordinates
4.5.3 Position description
The specification of a 3D position is available as shown in Figure 12 to indicate layer structure
and 3D coordination. The directions of the axes can be expressed in a horizontal direction for the
x-axis, a side direction for the y-axis and a height direction for the z-axis.
Figure 12 – Position definition
4.5.4 Relation between coordinate origin and board position
There is no specified relation between coordinates origin [(x, y, z) = (0, 0, 0)] and the board
position as shown in Figure 13.
Figure 13 – Relation between coordinates and board position
4.6 Layer concept
There are two types of layers: the conductor layer and the virtual layer, as illustrated in Figure 14.
Characteristics of layers are explained below. The conductor layer is the layer coinciding with
the terminals of an embedding component and a conducting layer. The conductor layer with
internal posts that can be connected to the embedded device is the embedding layer. This
concept is not applicable to the embedding of a device that is not connected to a conductor layer,
such as via connection. The virtual layer is considered as an imaginally conductor layer at
interconnection points of an embedded component.
This format can maintain coordinate data and design data in both of layer base and the 3D Z-axis
base design. It is recommended to maintain the layer-based data when the board structure
information is required in IEC TS 62678-2-3. Use of 3D Z-coordinate base can be used for
describing design data such as that for the SiP, which may not be an appropriate use of the
above structure. The 3D Z-coordinate base may not be appropriate to describe information
necessary in the production process. Additional information transfer other than defined the
present format data may be necessary between processes (among designs and design to
production) and efficiency may be lowered in design and production.
Figure 14 – Layer concept
4.7 Substrate data
4.7.1 General
As shown in Figure 8, board data are composed of nine information. Each type of information
listed below is defined from 4.7.2 to 4.8.6.
1) Layer map information
2) Device arrangement information
– 22 – IEC 62878-2-5:2019 © IEC 2019
3) Basic forms
4) Net information
5) Artwork information
6) Package information
7) External port information
8) Internal port information
9) User data expansion information
4.7.2 Layer map information
This information maintains the relation between inner and outer layers as devices are mounted
and embedded, as shown in Figure 15 and Figure 16.
1) Information of mounting layers
The information shows connections in each mounting layer and mounting direction.
Device is embedded in layer = L1 (conductor layer), and connected in L1
Device is embedded in layer = L3 (conductor layer), and connected in L3
Device is embedded in layer = L2 (conductor layer), and connected in L2-U11 (virtual layer)
Figure 15 – Layer construction
2) Simplified layer construction
Logic layers for embedding devices and for boards are combined in cases where the layer
map information is simplified. It is possible only in the case where there is only one logic
layer of the same type in one physical layer.
IEC
...
Frequently Asked Questions
IEC 62878-2-5:2019 is a standard published by the International Electrotechnical Commission (IEC). Its full title is "Device embedding assembly technology - Part 2-5: Guidelines - Implementation of a 3D data format for device embedded substrate". This standard covers: IEC 62878-2-5:2019 specifies requirements based on XML schema that represents a design data format for device embedded substrate, which is a board comprising embedded active and passive devices whose electrical connections are made by means of a via, electroplating, conductive paste or printing of conductive material. This data format is to be used for simulation (e.g. stress, thermal, EMC), tooling, manufacturing, assembly, and inspection requirements. Furthermore, the data format is used for transferring information among printed board designers, printed board simulation engineer, manufacturers, and assemblers. IEC 62878-2-5:2019 applies to substrates using organic material. It neither applies to the re-distribution layer (RDL) nor to the electronic modules defined as M-type business model in IEC 62421.
IEC 62878-2-5:2019 specifies requirements based on XML schema that represents a design data format for device embedded substrate, which is a board comprising embedded active and passive devices whose electrical connections are made by means of a via, electroplating, conductive paste or printing of conductive material. This data format is to be used for simulation (e.g. stress, thermal, EMC), tooling, manufacturing, assembly, and inspection requirements. Furthermore, the data format is used for transferring information among printed board designers, printed board simulation engineer, manufacturers, and assemblers. IEC 62878-2-5:2019 applies to substrates using organic material. It neither applies to the re-distribution layer (RDL) nor to the electronic modules defined as M-type business model in IEC 62421.
IEC 62878-2-5:2019 is classified under the following ICS (International Classification for Standards) categories: 31.180 - Printed circuits and boards; 31.190 - Electronic component assemblies. The ICS classification helps identify the subject area and facilitates finding related standards.
IEC 62878-2-5:2019 has the following relationships with other standards: It is inter standard links to IEC PAS 62878-2-5:2015. Understanding these relationships helps ensure you are using the most current and applicable version of the standard.
You can purchase IEC 62878-2-5:2019 directly from iTeh Standards. The document is available in PDF format and is delivered instantly after payment. Add the standard to your cart and complete the secure checkout process. iTeh Standards is an authorized distributor of IEC standards.
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