Device embedding assembly technology - Part 2-9: Guidelines - Concept of JISSO level in the electronic assembly technology industries

IEC TR 62878-2-9:2022(E) comprises the long-term discussion among Jisso International Council (JIC) members during 1999 and 2005, when the interim agreement among all JIC members about the “concept of Jisso” as well as the “Jisso product level” for the common understanding on IEC TC 91 (electronic assembly technology) activities was reached. Further discussion on “Jisso Product Level” could be needed among the current JIC members to finalize it in the near future based on this technical report.

General Information

Status
Published
Publication Date
26-Apr-2022
Current Stage
PPUB - Publication issued
Completion Date
27-Apr-2022
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IEC TR 62878-2-9
Edition 1.0 2022-04
TECHNICAL
REPORT
colour
inside
Device embedding assembly technology –
Part 2-9: Guidelines – Concept of JISSO Level in the electronic assembly
technology industries
IEC TR 62878-2-9:2022-04(en)
---------------------- Page: 1 ----------------------
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---------------------- Page: 2 ----------------------
IEC TR 62878-2-9
Edition 1.0 2022-04
TECHNICAL
REPORT
colour
inside
Device embedding assembly technology –
Part 2-9: Guidelines – Concept of JISSO Level in the electronic assembly
technology industries
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 31.180; 31.190 ISBN 978-2-8322-1104-2

Warning! Make sure that you obtained this publication from an authorized distributor.

® Registered trademark of the International Electrotechnical Commission
---------------------- Page: 3 ----------------------
– 2 – IEC TR 62878-2-9:2022 © IEC 2022
CONTENTS

FOREWORD ........................................................................................................................... 3

INTRODUCTION ..................................................................................................................... 5

1 Scope .............................................................................................................................. 6

2 Normative references ...................................................................................................... 6

3 Terms .............................................................................................................................. 6

4 Historical Concept of Jisso (JISSO) ................................................................................. 6

4.1 Some examples of terms on Jisso/JISSO used in the past ...................................... 6

4.2 JISSO level versus Packaging Level (Interconnecting Level) .................................. 8

4.2.1 JISSO Level (typical) ....................................................................................... 8

4.2.2 Packaging Level .............................................................................................. 8

5 Concept of typical terms and description on JISSO Level ................................................ 9

5.1 JISSO/Jisso ............................................................................................................ 9

5.2 JISSO Level 0 – Intellectual information ................................................................ 10

5.3 JISSO Product Level 1 – Electronic element ......................................................... 10

5.4 JISSO Product Level 2 – Electronic package ........................................................ 12

5.5 JISSO Product Level 3 – Electronic module .......................................................... 12

5.6 JISSO Product Level 4 – Electronic unit ................................................................ 13

5.7 J ISSO Product Level 5 – Electronic system.......................................................... 14

Bibliography .......................................................................................................................... 15

Figure 1 – Concept of Jisso/JISSO ......................................................................................... 7

Figure 2 – Relation between JISSO Level versus Packaging Level ......................................... 9

Figure 3 – JISSO Level Concept (1) preliminarily introduced by JNAC in 2004 ........................ 9

Figure 4 – JISSO Level Concept (2) ...................................................................................... 10

Figure 5 – Examples of JISSO Product Level 1 – Electronic element .................................... 11

Figure 6 – Examples of JISSO Product Level 2 – Electronic package .................................... 12

Figure 7 – Examples of JISSO Product Level 3 – Electronic module ..................................... 13

Figure 8 – Example of JISSO Product Level 4 – Electronic unit ............................................. 14

Figure 9 – Examples of JISSO product Level 5 – Electronic system ...................................... 14

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IEC TR 62878-2-9:2022 © IEC 2022 – 3 –
INTERNATIONAL ELECTROTECHNICAL COMMISSION
____________
DEVICE EMBEDDING ASSEMBLY TECHNOLOGY –
Part 2-9: Guidelines – Concept of JISSO Level in the electronic
assembly technology industries
FOREWORD

1) The International Electrotechnical Commission (IEC) is a worldwide organization for standardization comprising

all national electrotechnical committees (IEC National Committees). The object of IEC is to promote international

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IEC TR 62878-2-9 has been prepared by IEC technical committee 91: Electronics assembly

technology. It is a Technical Report.
The text of this Technical Report is based on the following documents:
Draft Report on voting
91/1703/DTR 91/1769/RVDTR

Full information on the voting for its approval can be found in the report on voting indicated in

the above table.
The language used for the development of this Technical Report is English.
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– 4 – IEC TR 62878-2-9:2022 © IEC 2022

This document was drafted in accordance with ISO/IEC Directives, Part 2, and developed in

accordance with ISO/IEC Directives, Part 1 and ISO/IEC Directives, IEC Supplement, available

at www.iec.ch/members_experts/refdocs. The main document types developed by IEC are

described in greater detail at www.iec.ch/standardsdev/publications.

A list of all parts in the IEC 62878 series, published under the general title Device embedding

assembly technology, can be found on the IEC website.

The committee has decided that the contents of this document will remain unchanged until the

stability date indicated on the IEC website under webstore.iec.ch in the data related to the

specific document. At this date, the document will be
• reconfirmed,
• withdrawn,
• replaced by a revised edition, or
• amended.

IMPORTANT – The "colour inside" logo on the cover page of this document indicates

that it contains colours which are considered to be useful for the correct understanding

of its contents. Users should therefore print this document using a colour printer.

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IEC TR 62878-2-9:2022 © IEC 2022 – 5 –
INTRODUCTION

The term and definition of JISSO Level had been developed originally at the sixth Jisso

International Council (JIC) meeting held in Herndon VA, USA in May 2005 among the experts

from North America, Europe and Japan on assembly/packaging technology involving
semiconductors, passive devices, PWB, their materials and board design.

The term “JISSO” stands for “total solution for interconnecting, assembling, packaging,

mounting and integrating system design for system integration”.

JIC started at the Headquarter of IPC in Chicago, USA in 2000 according to the agreement

made by TC 91 (Electronics assembly technology, Chairman: the late Mr. Dieter Bergman) and

IEC SC 47D (Semiconductor device packaging, Chairman: the late Mr. Martin G. Freedman)

based on the proposal made by JNC members of TC 91 and SC 47D (Mr. Katsumi Yamamoto

and Mr. Hisao Kasuga) at the 63th IEC General meeting in Kyoto in 1999.

Restructuring on JIC activities was discussed at the 14 JIC meeting held in Seoul, S. Korea

in April 2013 with the following conclusion:

The purpose of this council is to provide a platform to enable a strategic collaboration among

stakeholders that create benefits along the value chain of interconnecting, assembling,

packaging, mounting, integrating system design, and focused technologies by increasing global

awareness.

To accomplish these objectives, members will collaborate to evaluate technology and market

trends, to identify and address gaps not publicly recognized, and to provide inputs or potential

solutions to the electronic industry, academia, standardization bodies and regulatory institutions.

These activities will be undertaken in a spirit of responsibility to the worldwide electronic

industry.
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– 6 – IEC TR 62878-2-9:2022 © IEC 2022
DEVICE EMBEDDING ASSEMBLY TECHNOLOGY –
Part 2-9: Guidelines – Concept of JISSO Level in the electronic
assembly technology industries
1 Scope

The purpose of this Technical Report is to comprise the long-term discussion among Jisso

International Council (JIC) members during 1999 and 2005, when the interim agreement among

all JIC members about the “concept of Jisso” as well as the “Jisso product level” for the common

understanding on IEC TC 91 (electronic assembly technology) activities was reached.

Further discussion on “Jisso Product Level” could be needed among the current JIC members

to finalize it in the near future based on this technical report.
2 Normative references
There are no normative references in this document.
3 Term
...

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