ISO/IEC 11518-9:1999

Information technology - High-Performance Parallel Interface - Part 9: Serial Specification (HIPPI-SERIAL)

Defines a physical-level interface for transmitting digital data at 800 Mbit/s or 1 600 Mbit/s serially over fibre-optic cables across distances of up to 10 km. The signalling sequences and protocol used are compatible with HIPPI-PH, ISO/IEC 11518-1, which is limited to 25 m distances. HIPPI-Serial may be integrated as a host's native interface, or used as an external extender for HIPPI-PH ports.

General Information

• Status: Published
• Publication Date: 22-Apr-1999
• ICS: 35.200 - Interface and interconnection equipment
• Technical Committee: ISO/IEC JTC 1/SC 25 - Interconnection of information technology equipment
• Current Stage: PPUB - Publication issued
• Start Date: 23-Apr-1999
• Completion Date: 28-Feb-1999

Overview

ISO/IEC 11518-9:1999 - Information technology: High-Performance Parallel Interface, Part 9: Serial Specification (HIPPI-Serial) defines the physical-layer specification for sending HIPPI data serially over fibre-optic links. The standard supports 800 Mbit/s (32-bit, 100 MByte/s) and 1 600 Mbit/s (64-bit, 200 MByte/s) operation, distances up to 10 km, and signalling compatible with HIPPI-PH (ISO/IEC 11518-1). HIPPI-Serial can be implemented as a host-native interface or as an external extender for HIPPI-PH ports.

Key topics and technical requirements

• Data framing and encoding: Defines a 24-bit frame composed of a 20-bit data field plus a 4-bit coding nibble. Encoding rules for data, control (F0/F1), and overhead (M0/M1) are specified to preserve HIPPI-PH semantics.
• Serialisation and link architecture: Details Transmitter Link Interface (TLI), receiver sections, SUBMUX/SUBDEMUX functional units and timing/clocking requirements for serial operation.
• Link control and reset: Specifies signalling sequences for link initialization, automatic link reset, and debounced control handling for robust low‑latency operation.
• Optical interface: Optical specifications include support for long‑wavelength and short‑wavelength optics, single‑mode and multi‑mode fibre options, connector guidance, eye‑mask and optical measurements relevant to receiver sensitivity and return loss.
• Simplex/duplex and configurations: Supports simplex and dual‑simplex configurations, and can be used point-to-point as an integrated interface or as an extender to extend HIPPI-PH beyond 25 m.
• Robustness and testability: Includes normative references and annexes for implementation suggestions, optical test practices (FOTP/OFSTP), eye measurements, loss budget examples and loopback/test procedures.

Applications and users

• HPC and supercomputing vendors implementing HIPPI host interfaces or interconnects where legacy HIPPI traffic needs to be carried over longer distances.
• Storage system and SAN appliance designers requiring low‑latency, high‑bandwidth links between hosts and storage arrays.
• Optical transceiver and subsystem manufacturers building HIPPI‑Serial compliant modules, SUBMUX/SUBDEMUX units and extender products.
• System integrators and test labs performing interoperability testing, optical link budgeting and compliance verification.

Related standards

• ISO/IEC 11518-1 (HIPPI‑PH) - mechanical, electrical and signalling protocol
• ISO/IEC 11518 (other parts: HIPPI-FP, HIPPI-LE, HIPPI-ATM, etc.)
• ITU‑T G.652 (single-mode fibre characteristics)
• IEC 61300 series and IEC 61280 series (fibre test and measurement practices)

Keywords: ISO/IEC 11518-9:1999, HIPPI-Serial, HIPPI-SERIAL, HIPPI-PH, high-performance parallel interface, serial fibre-optic, 800 Mbit/s, 1600 Mbit/s, SUBMUX, SUBDEMUX, 24-bit frame, optical interface.

Standards Content (Sample)

INTERNATIONAL
ISO/IEC
STANDARD
11518-9
First edition
1999-04
Information technology –
High-Performance Parallel Interface –
Part 9:
Serial Specification (HIPPI-Serial)
Reference number
INTERNATIONAL
ISO/IEC
STANDARD
11518-9
First edition
1999-04
Information technology –
High-Performance Parallel Interface –
Part 9:
Serial Specification (HIPPI-Serial)
 ISO/IEC 1999
All rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized in any form or by any
means, electronic or mechanical, including photocopying and microfilm, without permission in writing from the publisher.
ISO/IEC Copyright Office Case postale 56 CH-1211 Genève 20 Switzerland
• • •
PRICE CODE
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For price, see current catalogue

11518-9 © ISO/IEC:1999(E)
CONTENTS
Page
FOREWORD .iii
INTRODUCTION .iv
Clause
1 Scope.1
2 Normative references.1
3 Definitions and conventions. 2
3.1 Definitions. 2
3.2 Editorial conventions. 4
3.3 Acronyms and other abbreviations .4
4 System overview.4
4.1 Functional units . 5
4.3 Non-HIPPI-PH control signals, OHn (Overhead bits). 6
4.4 Serial data input and output. 6
4.5 Configurations . 6
5 Transmit section . 6
5.1 Encoding the 20-bit data fields . 6
5.2 Encoding F0, F1 with REQUEST, PACKET, and BURST. 6
5.3 Encoding M0, M1 with CONNECT, READY, and OHn. 7
5.5 Transmit section clock signals. 10
6 Receive section. 11
6.1 Receive section clock signals. 11
6.2 Operating on the 24-bit frames. 11
6.3 Decoding 20-bit data fields . 12
6.4 Decoding F0, F1 into REQUEST, PACKET, and BURST . 12
6.5 Decoding M0, M1 into CONNECT, READY, and OHn. 12
7 Link Control.13
7.1 Link Control output signals . 13
7.2 Link Control input signals . 13
7.3 Link reset.13
8 Serial optical interface. 14
8.1 General specifications.14
8.2 Fibre type.15
8.3 Optical connectors.15
Serial Specification (HIPPI-Serial) i

11518-9 © ISO/IEC:1999(E)
Tables
Table 1 – 20-bit data field structure . 7
Table 2 – REQUEST, PACKET and BURST coding in F0 and F1 . 7
Table 3 – M0, M1 contents . 7
Table 4 – Overhead bit (OHn) functions . 8
Table 5 – Overhead bit 1 (OH1) coding. 8
Table 7 – General long wavelength optical specifications over single-mode fibre. 15
Table 8 – General long wavelength optical specifications over multimode fibre . 16
Table 9 – General short wavelength optical specifications . 16
Figures
Figure 1 – 32-bit, dual-simplex, HIPPI-Serial functional units example . 5
Figure 2 – Link reset state diagram . 13
Figure 3 – Transmitter eye diagram mask . 15
Figure A.1 – SUBMUX block diagram. 18
Figure A.2 – SUBDEMUX block diagram. 18
Figure D.1 – Remote and local loopback. 24
Annexes
A Implementation suggestions. 17
A.1 Example SUBMUX circuit. 17
A.2 Example SUBDEMUX circuit. 17
A.3 TLI and RLI availability . 17
B Additional optical information. 19
B.1 Eye measurements with an oscilloscope. 19
B.2 Optical power. 19
B.3 Optical spectrum. 19
B.4 Eye safety. 19
B.5 Loss budget examples. 19
C HIPPI-PH signal relationships . 21
C.1 REQUEST, PACKET, and BURST . 21
C.2 Control signals during errors . 21
D HIPPI-PH Extender . 23
D.1 HIPPI-PH signals. 23
D.2 HIPPI-Serial Extender loopbacks . 23
D.3 HIPPI-Serial Extender front panel user interface .25
E Bibliography. 26
ii Serial Specification (HIPPI-Serial)

11518-9 © ISO/IEC:1999(E)
Information technology –
High-Performance Parallel Interface –
Part 9:
Serial Specification (HIPPI-Serial)
Foreword
ISO (the International Organization for Standardization) and IEC (the International
Electrotechnical Commission) form the specialized system for worldwide
standardization. National bodies that are members of ISO or IEC participate in
the development of International Standards through technical committees
established by the respective organization to deal with particular fields of
technical activity. ISO and IEC technical committees collaborate in fields of
mutual interest. Other international organizations, governmental and non-
governmental, in liaison with ISO and IEC, also take part in the work.
In the field of information technology, ISO and IEC have established a joint
technical committee, ISO/IEC JTC 1. Draft International Standards adopted by
the joint technical committee are circulated to national bodies for voting.
Publication as an International Standard requires approval by at least 75% of the
national bodies casting a vote.
International Standard ISO/IEC 11518-9 was prepared by subcommittee 25:
Interconnection of information technology equipment, of ISO/IEC Joint Technical
Committee 1: Information technology.
ISO/IEC 11518 consists of the following parts, under the general title Information
technology – High-Performance Parallel Interface:
– Part 1: Mechanical, electrical, and signalling protocol specification
(HIPPI-PH)
– Part 2: Framing Protocol (HIPPI-FP)
– Part 3: Encapsulation of ISO/IEC 8802-2 (IEEE Std 802.2) Logical Link
Control Protocol Data Units (HIPPI-LE)
– Part 4: Mapping of HIPPI to IPI device generic command sets (HIPPI-IPI)
– Part 5: Memory Interface (HIPPI-MI)
– Part 6: Physical Switch Control (HIPPI-SC)
– Part 8: Mapping to Asynchronous Transfer Mode (HIPPI-ATM)
– Part 9: Serial Specification (HIPPI-Serial)
Annexes A to E of this part of ISO/IEC 11518 are for information only.
Serial Specification (HIPPI-Serial) iii

11518-9 © ISO/IEC:1999(E)
Introduction
This High-Performance Parallel Interface, Serial Specification (HIPPI-Serial),
defines a physical-level interface for transmitting digital data at 800 Mbit/s or
1 600 Mbit/s serially over fibre-optic cables across distances of up to 10 km. The
signalling sequences and protocol used are compatible with HIPPI-PH,
ISO/IEC 11518-1, which is limited to 25 m distances. HIPPI-Serial may be
integrated as a host’s native interface, or used as an external extender for HIPPI-
PH ports.
Characteristics of a HIPPI Serial interface include:
– Point-to-point connections use one or two pairs of fibre-optic cables for
distances of up to 10 km.
– Long wavelength and short-wavelength optics options.
– May be used in a simplex or duplex configuration.
– Support for 800 Mbit/s or 1 600 Mbit/s data rates.
– Use as an integrated host interface without an intervening HIPPI-PH is
supported.
– Use as an external extender for HIPPI-PH ports is supported.
– The coding scheme provides low-latency, automatic link reset, and robust
operation.
iv Serial Specification (HIPPI-Serial)

11518-9 © ISO/IEC:1999(E)
Information technology –
High-Performance Parallel Interface –
Part 9:
Serial Specification (HIPPI-Serial)
publication, the editions indicated were valid. All
1 Scope
standards are subject to revision, and parties to
agreements based on this part of ISO/IEC 11518
This part of ISO/IEC 11518 specifies a physical-
are encouraged to investigate the possibility of
level interface for transmitting digital data at
applying the most recent edition of the standards
800 Mbit/s or 1 600 Mbit/s serially over fibre-optic
listed below. Members of IEC and ISO maintain
cables across distances of up to 10 km. The
registers of currently valid International Standards.
signalling sequences and protocol used are
compatible with HIPPI-PH, ISO/IEC 11518-1,
ISO/IEC 11518-1:1995, High-Performance Parallel
which is limited to 25 m distances. HIPPI-Serial
Interface – Part 1: Mechanical, electrical, and
may be integrated as a host’s native interface, or
signalling protocol specification (HIPPI-PH)
used as an external extender for HIPPI-PH ports.
ISO/IEC 14165-111:199x, Fibre Channel –
Specifications are included for:
Part 111: Physical and Signalling Interface
– the encoding and serialisation of the parallel
(FC-PH)
data;
ITU-T G.652: Characteristics of a single mode
– the sequence of signals required for link
optical fibre cable
reset;
IEC 61300-3-6: Fibre optic interconnecting devices
– the timing and optical requirements of the
and passive components – Basic test and
serial signals;
measurement procedures – Part 3-6: Examina-
– 32-bit (800 Mbit/s, 100 MByte/s) and 64-bit
tions and measurements – Return loss
(1 600 Mbit/s, 200 MByte/s) operation;
IEC 61280-1-3: Fibre optic communication sub-
– simplex and dual simplex operation.
system basic test procedures – Part 1-3: Test
procedures for general communication sub-
systems – Central wavelength and spectral width
measurement
2 Normative references
IEC 61280-2-1: Fibre optic communication sub-
system basic test procedures – Part 2-1: Test
The following standards contain provisions which,
procedures for digital systems – Receiver
through reference in this text, constitute provisions
sensitivity and overload measurement
of this part of ISO/IEC 11518. At the time of
1 Serial Specification (HIPPI-Serial)

11518-9 © ISO/IEC:1999(E)
3 Definitions and conventions
3.1.9
debounced signal
A signal that has been converted from an
3.1 Definitions intermittent signal to a stable one. (See 7.2.)
For the purposes of this standard, the following
3.1.10
definitions apply.
Destination
A HIPPI-PH Destination.
3.1.1
attenuation
3.1.11
The power loss expressed in units of dB.
extinction ratio
The ratio, expressed in units of dB of the low, or
“off” optical power level (PL), to the high, or “on”
3.1.2
optical power level (PH), when the station is
average power
transmitting valid information.
The optical power measured using an average
reading power meter when transmitting continuous
valid information.
3.1.12
fibre-optic test procedure (FOTP)
Standards developed and published by the
3.1.3
Electronic Industries Association (EIA) under the
bit error rate (BER)
EIA-RS-455 series of standards.
The statistical probability of a transmitted bit being
erroneously received in a communication system.
The BER is measured by counting the number of 3.1.11
erroneous bits at the output of the receiver and
fibre plant
dividing by the total number of bits.
All of the optical elements, for example, fibre,
connectors, splices, etc., between an optical
transmitter and an optical receiver.
3.1.4
B0-B19
3.1.14
Bits in the 20-bit data field.
frame
24 bits consisting of a 20-bit data field and 4-bit
3.1.5
coding nibble.
centre wavelength (laser)
The nominal value of the central operating wave-
3.1.15
length, defined by a peak mode measurement.
(See IEC 61280-1-3.)
functional unit
A functional partition of the entire system.
Partitioning is for the purpose of explanation only.
3.1.6
Implementers are free to combine or divide
coding nibble
functional units.
The 4 bits appended to a 20-bit data field to form a
frame. They signal data inversion, indicate fill
frames, and supply the Master Transition.
3.1.16
HIPPI-PH
High-Performance Parallel Interface – Mechanical,
3.1.7
Electrical, and Signalling Protocol Specification
D0-D31, D32-D63
(HIPPI-PH), ISO/IEC 11518-1. Data is transmitted
Bits in the 32-bit, and extension for 64-bit, parallel
in parallel over copper twisted-pair cables.
HIPPI word.
3.1.17
3.1.8
HIPPI port
data field
A HIPPI-PH Source or Destination.
The 20-bit data portion of a 24-bit frame.
Serial Specification (HIPPI-Serial) 2

11518-9 © ISO/IEC:1999(E)
3.1.18 3.1.26
link Source
One way serial connection between HIPPI-Serial A HIPPI-PH Source.
devices.
3.1.27
spectral width (RMS)
3.1.19
The root mean square (RMS) width of the Active
Master Transition
Output interface optical spectrum.
A bit transition that always appears between the
(See IEC 61280-1-3.)
second and third bits of the coding nibble.
3.1.28
3.1.20
SUBMUX, SUBDEMUX
mean launch power
Functional units that combine (extract) the
The average optical power for a continuous valid
CONNECT, READY, and Overhead bits for trans-
information stream coupled into a fibre.
mission across the serial links as bits M0 and M1.
3.1.21
3.1.29
Optical Fibre System Test Practice (OFSTP)
time slot
Standards developed and published by the
a contiguous group of 16 frame pairs. Note that a
Electronics Industries Association (EIA) under the
frame pair contains one 40-bit word.
EIA/TIA-526 series of standards.
3.1.30
3.1.22
Transmitter Link Interface (TLI)
optical return loss
A functional unit that encodes and serialises 20-bit
The ratio (expressed in units of dB) of optical
data fields, preparing them for serial transmission.
power reflected by a component or an assembly to
the optical power incident on a component port
3.1.31
when that component or assembly is introduced
into a link or system. unit
(See IEC 61300-3-6 method 1.) See functional unit.
3.1.32
3.1.23
optional XDEMUX
Characteristics that are not required by HIPPI- A functional unit that decodes two 20-bit data fields
Serial. However, if any optional characteristic is into HIPPI data and control signals.
implemented, it shall be implemented as defined in
HIPPI-Serial.
3.1.33
XMUX
3.1.24 A functional unit that encodes the HIPPI data and
Overhead bit (OH1-OH8) control signals into two 20-bit data fields.
A bit, local to the HIPPI-Serial hardware, which is
transmitted along with the HIPPI-PH data over the
serial link to provide extra capacity for control and
maintenance functions.
3.1.25
Receiver Link Interface (RLI)
A functional unit that deserialises and decodes the
serial input data into 20-bit data fields.
3 Serial Specification (HIPPI-Serial)

11518-9 © ISO/IEC:1999(E)
4 System overview
3.2 Editorial conventions
In this standard, certain terms that are proper
The HIPPI-Serial provides a serial communication
names of signals or similar terms are printed in
facility for HIPPI. The primary purpose of HIPPI-
uppercase to avoid possible confusion with other
Serial is to extend the physical range of HIPPI
uses of the same words (e.g. FLAG). Any lower-
beyond 25 m. A secondary purpose is to replace
case uses of these words have the normal
the parallel HIPPI-PH cable and connectors with a
technical English meaning.
fibre-optic cable.
A number of conditions, sequence parameters,
The primary characteristics of HIPPI-Serial are:
events, states or similar terms are printed with the
first letter of each word in uppercase and the rest
Signalling Rate 1,2 GBaud
lowercase (e.g. State, Source). Any lowercase
Maximum station separation: 10 km
uses of these words have the normal technical
-12
Bit-Error Rate ≤10
English meaning.
64-Bit ( 1 600 Mbit/s) HIPPI supported by two
HIPPI-Serials in parallel
The word shall, when used in this standard,
HIPPI simplex or dual simplex operation
states a mandatory rule or requirement. The word
should, when used in this standard, states a
Since error rates are specified to be at or below
recommendation.
-12
10 , forward error correction, error correcting
codes and CRCs are not addressed in this
specification. If additional error detection is
3.3 Acronyms and other abbreviations
deemed necessary, it shall be included as part of
the higher-level protocols.
BER bit error rate
dB decibel
4.1 Functional units
dBm decibel (relative to 1 mW power)
Figure 1 is an example showing functional unit
FOTP Fibre Optic Test Procedure
building blocks that may be used in a HIPPI-Serial
HIPPI High-Performance Parallel Interface
implementation. This specification is written in
LLRC Length/Longitudinal Redundancy
terms of the functional units shown in figure 1.
Checkword
However, implementers are free to split or
ns nanoseconds
combine functions as they choose. This document
nm nanometers
does not intend to specify any of the interfaces
OFSTP Optical Fibre System Test Practice
between functional units. The only requirement for
phase locked loop
PLL
compatibility is that the external functionality, at the
PRBS pseudo random bit sequence
serial optical interfaces, conform to the overall
RIN relative intensity noise
functionality specified in this document.
RLI Receiver Link Interface
RMS root mean square
4.2 HIPPI-PH signals
SUBMUX Sub Multiplexer
The HIPPI-PH Source and Destination signals
SUBDEMUX Sub De-Multiplexer
shown in figure 1 shall conform to the signalling
TLI Transmitter Link Interface
protocol specified in ISO/IEC 11518-1, HIPPI-PH.
UI Unit interval = 1 bit period
These HIPPI-PH signals do not need to conform to
XDEMUX Receive De-Multiplexer
the HIPPI-PH mechanical and electrical specifi-
XMUX Transmit Multiplexer
cations. The HIPPI-PH INTERCONNECT signals
μs microseconds
shall not be transported over the serial link to the
Ω ohms
remote end.
Serial Specification (HIPPI-Serial) 4

11518-9 © ISO/IEC:1999(E)
HIPPI-PH
Source signals
XMUX TLI
25 MHz
25 MHz
CLOCK
Strobe
DATA
D31.D0
P3.P0
PARITY
FLAG
REQUEST
Serial
F0
Encode
PACKET
Data
F1
BURST (1,2 GBaud)
Data Field
(B19.B0)
CONNECT
and READY
TLI_UNLOCK
SEND_DATA
M0
2 SUBMUX SEND_FF0
M1
SEND_FF1
Non-HIPPI-PH
Control signals
OH1.OH8
Link
OH1.OH8
Control
RLI
XDEMUX
FF0_DET
M0
SUBDEMUX FF1_DET
M1
FE_DET
HIPPI-PH
Destination signals
DATA_DET DATA_DET
CONNECT
Data Field
and READY
(B19.B0)
Serial
REQUEST
F0 FLAG Data
Decode
PACKET
F1 (1,2 GBaud)
BURST
DATA
D31.D0
P3.P0
PARITY
50 MHz
50 MHz
25 MHz
Clock
Strobe
CLOCK
Figure 1 – 32-bit, dual-simplex, HIPPI-Serial functional units example
5 Serial Specification (HIPPI-Serial)

11518-9 © ISO/IEC:1999(E)
4.3 Non-HIPPI-PH control signals, OHn
5 Transmit section
(Overhead bits)
The Overhead bits, OH1 - OH8, provide a framing
The transmit section consists of the Encode,
function and some optional end-to-end status and
SUBMUX, XMUX, and Transmitter Link Interface
control capability that is outside the scope of
(TLI) functional units shown in the top portion of
HIPPI-PH. See 5.3.1 for details of the Overhead
figure 1. The transmit section encodes parallel
bits.
signals into a DC balanced serial stream.
5.1 Encoding the 20-bit data fields
4.4 Serial data input and output
40-bit words consisting of 32 bits of HIPPI-PH
The 1,2 GBaud serial data stream defined in this
data, 4 bits of HIPPI-PH parity, F0, F1, M0, and
specification is the interoperability point between
M1, shall be split into two 20-bit data fields. In
different implementations.
figure 1 this function is called the XMUX. A FLAG
signal shall be used to identify the first 20-bit data
field from the second 20-bit data field. Table 1
4.5 Configurations
specifies the bit assignments in the 20-bit data
fields, and the associated FLAG values. The 20-
4.5.1 Dual-simplex and simplex
bit data field with FLAG = 0 shall be transmitted
before the related 20-bit data field with FLAG = 1.
Figure 1 shows a 32-bit dual-simplex HIPPI-Serial
configuration. One fibre cable carries data and
NOTE – The bit arrangement in table 1 reduces the
control signals from the HIPPI-PH Source, and
possibility of corrupted data being identified as good
return direction CONNECT and READY signals to data. The HIPPI-PH parity bits cover a byte of
adjacent data bits (e.g. P0 covers D0 - D7). By
the HIPPI-PH Destination. The other cable
scattering the HIPPI-PH data and parity bits in the
carries the reverse direction signals. This uses a
20-bit fields, a noise hit corrupting up to seven
pair of links.
adjacent data field bits in the serial stream will be
detected as a HIPPI-PH parity error.  Corrupted bits
Simplex operation may be achieved by ignoring
in the coding nibble, will also be detected as errors.
the unused HIPPI-PH signals, or setting them to
zeros. The recovered HIPPI-PH CLOCK signal
32-bit (800 Mbit/s) HIPPI-Serial variants shall use
on the active side shall be used to drive the
one link as shown in figure 1, and shown as link
HIPPI-PH Source CLOCK signal on the unused
“a” in table 1.
side.
64-bit (1 600 Mbit/s) HIPPI-Serial variants shall
4.5.2 32-bit and 64-bit systems
use two separate physical links in parallel; these
are called links “a” and “b” in table 1. The serial
32-bit (800 Mbit/s) HIPPI-Serial implementations
data streams on links “a” and “b” shall be time
shall use a pair of links and two fibres as shown
aligned within 2 ns at the transmitter.
in figure 1. 64-bit (1 600 Mbit/s) HIPPI-Serial
implementations shall use two link-pairs shown in
figure 1, and four fibres. See 5.1, 6.3, 6.4 and 6.5
5.2 Encoding F0, F1 with REQUEST, PACKET,
for details of the information on the separate links
and BURST
of a 64-bit implementation. See 7.3 for details of
the 64-bit dual-link reset operations.
The HIPPI-PH REQUEST, PACKET and BURST
control signals shall be encoded into the F0 and
4.5.3 HIPPI-Serial extenders
F1 bits as shown in table 2. (See annex C.1 for
descriptions of these HIPPI-PH signals.)
An external extender for copper-cable-based
HIPPI-PH ports is described in annex D.
Serial Specification (HIPPI-Serial) 6

11518-9 © ISO/IEC:1999(E)
Table 1 – 20-bit data field structure
Link - Data field bit Bn
FLAG 0 123456789 10 11 12 13 14 15 16 17 18 19
a - 0 D00 D08 D16 D24 D01 D09 D17 D25 D02 D10 D18 D26 D03 D11 F0 D19 D27 P0 P1 F1
a - 1 P2 P3 D04 D12 D20 D28 D05 D13 D21 D29 D06 D14 D22 D30 M0 D07 D15 D23 D31 M1
b - 0 D32 D40 D48 D56 D33 D41 D49 D57 D34 D42 D50 D58 D35 D43 F0 D51 D59 P4 P5 F1
b - 1 P6 P7 D36 D44 D52 D60 D37 D45 D53 D61 D38 D46 D54 D62 '0' D39 D47 D55 D63 '0'
Link: a/b denotes separate physical links. a is used individually for 800 Mbit/s operation,
a and b are used together for 1 600 Mbit/s operation.
FLAG: 0/1 is derived from the coding nibble and is used to differentiate the first and second
20-bit data fields of a 40-bit word.
Dnn = HIPPI data bit
Pn = HIPPI parity bit
F0, F1 = REQUEST, BURST, and PACKET encoding (see 5.4 and table 2)
M0, M1 = Submultiplexed CONNECT, READY, and Overhead signals (see 5.5)
Table 2 – REQUEST, PACKET and BURST Table 3 – M0, M1 contents
coding in F0 and F1
Relative MO M1
40-bit word contents contents
HIPPI-PH signals Code
0 READY a CONNECT a
REQUEST PACKET BURST F1 F0 State
1 READY a CONNECT a
00 0 00Idle
2 READY a CONNECT a
1 0 0 0 1 Request
3 OH5 OH1
1 1 0 1 0 Packet
4 READY b CONNECT b
11 1 11Burst
5 READY b CONNECT b
00 1 00Idle
6 READY b CONNECT b
01 0 00Idle
7 OH6 OH2
01 1 00Idle
8 READY c CONNECT c
10 1 00Idle
9 READY c CONNECT c
10 READY c CONNECT c
11 OH7 OH3
5.3 Encoding M0, M1 with CONNECT, READY,
12 READY d CONNECT d
and OHn
13 READY d CONNECT d
The M0 bits and M1 bits carry several lower-
bandwidth signals multiplexed together. Table 3 14 READY d CONNECT d
shows the signals, and their relative 40-bit words.
15 OH8 (Alt 0/1) OH4
An example circuit to generate the M0 and M1
signals is described in annex A.1 and shown in
figure A.1. This function is called the SUBMUX in
NOTE 1 – A pair of 20-bit data fields are transferred
figure 1.
over a link every 40 ns, corresponding to the
25 MHz HIPPI-PH CLOCK signal. For example, D0-
D31, P0-P3, REQUEST, PACKET, BURST, M0 and
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11518-9 © ISO/IEC:1999(E)
M1, are transmitted every 40 ns. At relative 40-bit OH bits 1 through 7 shall not mimic OH8. OH bits
word 0, M0 would have the first sample of “READY
1 through 7 shall each transmit a minimum of four
a”, 40 ns later (relative 40-bit word 1) M0 would
consecutive bits of the same state in every 8-time
have the second “READY a”, at 80 ns (relative 40-
slot period (5,12 μs).
bit word 2) M0 would have the third “READY a”, at
120 ns (relative 40-bit word 3) M0 would have the
NOTES
OH5 signal, etc. Relative 40-bit word 0 is not
1 Limiting the OH2 through OH7 bandwidth to a
synchronised with any specific HIPPI-PH signal
maximum of 195 kHz will meet this criteria. OH1
combination or transition, i.e., its location is
already meets the four consecutive bit criteria.
arbitrary.
2 The optional functions assigned seem appro-
Each of the three adjacent CONNECT or READY
priate for HIPPI-Serial Extenders as described in
bits (e.g. READY a, READY a, and READY a)
annex D, but may not be appropriate for HIPPI-
shall be transmitted with the same value.
Serial integrated in a workstation.
NOTE 2 – The HIPPI-PH CONNECT and READY
5.3.2 Overhead bit OH1 encoding
signals travel in the reverse direction from the data
and other HIPPI-PH signals, without a reference Table 5 defines the functions carried in optional
clock or checksum. To improve the reliability of the
Overhead bit 1 (OH1). Like M0 and M1, OH1
CONNECT and READY signals in HIPPI-Serial, they
carries lower bandwidth signals multiplexed in
are sent three times (e.g. the three READY a’s) and
time slots. If an optional function of OH1 is not
spaced 40 bits apart in the serial stream. Majority
used, then the default value shown in table 5 shall
voting logic at the receiver will correct most of the
be transmitted in that OH1 time slot.
serial steam M0 and M1 errors associated with the
CONNECT and READY signals.
Table 5 – Overhead bit 1 (OH1) coding
5.3.1 OHn (Overhead bits)
Time Default Opt/
Function
Slot Value Man
Table 4 lists the Overhead bits. If optional
Overhead bits are used, their functions shall be as
0 1 Man Framing
specified in table 4. If an optional function is not
1 1 Man Framing
used, then its bit shall be transmitted as the
default value shown in table 4. The OH8 bit shall 2 1 Man Framing
be an alternating 1/0 pattern to provide framing for
3 1 Man Framing
the Overhead bit stream.
4 0 Man Framing
Table 4 – Overhead bit (OHn) functions 5 0 Opt RL: Remote loopback
6 0 Opt PP: Parallel Parity Error
OH Default Opt/
7 0 Opt SP: Serial Parity Error
Function
Bit Value Man
Opt = Optional
OH1 0 Opt Link Status and Control
Man = Mandatory when OH1 is used
OH2 0 Opt Asynchronous channel
OH3 0 Opt Asynchronous channel
RL: Remote Loopback - (Optional) If one end of a
OH4 0 Opt Reserved
link desires the other end to go into remote
OH5 0 Opt Reserved loopback, it shall transmit bit RL as a 1. When
RL is received as a 1, the receiving node
OH6 0 Opt Vendor unique
should go into remote loopback. When in
OH7 1 Opt Vendor unique
remote loopback, all data received shall be
OH8 1/0 Man Framing (alternate 1/0) echoed back to the other end of the link,
including the RL signal itself. (This will
OH = Overhead
acknowledge that the link is in remote
Opt = Optional
loopback, and will allow the echoed data to be
Man = Mandatory
checked for errors.) RL is a level sensitive,
static signal. As long as it is 0, the link
operates normally. As long as it is received as
a 1, the node should echo all received data.
However, RL should be filtered to prevent
infrequent bit errors from falsely enabling
Serial Specification (HIPPI-Serial) 8

11518-9 © ISO/IEC:1999(E)
loopback. When an end initiates remote The Link Control functional unit controls the types
loopback, it shall not go into remote loopback of frames transmitted with the signals:
upon receiving RL = 1. For recommended
SEND_DATA: Transmit Data Frame
implementations of loopback, refer to
annex D.2. SEND_FF0: Transmit Fill Frame 0s
SEND_FF1: Transmit Fill Frame 1s
PP: Parallel Parity Error - (Optional) Any parity
errors detected on the Source HIPPI-PH data
DC balance shall be achieved by keeping the
should be flagged by transmitting PP as a 1.
number of 1s transmitted as close as possible to
PP shall be stretched to between 6 μs and 9 μs
the number of 0s transmitted. A running count
to guarantee transmission over the link. The
shall be kept of the number of 1s and 0s
status of PP should be made available at both
transmitted in the serial stream, counting the
the local and remote ends of the link.
DISPARITY counter up for each 1 transmitted,
Persistent parallel parity errors indicate a
and counting down for each 0 transmitted. The
problem with the HIPPI-PH Source port.
initialisation point for the DISPARITY counter shall
be when SEND_FF0 transitions from true to false.
SP: Serial Parity Error - (Optional) The parity of
the HIPPI-PH data should be checked once
NOTE – The DISPARITY counter can be imple-
again as it is delivered from the XDEMUX in
mented with an up/down counter with a range of
figure 1 to the HIPPI-PH Destination. An error
plus or minus 31.
at this point should be flagged by setting SP of
the transmit link to a 1. The status of SP
5.4.1 Transmit Data Frame
should be made available at the local end of
the link, and it should be transmitted back to
When SEND_DATA = true, and there is a 20-bit
the remote node if a duplex system is in use.
data field to transmit, then the TLI shall append a
SP shall be stretched to between 6 μs and 9 μs
4-bit coding nibble to the 20-bit data field; if FLAG
to guarantee transmission over the link.
= 0 then coding nibble = 1101, if FLAG = 1 then
Assuming the transmitted Parallel Parity Error
coding nibble = 1011.
signal (PP) is 0, persistent received Serial
Parity Errors (SP = 1) indicate a problem with
DC balance shall be achieved by keeping the
the serial transmit portion of the link.
number of 1s transmitted as close as possible to
the number of 0s transmitted. As with the
5.3.3 Overhead bits OH2, OH3 encoding
DISPARITY counter, the number of 1s and 0s in
each 24-bit Data Frame to be sent shall be
When implemented, OH2 and OH3 provide
counted in the NEW counter. The NEW counter
195 kBaud streams that may be used for end-to-
shall be initialised for each new 24-bit Data
end voice or data signalling separate from HIPPI-
Frame; it is not a running count of all 24-bit Data
PH traffic. Each OH2 and OH3 value transmitted
Frames transmitted. If the sign of the NEW
shall cover at least eight time slots, i.e., at least
counter is the same as the sign of the DISPARITY
5,12 μs. When implemented, OH2 and OH3 shall
counter, then the bits in the 24-bit Data Frame
be transmitted as a 1 when there is no other data
shall be inverted before being transmitted serially.
to be transmitted.
For example, compare the first two rows in
table 6.
5.4 Converting parallel data to serial
Converting from parallel to serial occurs in the
Transmitter Link Interface (TLI) functional unit
shown in figure 1. Table 6 defines the 24-bit
frames that will be serialised by the TLI.
The bits in table 6 shall be transmitted in a left to
right sequence (i.e., B0 shall be transmitted
first; C3 transmitted last). The data shall
be transmitted in a non-return to zero fashion
(i.e., 1 = light on, 0 = light off).
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11518-9 © ISO/IEC:1999(E)
Note that in table 6 there are two Fill Frame 1s,
5.4.2 Transmit Fill Frame 0
FF1H and FF1L. FF1H contains more 1s than 0s,
and FF1L contains more 0s than 1s. To achieve
When SEND_FF0 = true, the TLI shall transmit
24-bit Fill Frame 0s (FF0) as defined in table 6. DC balance FF1Ls shall be transmitted when the
Since FF0 has an equal number of 1s and 0s, it is sign of the DISPARITY counter is positive, and
already DC balanced. FF0s are used during a link FF1Hs shall be transmitted when the sign of the
reset operation. (See 7.3.1.) DISPARITY counter is negative.
5.4.3 Transmit Fill Frame 1
5.5 Transmit section clock signals
When SEND_FF1 = true, the TLI shall transmit
The serial data stream shall be transmitted at a
24-bit Fill Frame 1s (FF1) as defined in table 6.
rate of 48 times the HIPPI-PH CLOCK rate, i.e.,
SEND_FF1 = true occurs during a link reset
48 x 25 (± 0,01%) MBaud = 1,2 GBaud. The TLI
operation. (See 7.3.2.)
shall set TLI_UNLOCK = 0 when the TLI clock
multiplier is stable and locked.
Table 6 – 24-bit frame structure
24-bit frame
Data field Coding nibble Interpretation
B0                 B19
C0 C1 C2 C3
XXXXXXXXXXXXXXXXXXXX 1101
Data Frame, FLAG = 0, Data True
____________________
Data Frame, FLAG = 0, Data Inverted
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX 1011
Data Frame, FLAG = 1, Data True
____________________
0100 Data Frame, FLAG = 1, Data Inverted
XXXXXXXXXXXXXXXXXXXX
11111111110000000000 0011
Fill Frame 0 (FF0)
11111111111000000000 0011
Fill Frame 1, Heavy (FF1H)
11111111100000000000 0011
Fill Frame 1, Light (FF1L)
XXXXXXXXX10XXXXXXXXX 1100
Reserved Frame
XXXXXXXXX01XXXXXXXXX 0011
Reserved Frame
XXXXXXXXX0XXXXXXXXXX 1100
Frame Error
XXXXXXXXX11XXXXXXXXX 1100
Frame Error
XXXXXXXXXXXXXXXXXXXX 1010 Frame Error
XXXXXXXXXXXXXXXXXXXX 0101
Frame Error
XXXXXXXXXXXXXXXXXXXX X00X
Frame Error (no Master Transition)
XXXXXXXXXXXXXXXXXXXX X11X
Frame Error (no Master Transition)
Serial Specification (HIPPI-Serial) 10

11518-9 © ISO/IEC:1999(E)
6.2 Operating on the 24-bit frames
6 Receive section
The RLI shall signal the type of 24-bit frame
The receive section consists of the Receiver Link received based on the values in table 6. Only one
Interface (RLI), XDEMUX, SUBDEMUX, and of the following signals shall be true for each 24-
Decode functional units shown in the lower portion bit frame received.
of figure 1. The receive section decodes the
DATA_DET: a Data Frame was detected
serial stream, frames the signals, checks for
FF0_DET: an FF0 was detected
errors, and outputs parallel signals.
FF1_DET: an FF1H or FF1L was detected
FE_DET: a Frame Error was detected
6.1 Receive section clock signals
Reserved Frames should never be sent or
Note that the FF0 pattern in table 6 results in a
received, but future enhancements to HIPPI-Serial
square wave with 12 consecutive 1s followed by
may define uses for the reserved frames.  Any
12 consecutive 0s. Also notice that a 1 to 0, or 0
reserved frames received shall be discarded
to 1, transition, called the Master Transition,
without interpretation. Violations of this guideline
occurs at the coding nibble bits C1 to C2. The
may result in loss of upward compatibility.
Master Transition shall be used for synchronising
the Master Transition Clock, and shall be used to
6.2.1 Receiving Data Frames
frame groups of 24 bits into the 24-bit frames
shown in table 6. The Master Transition Clock
A 24-bit frame with a binary coding nibble value of
shall be locked to the Master Transitions in the
1101, 0010, 1011, or 0100 (i.e., the first four rows
received serial data stream, e.g. with a phase
of table 6) is called a Data Frame. If the coding
locked loop. The received serial data stream shall
nibble of a Data Frame indicates that the data is
be strobed at a rate of 24 times the Master
inverted, then the 20-bit data field shall be
Transition Clock rate to recover the bits.
inverted before being passed to the XDEMUX.
The FLAG signal shall also be derived from the
NOTES
coding nibble as defined in table 6.
1 The Master Transition Clock rate is initially
6.2.2 Receiving Fill Frame 0 (FF0)
derived from the FF0 square wave during the reset
operation. (See 7.3.1.) When passing data, the
Receiving an FF0 indicates that a reset operation
Master Transition Clock rate is maintained by
is underway. (See 7.3.1.) The REQUEST,
synchronising to the Master Transition occurring
PACKET, BURST, signals to the HIPPI-PH
every 24 bits.
Destination, and the READY and CONNECT
2 The Master Transition Clock should have the
signals to the HIPPI-PH Source, shall be set to
same long-term tolerance as the HIPPI-PH CLOCK
zeros. A parity error shall be forced in the data
signal since it is directly derived from it. HIPPI-PH
sent to the HIPPI-PH Destination.
specifies for the transmitted CLOCK signal a
tolerance of ± 0,01%
NOTE –  A simple way to force parity errors in a
given HIPPI word is to set all of the data and parity
3 The Master Transition Clock rate is twice the
bits to the HIPPI-PH Destination to 0. Because
HIPPI-PH CLOCK rate (i.e., 50 MHz). The bit clock
HIPPI-PH uses odd parity, all four parity bits will
rate for strobing the received serial data stream
appear to have parity errors.
operates at 24 times that rate (i.e., 1,2 GHz).
6.2.3 Receiving Fill Frame 1 (FF1)
4 A clock recovery circuit for 50 MHz should be
simpler than for a 1,2 GHz. A simple, easily
Receiving a FF1 indicates that a reset operation is
integrated, Phase Locked Loop (PLL) clock
underway. (See 7.3.2.) The REQUEST,
recovery mechanism utilising this Master Transition
is described in references [1-5] in annex E. PACKET, BURST, signals to the HIPPI-PH
Destination, and the READY and CONNECT
signals to the HIPPI-PH Source, shall be set to
zeros. A parity error shall be forced in the data
sent to the HIPPI-PH Destination.
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11518-9 © ISO/IEC:1999(E)
“b” links shall be used to time synchronise the two
6.2.4 Receiving Frame Errors
links (i.e., get the right D00 - D31 and D32 - D63
A Frame Error, FE_DET, as defined in table 6, together). The serial data streams on links “a”
shall cause the following: and “b” shall be time aligned, by matching or
trimming the cable lengths, so that there is
– A parity error shall be forced in the data sent
≤ 22 ns between F0 on cable “a” and F0 on
to the HIPPI-PH Destination.
cable “b”.
– The HIPPI-PH REQUEST, PACKET, and
BURST signals to the HIPPI-PH Destination
shall be maintained at their previous values.
6.4 Decoding F0, F1 into REQUEST, PACKET,
See annex C.2 for a discussion of ramifications
and BURST
of maintaining these signals at the previous
value.
The F0 bits and F1 bits of the 40-bit word shall be
decoded into the REQUEST, PACKET, and
– The M0/M1 time slot shall be advanced, and
BURST signals as defined in table 2. The
the functions encoded in M0 and M1 shall be
REQUEST, PACKET and BURST signals shall be
maintained at their last value.
transmitted to the HIPPI Destination on the same
– Two consecutive Frame Errors shall cause
CLOCK used to transmit the HIPPI data signals of
the link to be reset. (See 7.3 for reset details.)
that 40-bit word. This function is done in the
Decode functional unit of figure 1.
6.2.5 OH8 framing errors
64-bit (1 600 Mbit/s) HIPPI-Serial variants shall
If the received OH8 signal does not conform to use only the F0 and F1 signals f
...