IEC 61691-4:2004

Behavioural languages - Part 4: Verilog® hardware description language

Contains the formal syntax and semantics of all Verilog HDL constructs; the formal syntax and semantics of Standard Delay Format (SDF) constructs; simulation system tasks and functions,such as text output display commands; compiler directives,such as text substitution macros and simulation time scaling; the Programming Language Interface (PLI) binding mechanism; the formal syntax and semantics of access routines,task/function routines,and Verilog procedural interface routines; informative usage examples; informative delay model for SDF; listings of header files for PLI This publication has the status of a double logo IEEE/IEC standard

General Information

• Status: Withdrawn
• Publication Date: 04-Oct-2004
• Withdrawal Date: 31-May-2011
• ICS: 25.040.01 - Industrial automation systems in general
• ICS: 35.060 - Languages used in information technology
• Technical Committee: TC 91 - Electronics assembly technology
• Drafting Committee: WG 2 - TC 91/WG 2
• Current Stage: WPUB - Publication withdrawn
• Completion Date: 01-Jun-2011

Standards Content (Sample)

INTERNATIONAL IEC
STANDARD 61691-4
First edition
2004-10
™
IEEE 1364
Behavioural languages –
Part 4:
Verilog® hardware description language

Reference number
IEC 61691-4(E):2004
IEEE Std. 1364(E):2001
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INTERNATIONAL IEC
STANDARD 61691-4
First edition
2004-10
™
IEEE 1364
Behavioural languages –
Part 4:
Verilog® hardware description language

Copyright © IEEE 2004 ⎯ All rights reserved
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Международная Электротехническая Комиссия

2 IEC 61691-4:2004(E)
IEEE 1364-2001(E)
CONTENTS
FOREWORD . 19
IEEE Introduction. 23
1. Overview. 25
1.1 Objectives of this standard. 25
1.2 Conventions used in this standard. 25
1.3 Syntactic description. 26
1.4 Contents of this standard. 26
1.5 Header file listings . 28
1.6 Examples. 29
1.7 Prerequisites. 29
2. Lexical conventions .30
2.1 Lexical tokens .30
2.2 White space.30
2.3 Comments .30
2.4 Operators.30
2.5 Numbers.30
2.5.1 Integer constants .31
2.5.2 Real constants . 34
2.5.3 Conversion . 34
2.6 Strings . 34
2.6.1 String variable declaration . 35
2.6.2 String manipulation. 35
2.6.3 Special characters in strings. 35
2.7 Identifiers, keywords, and system names . 36
2.7.1 Escaped identifiers. 36
2.7.2 Generated identifiers. 37
2.7.3 Keywords . 37
2.7.4 System tasks and functions . 37
2.7.5 Compiler directives. 38
2.8 Attributes. 38
2.8.1 Examples. 39
2.8.2 Syntax . 40
3. Data types. 44
3.1 Value set. 44
3.2 Nets and variables. 44
3.2.1 Net declarations . 44
3.2.2 Variable declarations . 46
3.3 Vectors . 47
3.3.1 Specifying vectors. 47
3.3.2 Vector net accessibility. 48
3.4 Strengths . 48
3.4.1 Charge strength . 48
3.4.2 Drive strength. 48
3.5 Implicit declarations. 49
3.6 Net initialization. 49
3.7 Net types . 49
3.7.1 Wire and tri nets. 49
3.7.2 Wired nets . 50
Published by IEC under licence from IEEE. © 2004 IEEE. All rights reserved.
IEEE 1364-2001(E)
3.7.3 Trireg net. 50
3.7.4 Tri0 and tri1 nets. 54
3.7.5 Supply nets. 55
3.8 regs. 55
3.9 Integers, reals, times, and realtimes. 55
3.9.1 Operators and real numbers . 56
3.9.2 Conversion . 56
3.10 Arrays. 57
3.10.1 Net arrays. 57
3.10.2 reg and variable arrays. 57
3.10.3 Memories . 57
3.11 Parameters. 58
3.11.1 Module parameters. 59
3.11.2 Local parameters—localparam . 60
3.11.3 Specify parameters. 61
3.12 Name spaces. 62
4. Expressions . 64
4.1 Operators. 64
4.1.1 Operators with real operands . 65
4.1.2 Binary operator precedence . 66
4.1.3 Using integer numbers in expressions . 67
4.1.4 Expression evaluation order. 67
4.1.5 Arithmetic operators . 68
4.1.6 Arithmetic expressions with regs and integers . 69
4.1.7 Relational operators . 70
4.1.8 Equality operators . 70
4.1.9 Logical operators . 71
4.1.10 Bit-wise operators . 71
4.1.11 Reduction operators . 72
4.1.12 Shift operators. 73
4.1.13 Conditional operator . 74
4.1.14 Concatenations. 75
4.1.15 Event or. 76
4.2 Operands
...