IEC 62530-2:2023

SystemVerilog - Part 2: Universal Verification Methodology Language Reference Manual

IEC 62530-2:2023 establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™.1. This is an IEC/IEEE dual logo standard.

General Information

• Status: Published
• Publication Date: 10-Oct-2023
• ICS: 25.040.01 - Industrial automation systems in general
• ICS: 35.060 - Languages used in information technology
• Technical Committee: TC 91 - Electronics assembly technology
• Drafting Committee: WG 13 - TC 91/WG 13
• Current Stage: PPUB - Publication issued
• Start Date: 08-Sep-2023
• Completion Date: 11-Oct-2023

Relations

• Revises: IEC 62530-2:2021 - SystemVerilog - Part 2: Universal Verification Methodology Language Reference Manual
• Effective Date: 05-Sep-2023

Standards Content (Sample)

IEC 62530-2 ®
Edition 2.0 2023-10
™
IEEE Std 1800.2
INTERNATIONAL
STANDARD
SystemVerilog –
Part 2: Universal Verification Methodology Language Reference Manual
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IEC 62530-2 ®
Edition 2.0 2023-10
IEEE Std 1800.2™
INTERNATIONAL
STANDARD
SystemVerilog –
Part 2: Universal Verification Methodology Language Reference Manual
INTERNATIONAL
ELECTROTECHNICAL
COMMISSION
ICS 25.040.01, 35.060 ISBN 978-2-8322-7516-0
– i – IEEE Std 1800.2™-2020
Contents
1. Overview .12
1.1 Scope .12
1.2 Purpose .12
1.3 Word usage .12
1.4 Conventions used .13
2. Normative references .15
3. Definitions, acronyms, and abbreviations .15
3.1 Definitions .15
3.2 Acronyms and abbreviations .16
4. Universal Verification Methodology (UVM) class reference .17
5. Base classes .18
5.1 Overview .18
5.2 uvm_void .18
5.3 uvm_object .19
5.4 uvm_transaction .27
5.5 uvm_port_base #(IF) .31
5.6 uvm_time .34
5.7 uvm_field_op .36
6. Reporting classes .38
6.1 Overview .38
6.2 uvm_report_message .39
6.3 uvm_report_object .41
6.4 uvm_report_handler .47
6.5 Report server.50
6.6 uvm_report_catcher .53
7. Recording classes .58
7.1 uvm_tr_database .59
7.2 uvm_tr_stream .61
7.3 UVM links .65
8. Factory classes .69
8.1 Overview .69
8.2 Factory component and object wrappers .69
8.3 UVM factory.75
9. Phasing .81
9.1 Overview .81
9.2 Implementation .81
9.3 Phasing definition classes .82
9.4 uvm_domain .91
9.5 uvm_bottomup_phase .92
9.6 uvm_task_phase.92
9.7 uvm_topdown_phase .93
9.8 Predefined phases .94
10. Synchronization classes .98
10.1 Event classes .98
Published by IEC under licence from IEEE. © 2020 IEEE. All rights reserved.

IEEE Std 1800.2™-2020 – ii –
10.2 uvm_event_callback .101
10.3 uvm_barrier .102
10.4 Pool classes .104
10.5 Objection mechanism .105
10.6 uvm_heartbeat .110
10.7 Callbacks classes .112
11. Container classes .115
11.1 Overview .115
11.2 uvm_pool #(KEY,T) .116
11.3 uvm_queue #(T) .118
12. UVM TLM interfaces .120
12.1 Overview .120
12.2 UVM TLM 1 .120
12.3 UVM TLM 2 .138
13. Predefined component classes .159
13.1 uvm_component .159
13.2 uvm_test .172
13.3 uvm_env .173
13.4 uvm_agent .173
13.5 uvm_monitor .174
13.6 uvm_scoreboard .174
13.7 uvm_driver #(REQ,RSP) .175
13.8 uvm_push_driver #(REQ,RSP) .175
13.9 uvm_subscriber .176
14. Sequence classes .177
14.1 uvm_sequence_item .177
14.2 uvm_sequence_base .181
14.3 uvm_sequence #(REQ,RSP) .189
14.4 uvm_sequence_library .191
15. Sequencer classes .
...