IEC PAS 62173:2000

Solderability test method

Provides a means of determining the solderability of device package terminations that are intended to be joined to another surface using solder for the attachment. Provides also optional conditions for ageing and soldering for the purpose of allowing simulation of the soldering process to be used in the device application.

General Information

• Status: Replaced
• Publication Date: 21-Aug-2000
• ICS: 31.080.01 - Semiconductor devices in general
• Technical Committee: TC 47 - Semiconductor devices
• Drafting Committee: WG 2 - TC 47/WG 2
• Current Stage: DELPUB - Deleted Publication
• Completion Date: 15-Mar-2004

Relations

• Replaced By: IEC 60749-21:2004 - Semiconductor devices - Mechanical and climatic test methods - Part 21: Solderability
• Effective Date: 05-Sep-2023

Standards Content (Sample)

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Solderability test method
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IN TER N A TION AL Reference number
E L E C T R OT E CHNI CA L
IEC/PAS 62173
C O MMI S S I O N
EIA/JEDEC
STANDARD
Solderability Test Method
JEDEC Solid State Technology Division

ELECTRONIC INDUSTRIES ALLIANCE
SEPTEMBER 1998
EIA/JESD22-B102-C
Copyright © 1998, JEDEC; 2000, IEC

INTERNATIONAL ELECTROTECHNICAL COMMISSION

____________
SOLDERABILITY TEST METHOD
FOREWORD
A PAS is a technical specification not fulfilling the requirements for a standard, but made available to the
public and established in an organization operating under given procedures.
IEC-PAS 62173 was submitted by JEDEC and has been processed by IEC technical committee 47: Semiconductor
devices.
The text of this PAS is based on the This PAS was approved for
following document: publication by the P-members of the
committee concerned as indicated in
the following document:
Draft PAS Report on voting
47/1446/PAS 47/1479/RVD
Following publication of this PAS, the technical committee or subcommittee concerned will investigate the
possibility of transforming the PAS into an International Standard.
An IEC-PAS licence of copyright and assignment of copyright has been signed by the IEC and JEDEC and is
recorded at the Central Office.
1) The IEC (International Electrotechnical Commission) is a worldwide organization for standardization comprising all
national electrotechnical committees (IEC National Committees). The object of the IEC is to promote international co-
operation on all questions concerning standardization in the electrical and electronic fields. To this end and in addition
to other activities, the IEC publishes International Standards. Their preparation is entrusted to technical committees;
any IEC National Committee interested in the subject dealt with may participate in this preparatory work. International,
governmental and non-governmental organizations liaising with the IEC also participate in this preparation. The IEC
collaborates closely with the International Organization for Standardization (ISO) in accordance with conditions
determined by agreement between the two organizations.
2) The formal decisions or agreements of the IEC on technical matters express, as nearly as possible, an international
consensus of opinion on the relevant subjects since each technical committee has representation from all interested
National Committees.
3) The documents produced have the form of recommendations for international use and are published in the form of
standards, technical specifications, technical reports or guides and they are accepted by the National Committees in
that sense.
4) In order to promote international unification, IEC National Committees undertake to apply IEC International Standards
transparently to the maximum extent possible in their national and regional standards. Any divergence between the
IEC Standard and the corresponding national or regional standard shall be clearly indicated in the latter.
5) The IEC provides no marking procedure to indicate its approval and cannot be rendered responsible for any
equipment declared to be in conformity with one of its standards.
6) Attention is drawn to the possibility that some of the elements of this PAS may be the subject of patent rights. The
IEC shall not be held responsible for identifying any or all such patent rights.
Page i
Copyright © 1998, JEDEC; 2000, IEC

NOTICE
EIA/JEDEC standards and publications contain material that has been prepared, reviewed, and

approved through the JEDEC Council level and subsequently reviewed and approved by the EIA

EIA/JEDEC standards and publications are designed to serve the public interest through

eliminating misunderstandings between manufacturers and purchasers, facilitating
interchangeability and improvement of products, and assisting the purchaser in selecting and
obtaining with minimum delay the proper product for use by those other than JEDEC members,
EIA/JEDEC standards and publications are adopted without regard to whether or not their
adoption may involve patents or articles, materials, or processes. By such action JEDEC does not
assume any liability to any patent owner, nor does it assume any obligation whatever to parties
The information included in EIA/JEDEC standards and publications represents a sound approach
to product specification and application, principally from the solid state device manufacturer
viewpoint. Within the JEDEC organization there are procedures whereby a EIA/JEDEC standard
No claims to be in conformance with this standard may be made unless all requirements stated in
Inquiries, comments, and suggestions relative to the content of this EIA/JEDEC standard or
publication should be addressed to JEDEC Solid State Technology Division, 2500 Wilson
©
ii
JEDEC Publication 21 "Manual of Organization and Procedure".
free to duplicate this document in accordance with the latest revision of
"Copyright" does not apply to JEDEC member companies as they are
Arlington, VA 22201-3834
2500 Wilson Boulevard
Engineering Department
ELECTRONIC INDUSTRIES ALLIANCE 1998
Published by
www.eia.org\jedec. Boulevard, Arlington, VA 22201-3834, [phone]/7559 or
the standard are met.
or publication may be further processed and ultimately become an ANSI/EIA standard.
adopting the EIA/JEDEC standards or publications.
whether the standard is to be used either domestically or internationally.
General Counsel.
Copyright © 1998, JEDEC; 2000, IEC

TEST METHOD B102-C
SOLDERABILITY
CONTENTS
2 Apparatus1
2.1 Solder pot1
4 Procedure for dip and look solderability testing7
4.2 Solder dip conditions7
Tables
2 Maximum limits of solder bath contaminant11
i
ii
1 Altitude versus steam temperature
6 Inspected area for J-lead packages (dip and look method)
5 Inspected area for gullwing packages (dip and look method)
4 Critical areas in tantalum chip capacitor
3 Critical areas in plastic-leaded chip carrier (SMD method)
2 Critical areas in SOIC and QFP packages (SMD method)
1 Critical areas in rectangular passive components (SMD method)
Figures
5 Summary
4.3 Testing
4.1 Preconditioning
3.3 Visual inspection
3.2 Specimen preparation and surface condition
3.1 Test equipment set-up
3 Procedure for simulated board mounting reflow solderability test in SMDs
2.7 SMD reflow equipment
2.6 Materials
2.5 Lighting equipment
2.4 Steam aging equipment
2.3 Optical equipment
2.2 Dipping device
1 Purpose
Page
JEDEC Standard 22-B102-C
Copyright © 1998, JEDEC; 2000, IEC

2 Apparatus
2.1 Solder pot
o
C.
2.2 Dipping device
Test Method B102-C
(Revision of Test Method B102-B)
used.
An optical microscope capable of providing magnification inspection from 10x to 20x shall be
2.3 Optical equipment
solder bath as specified shall be used.
terminations and providing a dwell time (time of total immersion to the required depth) in the
A mechanical dipping device capable of controlling the rates of immersion and emersion of the
The apparatus shall be capable of maintaining the solder at the specified temperature within +/- 5
A static solder pot of sufficient size to contain at least 2 pounds (4.4 kg) of solder shall be used.
simulated use testing for surface mount packages.
for dip & look solderability testing of through hole, axial and surface mount devices and reflow
simulation of the soldering process to be used in the device application. It provides procedures
This test method provides optional conditions for aging and soldering for the purpose of allowing
attachment.
package terminations that are intended to be joined to another surface using solder for the
The purpose of this test method is to provide a means of determining the solderability of device
1 Purpose
Subcommittee on Reliability Test Methods for Packaged Devices.)
(From JEDEC Council Ballot JCB-97-71, formulated under the cognizance of the JC-14.1
SOLDERABILITY
TEST METHOD B102-C
Page
JEDEC Standard 22-B102-C
Copyright © 1998, JEDEC; 2000, IEC

2.5 Lighting equipment
2.6.1 Flux
o
C.
2.7 SMD reflow equipment
Test Method B102-C
(Revision of Test Method B102-B)
e.g., 0.889 mm (0.035 in) thick.
2.7.3 Ceramic substrate
2.7.2 Rubber squeegee or metal spatula
in), and 0.203 mm (0.008 in) for a component with lead pitch greater than 0.635 mm (0.025 in).
0.152 mm (0.006 in) for a component with lead pitch of 0.508 mm to 0.635 mm (0.020 in to 0.025
0.102 mm (0.004 in) for terminals with less than 0.508 mm (0.020 in) component lead pitch,
Unless otherwise agreed upon between vendor and user, nominal stencil thickness should be
A stencil or screen with pad geometry opening that is appropriate for the terminals being tested.
2.7.1 Stencil or screen
Soldering Applications".
Electronic Grade Solder Alloys and Fluxed and Non-Fluxed Solid Solders for Electronic
The solder shall conform to type Sn6337A or Sn60Pb40A of J-STD-006, “Requirements for
2.6.2 Solder
the flux shall be maintained within the range of 0.838 to 0.913 at 25
percent by weight Gum Rosin in a 99 percent Isopropyl Alcohol solvent.) The specific gravity of
The flux shall conform to type ROL of J-STD-004, “Requirements for Soldering Fluxes". (25
2.6 Materials
of the specimen.
A lighting system shall be used that will provide a uniform, nonglare, nondirectional illumination
of supporting the specimens shall be improvised using noncontaminating material.
specimen is a minimum of 1.5 inches (38 mm) above the surface of the water. A suitable method
inside the vessel shall be used. The specimens shall be placed such that the lowest portion of the
A noncorrodible container and cover of sufficient size to allow the placement of specimens
2.4 Steam aging equipment
2 Apparatus (cont’d)
Page
JEDEC Standard 22-B102-C
Copyright © 1998, JEDEC; 2000, IEC

2.7.6 Flux removal solvent
Test Method B102-C
(Revision of Test Method B102-B)
Time (s)
215-230 150-170 Temperature (°C)
Reflow Preheat
3.1.2 Infrared reflow
Time       = 30 - 60 s dwell at reflow temperature
Temperature = 215 - 219°C
3.1.1 Vapor phase reflow
3.1 Test equipment set-up
Note — This procedure comes from EIA-638, “Surface Mount Solderability Test”
adequately with the dip & look method. Also, dip & look is inappropriate for BGA’s.
procedure of section 4. Fine pitch gullwing leads (spacings < 20 mils) cannot be tested
This procedure may be used for surface mounted devices as an alternative to the dip & look
3 Procedure for simulated board mounting reflow solderability testing of SMDs
flux residues and meet local environmental regulations.
Material used for cleaning flux from leads and terminations shall be capable of removing visible
the reflow temperature of the paste being used.
Infrared/convection reflow oven, vapor phase reflow system, or storage oven capable of reaching
2.7.5 Reflow equipment
Note — Paste storage and shelf life shall be in accordance with manufacturer’s specifications.
for Soldering Pastes”, and shall have a mesh size of -325/+500.
The solder paste shall conform to Sn6337A or Sn60Pb40A, ROL, of J-STD-005 “Requirements
2.7.4 Solder paste
2.7 SMD reflow equipment (cont’d)
2 Apparatus (cont’d)
Page
JEDEC Standard 22-B102-C
Copyright © 1998, JEDEC; 2000, IEC

3.2 Specimen preparation and surface condition

3.3 Visual inspection
Test Method B102-C
(Revision of Test Method B102-B)
Each termination shall be examined using a magnification of 10X to 20X.
3.3.1 Visual magnification criteria
3.2.7 Remove any flux residue by using appropriate cleaning solution.
substrate using tweezers. Terminals may adhere slightly to ceramic material due to flux residue.
3.2.6 After specimen has cooled to room temperature, remove component from ceramic
3.2.5 After reflow, carefully remove substrate with components and allow to cool.
and components to the reflow process.
3.2.4 Place the ceramic substrate on the applicable reflow equipment and subject the substrate
appropriate magnification.
the unit so that the terminals will not be contaminated with skin oils. Verify part placement by
3.2.3 Using tweezers, place the terminals of the unit on the solder paste print. Avoid touching
equivalent in geometry to the terminal of the device to be tested.
3.2.2 Remove the screen carefully so as to avoid smearing the paste print. Verify a paste print
paste over the screen using either a spatula for fine pitch or a squeegee for standard pitch.
3.2.1 Place solder paste onto screen and print the terminal pattern onto the ceramic by wiping the
the leads or terminations being tested be wiped, cleaned, scraped, or abraded.
The specimens to be tested shall not be touched by fingers or otherwise contaminated, nor shall
be in at the time of assembly soldering.
All component leads or terminations shall be tested under the condition that they would normally
Time       = 2-5 min (until reflow is assured)
Temperature = 215-230°C
3.1.3 Storage oven
3.1 Test equipment set-up (cont’d)
3 Procedure for simulated board mounting reflow solderability testing of SMDs (cont’d)
Page
JEDEC Standard 22-B102-C
Copyright © 1998, JEDEC; 2000, IEC

3.3 Visual inspection (cont’d)

Test Method B102-C
(Revision of Test Method B102-B)
Figure 2 — Critical Areas in SOIC and QFP Packages (SMD Method)
Figure 1 — Critical Areas in Rectangular Passive Components (SMD Method)
Examples of the critical areas for various devices are contained in Figures 1 through 4.
end toe of surface mount components.
nonwetting, and pinholes are not cause for rejection. Exposed terminal metal is allowable on the
95% of the critical surface area of any individual termination. Anomalies other than dewetting,
All terminations shall exhibit a continuous solder coating free from defects for a minimum of
3.3.2 Accept/reject criteria
3 Procedure for simulated board mounting reflow solderability testing of SMDs (cont’d)
Page
JEDEC Standard 22-B102-C
Copyright © 1998, JEDEC; 2000, IEC

3.3 Visual inspection cont’d)

Test Method B102-C
(Revision of Test Method B102-B)
Figure 4 — Critical Area in Tantalum Chip Capacitor
Figure 3 — Criti
...