ISO 11898-2:2026

Road vehicles — Controller area network (CAN) — Part 2: High-speed physical medium attachment (PMA) sublayer

This document specifies physical medium attachment (PMA) sublayers for the controller area network (CAN). This includes the high-speed (HS) PMA without and with low-power mode capability, without and with selective wake-up functionality. Additionally, this document specifies PMAs supporting the signal improvement capability (SIC) mode and the FAST mode in Annex A. The physical medium dependent (PMD) sublayer is not in the scope of this document.

Véhicules routiers — Gestionnaire de réseau de communication (CAN) — Partie 2: Sous-couche de l’unité d'accès au support à haute vitesse (PMA)

General Information

• Status: Published
• Publication Date: 20-May-2026
• ICS: 43.040.15 - Car informatics. On board computer systems
• Technical Committee: ISO/TC 22/SC 31 - Data communication
• Drafting Committee: ISO/TC 22/SC 31/WG 3 - In-vehicle networks
• Current Stage: 6060 - International Standard published
• Start Date: 21-May-2026
• Due Date: 28-Apr-2026
• Completion Date: 21-May-2026

Relations

• Revises: ISO 11898-2:2024 - Road vehicles — Controller area network (CAN) — Part 2: High-speed physical medium attachment (PMA) sublayer
• Effective Date: 07-Jan-2025

Overview

ISO 11898-2: Road vehicles - Controller area network (CAN) - High-speed physical medium attachment (PMA) sublayer is an international standard published by ISO. This document specifies the requirements and characteristics of the physical medium attachment (PMA) sublayer for CAN networks in road vehicles, focusing on high-speed (HS) CAN communications. It covers implementations with and without low-power mode, optional selective wake-up functions, and advanced features such as signal improvement capability (SIC) and FAST mode.

The standard is intended for use by CAN transceiver designers, automotive OEMs, ECU manufacturers, and network designers aiming to optimize high-speed CAN communication reliability, robustness, and interoperability in modern vehicles.

Key Topics

• High-speed PMA requirements: ISO 11898-2 defines base requirements for the high-speed CAN PMA, including normal and low-power operation, transmitter and receiver behaviors, and signal characteristics.
• Modes of Operation: The document covers PMA configurations with and without low-power and selective wake-up functionality, enabling energy-efficient network operation and advanced network management.
• Signal Improvement Capability (SIC) and FAST Mode: Annexes specify signal improvement techniques to reduce bus ringing and improve signal quality, as well as FAST mode for improved data transmission in CAN networks.
• Conformance and Testing: Specifies conformance requirements for correct PMA implementation and outlines relevant test circuits and setups.
• Static and Dynamic Parameters: Defines voltage levels, current limits, driver symmetry, input resistance, leakage currents, and timing requirements essential for robust high-speed CAN communication.
• Wake-up Procedures: Describes procedures for waking network nodes from low-power modes, with or without selective wake-up capabilities.
• Terminology and Abbreviations: The standard provides a glossary and abbreviated terms relevant to CAN transceivers and networking.

Applications

ISO 11898-2 is widely adopted for the physical layer of high-speed CAN communication in various automotive applications, including:

• Engine and powertrain control modules: Ensures fast, reliable real-time data exchange for critical vehicle systems.
• Advanced driver assistance systems (ADAS): Provides robust communication between sensors, actuators, and control units, supporting safety features and automation.
• Infotainment and in-vehicle networking: Enables high-speed multimedia and data sharing between ECUs and user interfaces.
• Battery management and electric vehicle systems: Supports EV-specific applications requiring reliable and low-latency communication.
• Fleet and commercial vehicles: Facilitates diagnostics, telematics, and fleet management through standardized, interoperable CAN networks.

The standard’s support for selective wake-up and low-power features also contributes to energy-efficient vehicle operation, by allowing network segments or ECUs to sleep when not needed.

Related Standards

ISO 11898-2 is one component within a suite of CAN standards for road vehicles. Relevant related standards include:

• ISO 11898-1: Specifies the CAN data link layer and physical coding sublayer, forming the protocol foundation for CAN networks.
• ISO 11898 series: Comprises additional documents addressing fault-tolerant CAN, low-speed CAN, and CAN FD (Flexible Data-Rate).
• ISO 16845 series: Provides conformance test plans for the CAN data link and physical layers, ensuring reliable implementation and interoperability.
• ISO/IEC 7498-1: The OSI Reference Model, forming the basis for how CAN sublayers map to OSI layers.

Practical Value

Adhering to ISO 11898-2 ensures that CAN transceivers and automotive ECUs exhibit consistent electrical behavior, high noise immunity, and interoperability across the industry. The specification is critical for:

• Enabling high-speed, reliable in-vehicle communication
• Ensuring compatibility between components from different suppliers
• Meeting automotive safety and EMC (electromagnetic compatibility) requirements
• Supporting new network architectures with energy-saving features

Implementing the latest edition of ISO 11898-2 allows automotive engineering teams to address modern vehicle networking requirements, maintain robust performance under harsh conditions, and adhere to global best practices in automotive network design.

Standards Content (Sample)

International
Standard
ISO 11898-2
Fourth edition
Road vehicles — Controller area
2026-05
network (CAN) —
Part 2:
High-speed physical medium
attachment (PMA) sublayer
Véhicules routiers — Gestionnaire de réseau de communication
(CAN) —
Partie 2: Sous-couche de l’unité d'accès au support à haute vitesse
(PMA)
Reference number
© ISO 2026
All rights reserved. Unless otherwise specified, or required in the context of its implementation, no part of this publication may
be reproduced or utilized otherwise in any form or by any means, electronic or mechanical, including photocopying, or posting on
the internet or an intranet, without prior written permission. Permission can be requested from either ISO at the address below
or ISO’s member body in the country of the requester.
ISO copyright office
CP 401 • Ch. de Blandonnet 8
CH-1214 Vernier, Geneva
Phone: [phone]
Email: [e-mail]
Website: www.iso.org
Published in Switzerland
ii
Contents Page
Foreword .iv
Introduction .v
1 Scope . 1
2 Normative references . 1
3 Terms and definitions . 1
4 Abbreviated terms . 3
5 HS-PMA function . 4
5.1 Base requirements .4
5.2 HS-PMA test circuit .4
5.3 Static parameter .5
5.3.1 Maximum ratings of V , V and V .5
CAN_H CAN_L Diff
5.3.2 Recessive output characteristics, bus biasing active .5
5.3.3 Recessive output characteristics, bus biasing inactive .6
5.3.4 Dominant output characteristics .6
5.3.5 Maximum driver output current .8
5.3.6 PMA static receiver input characteristics, bus biasing active and inactive.8
5.3.7 Receiver input resistance .9
5.3.8 Maximum leakage currents of CAN_H and CAN_L .10
5.4 Dynamic parameter .10
5.4.1 Driver symmetry . .10
5.4.2 Optional transmit dominant timeout .11
5.4.3 Transmitter and receiver timing behaviour .11
5.5 Wake-up from low-power mode . 15
5.5.1 Wake-up procedures . 15
5.5.2 General requirement . . 15
5.5.3 Basic wake-up . 15
5.5.4 Via wake-up pattern . 15
5.5.5 Selective wake-up .19
5.5.6 Bus biasing procedure .24
6 Conformance .26
Annex A (normative) HS-PMA with SIC mode and FAST mode .27
Annex B (informative) ECU and network design.54
Annex C (informative) PN physical layer modes .60
Bibliography . 61

iii
Foreword
ISO (the International Organization for Standardization) is a worldwide federation of national standards
bodies (ISO member bodies). The work of preparing International Standards is normally carried out through
ISO technical committees. Each member body interested in a subject for which a technical committee
has been established has the right to be represented on that committee. International organizations,
governmental and non-governmental, in liaison with ISO, also take part in the work. ISO collaborates closely
with the International Electrotechnical Commission (IEC) on all matters of electrotechnical standardization.
The procedures used to develop this document and those intended for its further maintenance are described
in the ISO/IEC Directives, Part 1. In particular, the different approval criteria needed for the different types
of ISO documents should be noted. This document was drafted in accordance with the editorial rules of the
ISO/IEC Directives, Part 2 (see www.iso.org/directives).
ISO draws attention to the possibility that the implementation of this document may involve the use of (a)
patent(s). ISO takes no position concerning the evidence, validity or applicability of any claimed patent
rights in respect thereof. As of the date of publication of this document, ISO had not received notice of (a)
patent(s) which may be required to implement this document. However, implementers are cautioned that
this may not represent the latest information, which may be obtained from the patent database available at
www.iso.org/patents. ISO shall not be held responsible for identifying any or all such patent rights.
Any trade name used in this document is information given for the convenience of users and does not
constitute an endorsement.
For an explanation of the voluntary nature of standards, the meaning of ISO specific terms and expressions
related to conformity assessment, as well as information about ISO’s adherence to the World Trade
Organization (WTO) principles in the Technical Barriers to Trade (TBT), see www.iso.org/iso/foreword.html.
This document was prepared by Technical Committee ISO/TC 22, Road vehicles, Subcommittee SC 31, Data
communication.
This fourth edition cancels and replaces the third edition (ISO 11898-2:2024), which has been technically
revised.
The main changes are as follows:
— bugs have been fixed, clarifications have been made and figures have been updated;
— the common mode range specification of the receiver has become extended towards +/− 8 V differential
(see Table 7).
A list of all parts in the ISO 11898 series can be found on the ISO website.
Any feedback or questions on this document should be directed to the user’s national standards body. A
complete listing of these bodies can be found at www.iso.org/members.html.

iv
Introduction
The ISO 11898 series provides requirement specifications for the CAN data link layer and physical layer. It
is intended for chip implementers, e.g. ISO 11898-1 for CAN protocol controllers and this document for CAN
transceivers. Related conformance test plans are given in the ISO 16845 series. The CAN data link layer
models the open system interconnect (OSI) data link layer; it is internally subdivided into logic link control
(LLC) and medium access control (MAC). ISO 11898-1 also specifies the CAN physical coding sublayer
(PCS) by means of the attachment unit interface (AUI). Optionally, the PCS also provides the pulse-width
modulation (PWM) encoding to be linked to a CAN SIC XL transceiver, which provides the PWM decoding.
The OSI layers above the data link layer (e.g. the network layer) are not specified in the ISO 11898 series.
Figure 1 shows the relation between the OSI layers and the CAN sublayers.
Key
AUI attachment unit interface
LLC logic link control
MAC medium access control
MDI medium dependent interface
PCS physical coding sublayer
PMA physical medium attachment
PMD physical medium dependent
PWM pulse-width modulation
Figure 1 — CAN data link and physical sublayers relation to the OSI model

v
International Standard ISO 11898-2:2026(en)
Road vehicles — Controller area network (CAN) —
Part 2:
High-speed physical medium attachment (PMA) sublayer
1 Scope
This document specifies physical medium attachment (PMA) sublayers for the controller area network
(CAN). This includes the high-speed (HS) PMA without and with low-power mode capability, without and
with selective wake-up functionality. Additionally, this document specifies PMAs supporting the signal
improvement capability (SIC) mode and the FAST mode in Annex A. The physical medium dependent (PMD)
sublayer is not in the scope of this document.
2 Normative references
The following documents are referred to in the text in such a way that some or all of their content constitutes
requirements of this document. For dated references, only the edition cited applies. For undated references,
the latest edition of the referenced document (including any amendments) applies.
ISO/IEC 7498-1, Information technology — Open Systems Interconnection — Basic Reference Model: The Basic
Model
ISO 11898-1, Road vehicles — Controller area network (CAN) — Part 1: Data link layer and physical coding
sublayer
3 Terms and definitions
For the purposes of this document, the terms and definitions given in ISO/IEC 7498-1, ISO 11898-1 and the
following apply.
ISO and IEC maintain terminology databases for use in standardization at the following addresses:
— ISO Online browsing platform: available at https:// www .iso .org/ obp
— IEC Electropedia: available at https:// www .electropedia .org/
3.1
active recessive
intermediate high-speed physical medium attachment (3.13) (HS-PMA) output drive with a dedicated lower
than nominal impedance at transitions from dominant state or level_0 state towards the passive recessive
(3.11) state with a dedicated duration
3.2
bus state
state of the medium dependent interface (MDI) (3.8), which is dominant or recessive if the physical medium
attachment (PMA) (3.13) sublayer is in arbitration mode, or is level_0 or level_1 otherwise
Note 1 to entry: The dominant state represents the logical 0 and the recessive state represents the logical 1. During
simultaneous transmission of dominant and recessive bits, the resulting bus state is dominant. When no transmission
is in progress, the bus is idle. During idle time, it is in recessive state.
Note 2 to entry: The level_0 state represents the logical 0, and the level_1 state represents the logical 1.

3.3
CAN_H, CAN_L
pair of ports, where V – V is positive at dominant bus state (3.2) and level_0 bus state
CAN_H CAN_L
3.4
FAST RX mode
mode in which the physical medium attachment (PMA) (3.13) sublayer drives the bus state (3.2) recessive and
the receive thresholds are adjusted to distinguish between the bus states level_0 and level_1
3.5
FAST TX mode
mode in which the physical medium attachment (PMA) (3.13) sublayer drives the bus states (3.2) level_0 and
level_1, which are complementary with non-conclusive result if driven simultaneously
3.6
legacy implementation
high-speed physical medium attachment (3.13) (HS-PMA) implementation conform to previous ISO 11898-2
editions
3.7
low-power mode
mode in which the transceiver is not capable of transmitting or receiving frames, except for the purposes of
determining if a wake-up pattern (WUP) or wake-up frame (WUF) is being received
3.8
MDI
medium dependent interface
electrical interface consisting of CAN_H and CAN_L, that defines the signal transfer between the physical
medium dependent (PMD) sublayer and the physical medium attachment (PMA) (3.13) sublayer
3.9
nominal bit time
duration of one bit in the arbitration phase
3.10
normal-power mode
mode in which the transceiver is capable of transmitting and receiving
3.11
passive recessive
final high-speed physical medium attachment (3.13) (HS-PMA) output drive with nominal impedance
Note 1 to entry: Passive recessive is the same as recessive in prior editions of this document.
3.12
physical coding sublayer
PCS
sublayer of the open system interconnect (OSI) physical layer that performs bit encoding/decoding and
synchronization
3.13
physical medium attachment
PMA
sublayer of the open system interconnect (OSI) physical layer that converts physical signals into logical
signals and vice versa
3.14
PWM decoding
PWMD
physical medium attachment (PMA) (3.13) sublayer function decoding the pulse-width modulation (PWM) bit
streams into the non-return-to-zero (NRZ) bit streams

3.15
PWM encoding
PWME
physical coding sublayer (PCS) (3.12) function encoding the non-return-to-zero (NRZ) bit streams into the
pulse-width modulation (PWM) bit streams
3.16
receiver
functional block inside the physical medium attachment (PMA) (3.13) converting the analogue medium
dependent interface (MDI) (3.8) interface signals CAN_H and CAN_L into a logic level
3.17
RXD
port of the attachment unit interface (AUI) used to transmit the actual state of the physical medium, in binary
format, to the physical coding sublayer (PCS) (3.12)
3.18
signal improvement capability
SIC
capability to suppress the ringing on the medium dependent interface (MDI) (3.8)
Note 1 to entry: It is as specified in the high-speed physical medium attachment (3.13) (HS-PMA) implementation
parameter set C in Table 14 and Table 17.
3.19
SIC mode
mode according to the high-speed physical medium attachment (3.13) (HS-PMA) during the arbitration phase
Note 1 to entry: For PMA implementations, it is according to parameter set C or Annex A.
3.20
transmitter
functional block inside the physical medium attachment(PMA) (3.13) converting the digital attachment unit
interface (AUI) signal into analogue medium dependent interface (MDI) (3.8) signals CAN_H and CAN_L
3.21
TXD
port of the attachment unit interface (AUI) driven by the physical coding sublayer (PCS) (3.12) to control how
the physical medium attachment (PMA) (3.13) influences the actual state of the physical medium
4 Abbreviated terms
For the purposes of this document, the symbols and abbreviated terms given in ISO 11898-1 and the
following apply.
CAN controller area network
DLC data length code
ECU electronic control unit
EMC electromagnetic compatibility
ESD electro static discharge
GND ground
HS-PMA high-speed PMA
NRZ non-return-to-zero
OSI open layer system
PMD physical medium dependent
PN partial networking
PWM pulse width modulation
RF radio frequency
WUF wake-up frame
WUP wake-up pattern
5 HS-PMA function
5.1 Base requirements
The HS-PMA comprises one transmitter and one receiving entity. It shall be able to bias the connected
physical medium, an electric two-wire cable, relative to a common ground. The transmitter entity shall
drive a differential voltage between the CAN_H and CAN_L signals to signal a logical 0 (dominant) or shall
not drive a differential voltage to signal a logical 1 (recessive) to be received by other nodes connected to the
very same medium. These two signals are the interface to the PMD sublayer.
The HS-PMA shall provide an AUI to the physical coding sublayer as specified in ISO 11898-1. It comprises the
TXD and RXD signals as well as the GND signal. The TXD signal receives from the physical coding sublayer
the bit stream to be transmitted on the MDI. The RXD signal transmits to the physical coding sublayer the
bit stream received from the MDI.
Implementations that comprise one or more HS-PMAs shall at least support the normal-power mode of
operation. A low-power mode may be implemented.
Some of the items specified in the following depend on the operation mode of the (part of the) implementation,
in which the HS-PMA is included.
Table 1 shows the possible combinations of HS-PMA operating modes and expected behaviour.
Table 1 — HS-PMA operating modes and expected behaviour
Operating mode Bus-biasing behaviour Transmitter behaviour
Normal-power mode Bus biasing active Dominant, active recessive, or passive
a
recessive
Low-power mode Bus biasing active or inactive Passive recessive
a
Depends on input conditions as specified in this document.
Parameters given in Clause 5 shall be fulfilled throughout the operating temperature range and supply
voltage range (if not explicitly specified for unpowered) as specified individually for every HS-PMA
implementation.
SIC XL specific parameters shall conform with the requirements given in Annex A.
5.2 HS-PMA test circuit
The outputs of the HS-PMA implementation to the CAN signals are called CAN_H and CAN_L, TXD is the
transmit data input and RXD is the receive data output. Figure 2 shows the external circuit used to measure
the specified voltage and current parameters. R represents the effective resistive load (bus load) for an
L
HS-PMA implementation, when used in a network, and C represents an optional split-termination capacitor.
The values of R and C vary for different parameters that the HS-PMA implementation needs to meet and
L 1
are given as condition in the tables of related parameters.

Key
1 PMA implementation
V differential voltage between CAN_H and CAN_L wires
Diff
V single-ended voltage on CAN_H wire
CAN_H
V single-ended voltage on CAN_L wire
CAN_L
C capacitive load on RXD
RXD
C optional split-termination capacitor
C differential capacitive load
R differential load resistance
L
Figure 2 — HS-PMA test circuit
5.3 Static parameter
5.3.1 Maximum ratings of V , V and V
CAN_H CAN_L Diff
Table 2 specifies upper and lower limit static voltages, which can be applied to CAN_H and CAN_L without
causing damage, while V stays within in its own maximum rating range.
Diff
Table 2 — HS-PMA maximum ratings of V , V and V
CAN_H CAN_L Diff
Value
Parameter description Notation
Min. Max.
[V] [V]
a
Maximum rating V −5,0 +10,0
Diff
V ,
CAN_H
General maximum rating −27,0 +40,0
V
CAN_L
V ,
CAN_H
Optional: Extended maximum rating −58,0 +58,0
V
CAN_L
a
This is required regardless whether general or extended maximum rating for V and V is fulfilled.
CAN_H CAN_L
Applies to HS-PMA implementation powered and unpowered conditions. Applies to transmit data input de-
asserted and transmit data input (TXD) becomes asserted while CAN_H or/and CAN_L connected to a fixed
voltage.
The maximum rating for V excludes that all combinations of V and V are conforming to this
Diff CAN_H CAN_L
document. V = V − V , see Figure 2.
Diff CAN_H CAN_L
5.3.2 Recessive output characteristics, bus biasing active
Table 3 specifies the recessive output characteristics when bus biasing is active.

Table 3 — HS-PMA passive recessive output characteristic, bus biasing active
Value
Parameter Notation
Min. Nom. Max.
[V] [V] [V]
a
Single-ended output voltage on CAN_H V +2,0 +2,5 +3,0
CAN_H
b
Single-ended output voltage on CAN_H V +2,137 +2,5 +2,887
CAN_H_rec
a
Single-ended output voltage on CAN_L V +2,0 +2,5 +3,0
CAN_L
b
Single-ended output voltage on CAN_L V +2,137 +2,5 +2,887
CAN_L_rec
a, b
Differential output voltage V −0,5 0 +0,05
Diff
NOTE The requirements in this table apply concurrently. Therefore, not all combinations of V and V are conforming
CAN_H CAN_L
with the defined differential output voltage.
a
Measurement setup according to Figure 2 (including implementations with selective wake-up function):
R > 10 Ω (not present)
L
C = 0 pF (not present)
C = 0 pF (not present)
C = 0 pF (not present)
RXD
b
Measurement setup according to Figure 2:
R = 60 Ω (tolerance ≤ ±1 %)
L
C = 0 pF (not present)
C = 0 pF (not present)
C = 0 pF (not present)
RXD
5.3.3 Recessive output characteristics, bus biasing inactive
Table 4 specifies the recessive output characteristics when bus biasing is inactive.
Table 4 — HS-PMA passive recessive output characteristic, bus biasing inactive
a
Value
Parameter Notation
Min. Nom. Max.
[V] [V] [V]
Single-ended output voltage on CAN_H V −0,1 0 +0,1
CAN_H
Single-ended output voltage on CAN_L V −0,1 0 +0,1
CAN_L
Differential output voltage V −0,2 0 +0,2
Diff
NOTE See 5.5.6 to determine when bias is inactive.
a
Measurement setup according to Figure 2:
R > 10 Ω (not present)
L
C = 0 pF (not present)
C = 0 pF (not present)
C = 0 pF (not present)
RXD
5.3.4 Dominant output characteristics
Table 5 specifies the output characteristics during dominant state. Figure 3 illustrates the voltage range for
the dominant state.
Table 5 — HS-PMA dominant output characteristics
a
Value
b
Parameter Notation Condition
Min. Nom. Max.
[V] [V] [V]
Single-ended voltage on CAN_H V +2,75 +3,5 +4,5 R = 50 Ω to 65 Ω
CAN_H L
Single-ended voltage on CAN_L V +0,5 +1,5 +2,25 R = 50 Ω to 65 Ω
CAN_L L
Differential voltage on normal bus load V +1,5 +2,0 +3,0 R = 50 Ω to 65 Ω
Diff_nom L
Differential voltage on effective resistance Not
V +1,5 +5,0 R = 2 240 Ω (See NOTE)
Diff_arb L
during arbitration defined
Optional: Differential voltage on extended
V +1,4 +2,0 +3,3 R = 45 Ω to 70 Ω
Diff_ext L
bus load range
NOTE Assuming a maximum R of 70 Ω, this scenario covers a 32-node network (2 240 Ω/70 Ω = 32), 2 240 Ω is emulating a
L
situation with up to 32 nodes transmitting dominant value simultaneously. In such case, the effective load resistance for single
nodes decreases (a node does drive only a part of the nominal bus load).
a
Requirements given in this table apply concurrently. Therefore, not all combinations of V and V are conforming
CAN_H CAN_L
with the defined differential voltage (see Figure 3).
b
Measurement setup according to Figure 2:
C = 0 pF (not present)
C = 0 pF (not present)
C = 0 pF (not present)
RXD
Key
1 range of V
CAN_H(dom)
V differential voltage between CAN_H and CAN_L wires
Diff
V single-ended voltage on CAN_H wire
CAN_H
V single-ended voltage on CAN_L wire
CAN_L
Figure 3 — Voltage range of V during dominant state of CAN node, when V varies from
CAN_H CAN_L
minimum to maximum voltage level (50 Ω to 65 Ω bus-load condition)

5.3.5 Maximum driver output current
Table 6 specifies the maximum HS-PMA driver output current.
Table 6 — Maximum HS-PMA dominant driver output current
a
Value
Parameter Notation Condition
Min. Max.
[mA] [mA]
Absolute current on CAN_H I not specified 115 −3 V ≤ V ≤ +18 V
CAN_H CAN_H
Absolute current on CAN_L I not specified 115 −3 V ≤ V ≤ +18 V
CAN_L CAN_L
NOTE It is expected that the implementation does not stop driving its output dominant when the differential voltage between
CAN_H and CAN_L is outside the limits given in the condition column. The minimum output current limitation is implicitly
specified in Table 5 and thus can be expected to be above 30 mA.
a
Measurement setup according to Figure 2:
R > 10 Ω (not present)
L
C = 0 pF (not present)
C = 0 pF (not present)
C = 0 pF (not present)
RXD
5.3.6 PMA static receiver input characteristics, bus biasing active and inactive
Table 7 specifies the static voltage range for the HS-PMA receiver, when the bus biasing is active.
Table 7 — HS-PMA receiver static input characteristics, bus biasing active
a
Value
Parameter Notation Condition
Min. Max.
[V] [V]
Recessive state differential input voltage −12,0 V ≤ V ≤ +12,0 V
CAN_L
V −8,0 +0,5
Diff
range
−12,0 V ≤ V ≤ +12,0 V
CAN_H
Dominant state differential input voltage −12,0 V ≤ V ≤ +12,0 V
CAN_L
V +0,9 +8,0
Diff
range
−12,0 V ≤ V ≤ +12,0 V
CAN_H
a
Measurement setup according Figure 2:
R > 10 Ω (not present)
L
C = 0 pF (not present)
C = 0 pF (not present)
C = 0 pF (not present)
RXD
NOTE A negative differential voltage can temporarily occur when the HS-PMA is connected to a medium in which common
mode chokes or unterminated stubs or both are present. The maximum positive differential voltage can temporarily occur
when the HS-PMA is connected to a medium while more than one HS-PMA is sending dominant and concurrently a ground shift
between the sending HS-PMAs is present.
Table 8 specifies the static voltage range for the HS-PMA receiver, when the bus biasing is inactive.

Table 8 — HS-PMA receiver static input characteristics, bus biasing inactive
a
Value
Parameter Notation Condition
Min. Max.
[V] [V]
Recessive state differential input −12,0 V ≤ V ≤ +12,0 V
CAN_L
V −8,0 +0,4
Diff
voltage range
−12,0 V ≤ V ≤ +12,0 V
CAN_H
Dominant state differential input −12,0 V ≤ V ≤ +12,0 V
CAN_L
V +1,15 +8,0
Diff
voltage range
−12,0 V ≤ V ≤ +12,0 V
CAN_H
a
Measurement setup according Figure 2:
R > 10 Ω (not present)
L
C = 0 pF (not present)
C = 0 pF (not present)
C = 0 pF (not present)
RXD
NOTE A negative differential voltage can temporarily occur when the HS-PMA is connected to a medium in which common
mode chokes or unterminated stubs or both are present. The maximum positive differential voltage can temporarily occur
when the HS-PMA is connected to a medium while more than one HS-PMA is sending dominant and concurrently a ground shift
between the sending HS-PMAs is present.
5.3.7 Receiver input resistance
Figure 4 shows an equivalent circuitry of the HS-PMA internal differential input resistance. Table 9 specifies
the HS-PMA receiver input resistance parameter. Table 10 specifies the HS-PMA receiver input resistance
matching parameters.
Key
1 PMA implementation
2 V (see Table 3)
CAN
Figure 4 — HS-PMA internal differential input resistance

Table 9 — HS-PMA receiver input resistance
Value
Parameter Notation Condition
Min. Max.
[kΩ] [kΩ]
a
Differential internal resistance R 12 100
Diff_pas_rec
−2 V ≤ V
CAN_L
R
SE_pas_rec_H
V ≤ +7 V
Single-ended internal resistance 6 50
CAN_H
R
SE_pas_rec_L
a
R = R + R .
Diff_pas_rec SE_pas_rec_H SE_pas_rec_L
Table 10 — HS-PMA receiver input resistance matching
Value
Parameter Notation Condition
Min. Max.
V , V :
CAN_L CAN_H
a
Matching of internal resistance m −0,03 +0,03
R
+5 V
a
The matching shall be calculated as m = 2 × (R − R )/(R + R ).
R SE_H SE_L SE_H SE_L
5.3.8 Maximum leakage currents of CAN_H and CAN_L
An unpowered HS-PMA implementation shall not disturb the communication of other HS-PMAs that are
connected to the same medium. Table 11 specifies the HS-PMA maximum leakage currents.
Table 11 — HS-PMA maximum leakage currents on CAN_H and CAN_L, unpowered
Value
Parameter Notation
Min. Max.
[µA] [µA]
I ,
CAN_H
Leakage current on CAN_H, CAN_L −10 +10
I
CAN_L
V = 5 V, V = 5 V, all supply inputs are connected to GND.
CAN_H CAN_L
Positive currents are flowing into the implementation.
5.4 Dynamic parameter
5.4.1 Driver symmetry
In order to achieve a level of RF emission that is acceptably low, the transmitter shall meet the driver signal
symmetry as specified in Table 12.

Table 12 — HS-PMA driver symmetry
c
Value
Parameter Notation
Min. Nom. Max.
a
Driver symmetry based on V V +0,9 +1,0 +1,1
CC Sym_vcc
b
Driver symmetry based on V V +0,9 +1,0 +1,1
rec_sum Sym_vrec
a
V = (V + V )/V , with V being the power supply of the transmitter
Sym_vcc CAN_H CAN_L CC CC
b
V = (V + V )/V , without V reference
Sym_vrec CAN_H CAN_L rec_sum CC
V = V + V
rec_sum CAN_H_rec CAN_L_rec
V and V shall be observed during dominant state and recessive state and also during the transition
Sym_vcc Sym_vrec
from dominant to recessive and vice versa, while TXD is stimulated by a square wave signal with a frequency
that corresponds to the highest bit rate for which the HS-PMA implementation is intended, however, at most
1 MHz (2 Mbit/s) (HS-PMA in normal-power mode).
c
Measurement setup according to Figure 2:
R = 60 Ω (tolerance ≤ ±1 %)
L
C = 4,7 nF (tolerance ≤ ±5 %)
C = 0 pF (not present)
C = 0 pF (not present)
RXD
5.4.2 Optional transmit dominant timeout
An implementation of an HS-PMA may limit the duration of dominant transmission. This allows other CAN
nodes to continue communication when the TXD input at one or multiple nodes is permanently asserted. The
HS-PMA implementation should implement a timeout. Table 13 recommends the optional HS-PMA transmit
dominant timeout value range.
Table 13 — Optional HS-PMA transmit dominant timeout
a
Value
Parameter Notation
Min. Max.
[ms] [ms]
a
Transmit dominant timeout t 0,8 10,0
dom
a
A minimum value of 0,3 ms is accepted for legacy implementations.
NOTE There is a relation between the t minimum value and the minimum bit rate. A t minimum value of
dom dom
0,8 ms accommodates 17 consecutive dominant bits at bit rates greater than or equal to 21,6 kbit/s and 36 consecutive
dominant bits at bit rates greater than or equal to 45,8 kbit/s. The value 17 reflects PMA implementation attempts to
send a dominant bit and every time sees a recessive level at the receive data input. The value 36 reflects six consecutive
error frames when there is a bit error in the last bit of the first five attempts.
5.4.3 Transmitter and receiver timing behaviour
Figure 5 defines the HS-PMA implementation timing. Table 14 specifies the HS-PMA implementation loop-
delay requirements for parameter set A, parameter set B, and parameter set C. Table 15 specifies the HS-
PMA implementation data signal timing requirements for parameter set A. Table 16 specifies the HS-PMA
implementation data signal timing requirements for parameter set B. Table 17 and Table 18 specify HS-PMA
implementation data signal timing requirements for parameter set C.

Key
t nominal bit time of the bit rates the HS-PMA supports
Bit(TXD)
Figure 5 — HS-PMA implementation timing definitions
Table 14 — HS-PMA implementation loop-delay requirement for parameter sets A, B and C
b
Value
Parameter Notation
Min. Max.
[ns] [ns]
a
Loop delay for parameter set A and parameter set B t not specified 255
Loop
a
Loop delay for parameter set C t not specified 190
Loop
Propagation delay from TXD to CAN_H/CAN_L for parameter
t not specified 80
Prop(TXD_BUS)
set C
Propagation delay from CAN_H/CAN_L to RXD for parameter
t not specified 110
Prop(BUS_RXD)
set C
a
Time span from signal edge on TXD input to the next signal edge with the same polarity on RXD output, the maximum of
delay of both signal edges shall be used.
b
Measurement setup according to Figure 2:
R = 60 Ω (tolerance ≤ ±1 %)
L
C = 0 pF (not present)
C = 100 pF (tolerance ≤ ±1 %)
C = 15 pF (tolerance ≤ ±1 %)
RXD
Measurement according to Figure 5:
The input signal on TXD shall have rise and fall times (10 %/90 %) of less than 10 ns.

Table 15 — HS-PMA implementation data signal timing requirements for parameter set A
d
Value
Parameter Notation
Min. Max.
[ns] [ns]
a
Transmitted recessive bit width variation t −65 +30
ΔBit(Bus)
b
Received recessive bit width variation t −100 +50
ΔBit(RXD)
c
Receiver timing symmetry t −65 +40
ΔREC
a
tt t
BitBus BitBus BitTXD
  
b
tt t
BitRXD BitRXD BitTXD
c
tt t
RecBit RXDBit Bus
 
The requirements in this table apply concurrently. Therefore, not all combinations of t and t are conforming with
ΔBit(Bus) ΔRec
t .
ΔBit(RXD)
d
Measurement setup according to Figure 2:
R = 60 Ω (tolerance ≤ ±1 %)
L
C = 0 pF (not present)
C = 100 pF (tolerance ≤ ±1 %)
C = 15 pF (tolerance ≤ ±1 %)
RXD
Measurement according to Figure 5:
The input signal on TXD shall have rise and fall times (10 %/90 %) of less than 10 ns.
NOTE Limits for t and t are not defined for intended use with bit rates up to 1 Mbit/s.
Bit(Bus) Bit(RXD)
Table 16 — HS-PMA implementation data signal timing requirements for parameter set B
d
Value
Parameter Notation
Min. Max.
[ns] [ns]
Transmitted recessive bit width variation a −45 +10
t
BitBus
Received recessive bit width variation b −80 +20
t
BitRXD

Receiver timing symmetry variation c −45 +15
t
∆Rec
a
tt t
BitBus BitBus BitTXD
  
b
tt t
BitRXD BitRXD BitTXD
  
c
tt t
RecBit RXDBit Bus
 
The requirements in this table apply concurrently. Therefore, not all combinations of t and t are conforming with
ΔBit(Bus) ΔRec
t .
ΔBit(RXD)
d
Measurement setup according to Figure 2:
R = 60 Ω (tolerance ≤ ±1 %)
L
C = 0 pF (not present)
C = 100 pF (tolerance ≤ ±1 %)
C = 15 pF (tolerance ≤ ±1 %)
RXD
Measurement according to Figure 5:
The input signal on TXD shall have rise and fall times (10 %/90 %) of less than 10 ns.
NOTE Limits for t and t are not defined for intended use with bit rates up to 1 Mbit/s.
Bit(Bus) Bit(RXD)
Table 17 — HS-PMA implementation data signal timing requirements for parameter set C
d
Value
Parameter Notation
Min. Max.
[ns] [ns]
Transmitted recessive bit width variation a −10 +10
t
BitBus

Received recessive bit width variation b −30 +20
t
BitRXD

Receiver timing symmetry variation c −20 +15
t
∆Rec
a
tt t
BitBus BitBus BitTXD
  
b
tt t
BitRXD BitRXD BitTXD
c
tt t
RecBit RXDBit Bus
 
All requirements in this table apply concurrently. Therefore, not all combinations of t and t are conforming with
ΔBit(Bus) ΔRec
t .
ΔBit(RXD)
d
Measurement setup according to Figure 2:
R = 60 Ω (tolerance ≤ ±1 %)
L
C = 0 pF (not present)
C = 100 pF (tolerance ≤ ±1 %)
C = 15 pF (tolerance ≤ ±1 %)
RXD
Table 18 specifies the HS-PMA implementation SIC timing and impedance for parameter set C.
Table 18 — HS-PMA implementation SIC timing and impedance for parameter set C
Value
Parameter Notation Condition
Min. Max.
a
Differential internal SIC impedance R 75 Ω 133 Ω +2 V ≤ V ≤ V – 2 V
Diff_act_rec CAN_H/L CC
(CAN_H to CAN_L)
a
Internal single-ended SIC impedance R 37,5 Ω 66,5 Ω +2 V ≤ V ≤ V – 2 V
SE_act_rec CAN_H/L CC
Start time of active signal improve- t n.a. 120 ns Measured from rising TXD edge
act_rec_start
ment phase with <5 ns slope at 50 % threshold
End time of active signal improve- t 355 ns n.a.
act_rec_end
ment phase
Start time of passive recessive phase t n.a. 530 ns Measured from rising TXD edge with
pas_rec_start
<5 ns slope at 50 % threshold with
R ≥ min. R and R ≥ min. R
Diff Diff_pas_rec SE SE_
.
pas_rec
a
V may be replaced through V for devices without V access.
CC rec_sum CC
V = V + V
rec_sum CAN_H_rec CAN_L_rec
Figure 6 defines the SIC timing.

Figure 6 — SIC timing definitions
5.5 Wake-up from low-power mode
5.5.1 Wake-up procedures
When an implementation comprising one or more HS-PMAs implements a low-power mode, the HS-PMA can
signal a wake-up event. Table 19 lists the wake-up procedures for defined types of HS-PMA implementations.
Table 19 — HS-PMA wake-up implementations
Type of HS-PMA implementation Required wake-up mechanism
Without low-power mode No wake-up
With low-power mode, but without selective wake-up Either basic wake-up or wake-up pattern
(WUP) wake-up
With selective wake-up Selective wake-up frame (WUF) and
wake-up pattern (WUP) wake-up
5.5.2 General requirement
In case more than one wake-up procedure is implemented in an HS-PMA, the wake-up procedure to be used
shall be configurable.
5.5.3 Basic wake-up
After having received a dominant state for the duration of at least t , the HS-PMA shall detect a wake-up.
Filter
5.5.4 Via wake-up pattern
Upon receiving two dominant states of at least t , separated by at least one recessive state with a
Filter
duration of t , a wake-up shall happen if these phases of bus states complete within t . This method is
Filter Wake
illustrated in Figure 7.
Key
1 INI state
2 state A
3 state B
4 state C: wake-up detected, entering this state shall signal the bus wake-up event
5 wait state
6 transition from other modes option a)
7 power-on option b)
Figure 7 — WUP3: Wake-up finite state machine
The finite state machine in Figure 7 specifies the wake-up behaviour for all operation modes. When entering
state A the optional timer, t , shall be reset and when entering the Wait state the t timer shall be
Wake Filter
reset. Table 20 specifies the wake-up control timings and Figure 8 defines the wake-up reaction time.

Table 20 — PMA voltage wake-up control timings
Value
Parameter Notation Condition
Min. Max.
[µs] [µs]
a
CAN activity filter time, long t 0,5 5,0 Bus voltages shall be as specified in
Filter
Table 8.
b
CAN activity filter time, short t 0,15 1,8 Bus voltages shall be as specified in
Filter
Table 8.
Wake-up timeout t 800,0 10 000,0 Optional timer
Wake
Wake-up pattern signalling t not defined 250,0 Measured from the completed wake-
Flag
up pattern, see Figure 8
a
Implementations do not need to meet this timing, in case the “CAN activity filter time, short” is met. It should be noted
that the maximum filter time has an impact to the suitable wake-up pattern, especially at high bit rates. In case the HS-PMA
implementation implements low-power mode(s), then a wake-up mechanism, in a 500 kbit/s network, a wake-up pattern shall
carry at least three similar bit levels in a row in order to safely pass the wake-up filter. Shorter filter time implementations can
increase the risk for unwanted bus wake-ups due to noise. The specified range is a compromise between robustness against
unwanted wake-ups and freedom in frame selection.
b
Implementations do not need to meet this timing, in case the “CAN activity filter time, long” is met.

a) Correct wake-up pattern with PMA low-power mode
b) Incorrect wake-up pattern, dominant phase longer than t
Wake
c) Incorrect wake-up pattern, recessive phase longer than t
Wake
Key
1 INI state
2 in state A
3 in state B
4 in state C
5 in wait state
6 in low-power mode
7 wake-up detected
8 wake-up flagged
Figure 8 — WUP3: Wake-up reaction time

5.5.5 Selective wake-up
5.5.5.1 General
Upon detection of a wake-up frame (WUF), a wake-up event shall happen. Decoding of CAN frames in either
classical base frame format (CBFF) or classical extended frame format (CEFF) and acceptance as a WUF is
done by the HS-PMA. If enabled, decoding of CAN frames shall be possible in normal-power mode and low-
power mode. The acceptance procedure is described in detail in the following subclauses.
After the bias reaction time t has elapsed, the implementation may ignore up to four (or up to eight when
Bias
bit rate higher than 500 kbit/s) frames in CBFF and CEFF and shall not ignore any following frame in CBFF
and CEFF.
In case of erroneous communication, the HS-PMA shall signal a wake-up upon or after an overflow of the
internal error counter.
5.5.5.2 Behaviour during transitions between normal-power mode to low-power mode
If selective wake-up is enabled prior to the mode change and the HS-PMA is not anymore ignoring frames,
decoding of CAN data frames and CAN remote frames shall also be supported during mode transitions,
which have the frame detection functionality enabled. If the received frame is a valid WUF, the transceiver
shall indicate a wake-up. If enabled, decoding of CAN data shall be possible in normal-power mode and low-
power mode.
5.5.5.3 Bit decoding
A received classical CAN frame shall be decoded correctly when the timing of the differential voltage
between CAN_H and CAN_L conforms with one of the two following types of signals:
— the bit stream consists of multiple instances of the signal shape A
...